JPS6294024A - C-r type digital/analog converter - Google Patents

Abstract

PURPOSE:To attain D/A conversion with high accuracy by using a C array type D/A converter with less voltage dependency to apply D/A conversion to a high-order bit of digital input. CONSTITUTION:The data of a high-order bit of a digital data input is supplied to the C array type D/A converter 31, where the data is D/A-converted and a data of a low-order bit of the digital data is D/A-converted by an R type D/A converter 32, the output point of the R type D/A converter 32 and the output point of the C array type D/A converter 31 are coupled by capacitance coupling means 33 to extract a D/A conversion output from the output point of the C array type D/A converter 31. Each capacitor constituting the converter 31 is set to the same capacitance and the output of a decoder receiving a high- order bit digital data is fed to each capacitor so as to apply charge/discharge control.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D/A (default/analog) converter used in various electronic devices, and particularly to a C-R type D/A converter using a capacitor array and a resistor group.

[Technical background of the invention and its problems]

The circuit format of the D/A converter is (a) an R-2R ladder circuit using a resistor network, (b) an IJ-W circuit using a resistor string, (e) a C array type circuit using a capacitor array, (d) A C-C type circuit that combines two sets of capacitor arrays, and (s) a C-R type circuit that combines a C array type circuit and a tree type circuit.

When the R-2R ladder circuit in (a) above is realized using a MOS process, if an ion implanted resistor is used, the resistance value changes due to the piezoelectric effect, resulting in poor D/A conversion accuracy. , the disadvantage is that the number of bits that can be handled is small, about 6 bits. Furthermore, when a diffused resistor or a polysilicon resistor is used, since the resistance value thereof is small, the switch must be controlled by digital input, and good conversion accuracy cannot be obtained unless the resistance of the switch element is made extremely small. However, it is difficult to extremely reduce the resistance of the switch element, and it is difficult to achieve high accuracy.

Furthermore, the tree-type circuit in (b) requires m=2T' resistors when the number of bits handled is n, and the MOS
When converting into an LSI, if the number of bits is large, the area occupied by the chip becomes very large, and the manufacturing cost becomes high.

Further, the C array type circuit in (c) above is a MOS LSI
(Capacitors have the advantage of increasing accuracy because they have no voltage dependence, but since there is a limit to the minimum capacitance value, the capacitance value of the upper bits that are sequentially weighted becomes very large as the number of bits handled increases.) This increases the area occupied by the chip and increases the manufacturing cost.

In addition, in the C-C type circuit of (d) above, as shown in FIG. A coupling capacitor Ce is connected between the outputs of the two. Here, 81 to SL are switch elements connected corresponding to capacitor arrays 01 to Ct (capacitance values are C to 2t-1・C) for lower bits v1 to Vt of the digital input, St++ to St+ □ is the capacitor array C, ~C et for the upper bits V ~ v of the digital input.
+1 t+m (capacitance value is 0 to 2m-1・C), and these switch elements S, ~St+
□ is “1” of each corresponding input bit v, ~vt+□
0'', the reference voltage vRffiF source is connected to the ground terminal GND. If the coupling capacitor Cc or the capacitance Ceff looking at the capacitor array of the lower bit is matched to the minimum capacitance value C of the capacitor array, the output ' Voltage V.UT
is 2 L+m (Vk: 1 or O), and a linear D/A conversion characteristic is obtained as shown in FIG. 7(b). However, as described above, it is difficult to match Ceff and C because the capacitance value of the coupling capacitor C is not an integral multiple of the minimum capacitance value of the capacitor array.

Further, the C-R type circuit (@) is a combination of a C array type circuit and a tree type circuit connected together as shown in FIG. 8(a). Here, switch elements S, to SM. teeth,
Resistor strings R, ~R. in a tree-type circuit. The resistors R1 to RM are connected between the reference voltage vREF source and the ground leakage GND. There is. On the other hand, the switching elements T1 to TN connect one end of each of the capacitors C1 to CN of the capacitor array in the C array type circuit to the reference voltage vRoF source, GND, ! I? ! :P is to be switched and connected to any of the output nodes. These switch elements S, ~5M-4, T, and ~TN are switch-controlled as shown in FIG. 8(b) in response to digital inputs. That is, the switch elements S, ~5M-1 are controlled to selectively conduct as the lower bit of the digital input becomes larger, and the switch elements T, ~TN become more conductive as the higher bit of the digital input becomes larger. Control is performed so that the switching element T1 corresponding to the smaller bit becomes conductive in order from the switching element T1 corresponding to the bit having the largest weight to the switching element TH corresponding to the bit having the largest weight. Further, the switch element V is V of a C array type circuit. It is connected between the UT output point and GND, and is controlled to be temporarily conductive before starting the D/A conversion operation.

Therefore, when 5j (1≦j≦M-1) of the switching elements 81 to 5M-1 is now conductive, Vs, 8Pt
The pressure is 4... (3) vsrx
At this time, T1 to Tt, -4 of the switching elements T, to TN are connected to the VREF power supply, TL is connected to the vSTEP output node, and Tt+1 to TN are connected to the G
If connected to ND, capacitor array C1~
CN output voltage V. tlA is. Here, C8-2
・The capacitor array C7 which is set to co
Assuming that the capacitance value of CN is binary weighted, 1=1. By the way, the above equation (7) expresses the nonlinear D/A conversion characteristic as shown in FIG. S (b). However, such nonlinear characteristics are used for special purposes, such as PCM encoders and decoders (C0DEC) in PCM transmission terminal equipment, and are not applicable when linear D/A conversion characteristics are required. In this case, the more C-R type circuit shown in FIG. 8(a) cannot be used.

MO8L eliminates the above-mentioned drawbacks, provides high-precision D/A conversion characteristics, and can be made smaller and cheaper.
A C-R type D/A converter suitable for SI has been proposed in Japanese Patent Application No. 1983-379t1 by the present applicant. However, even in this D/A converter, there is room for improvement regarding monotonically increasing output levels and errors in converted outputs due to manufacturing variations in capacitors.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to achieve high monotonous increase in output level, small error in conversion output, and high-precision D/A conversion characteristics. , C-R type D/A suitable for MO8LSI
The purpose of the present invention is to provide a converter.

[Summary of the invention]

That is, the C-R type D/A converter of the present invention converts the upper bit data of the digital data input into a D/A converter using the C array type D/A converter, and converts the lower bit data of the digital data input into a D/A converter. The data is converted into D/A f by an R type/Aq converter, and the output point of the R type D/A converter and the C array type D
/A converter output point is capacitively coupled, C array type /A
The D/A conversion output is taken out from the output point of the converter, and each capacitor making up the above C array type D/A converter is set to the same capacitance value, and the upper bit of the upper bit is connected to each capacitor. Charging and discharging is controlled by supplying the full output of the decoder that receives digital data.

Therefore, according to the above C-R type D/A converter.

When implemented as a MOS LSI, the high-order bit data of the digital input is D/A converted by a C array type D/A converter with low voltage dependence, making it possible to perform highly accurate D/A conversion. Further, the above C array type D/A converter has N
When performing D/A conversion of bits, since it is composed of two capacitors with the same capacitance value, monotonous increase is guaranteed, and variations in capacitance value during the manufacturing of each capacitor are canceled out between each capacitor. Therefore, the error in the conversion output is also small.

[Embodiments of the invention]

The present invention will be described in detail below with reference to one drawing.

FIG. 1 shows the basic configuration of the present invention, where 31 is a C array type D/A converter for D/A converting the upper bit data f of the digital data input, and 32 is a C array type D/A converter for D/A converting the upper bit data f of the digital data input. R type (R-2R ladder type or resistor string type) for D/A conversion of lower bit data
The D/A converter 33 is a capacitor supply means for superimposing the output of the R type D/A converter 32 on the output of the C array type/A converter 53; /A converter 3
Analog output voltage V from . I try to make UT good.

Next, one embodiment of the present invention will be described in detail.

In Fig. 2, No. 3 is an N-bit C array type D/A converter, and this D/A converter 31 has capacitors C and C of 2N41i (N is the number of upper bits) having the same capacitance value. Consists of ,... Above capacitor C, C,・
One electrode of ... is commonly connected.

The other electrode has digital data DAIn (upper pin) D.
,,D2. ...DN) of the decoder 34 that can supply the output 0. , 02. ...02□ is supplied. The decoder 34 is shown in FIGS. 3(a) and 3(b).
ttC, binary code input, D2. ...,
Decode DN and output O1, 0□, ..., 0□8-
1. If you get everything, you can input it, D2. ...
l Output when all DNs are on: 01, 0□,...”
2N-1 is all ``O'', human power 1), , D2.・
..., DN is ro, o, ..., 1", output 01
,0□,..." 2N-1 is ro, o,...,1"
, Dl, D2. ...DN is ro, o, ..., 1.
In the case of OJ, the output o , o , ..., 0□, is r
o, o,...

1.1'', D, , D2. ..., DN is ro, o,
....

1.1" output O9, 0□,..., O□N-1
is ro, o, ..., 1, 1. Becomes I.J. This can be expressed using arithmetic symbols as shown below.

02N-+ = DN +DN-1+ DN-2+DN
zu+...+D.

O□N-2= DN-++DN-2+DN-3+・
・・+D1O□N-5=DN ” DN-1+ DN
-2+D? J-s+...10.

2N-4DH-2+DN-s+...+D1O□N-5
= (DN+D,,) X DN, + DN, ten... ten.

0°N-6= DN-, x DN,, 10 DN-,
+...+D.

0,,N, =pNX DN, X D, 2+DN,
+-+D.

2N-8DN-s+...10.

01=DNXDN, XDN, XDN, X...×D.

That is, the digital data is a binary code, and the output of the decoder 34 is 0. Of (1≦l≦2N-1), '11
The number of decoder outputs that become ' is equal to the number represented by the binary code. Therefore, the number of decoder outputs X1 that is '1' is expressed by the following equation (8).

Xl-Σ21-1・D...(8
)1=1 By the way, the output of C array type D/A converter 3 is “1
Since it is proportional to the number of decoder outputs, even if this C
Each capacitor C constituting the array type D/A converter 3,
Even if there are variations in the fIk values of C, . . . , the monotonically increasing property of the output level is maintained.

On the other hand, 32 is an M-bit R type D/A converter;
The A f converter 32 is connected in series between the power supply vDD and the ground point GND, and has resistors R1R2... having the same resistance value, and connecting points of these resistors R, R,... as a capacitance supply means. Switches sw and sw connected between one electrode of the capacitor C.

It consists of... The capacitance value of the capacitor C is as follows:
,C,..., and the other electrode of the capacitor C is
These are connected to the negative electrodes of the capacitors C, C, . . . , respectively. The above switches sw, sw, . . . each have digital data DAI.

Outputs 01',...0□,' of the decoder 35 to which (lower bits DN+1...l DN-1-M) are supplied
is supplied. The decoder 35 receives digital data D.
Lower pi of AIn) DN+11..., DN+1
is decoded, and the decoder output 0. is represented by the digital data of the lower bits. ' (1≦i≦2M) only''
1''. Therefore, the output of the R-type D/A converter 32 is proportional to the following equation (9).

2'-" DN+M- (,Σ i+1')72M...(9)
The output of the R-type D/A converter 32 is connected to the coupling capacitor C
Since it is superimposed on the output of the C array type Δ converter 31, the weight for the C array type D/A converter 31 is 17.
It becomes 2N. Therefore, the D/A conversion output DAO of this circuit
ut is expressed by the following formula α1.

Now, the maximum value of the conversion output in the circuit shown in FIG.
”, the output of C array type D/A converter 3 is 0ut.
l is expressed by the following formula α.

1, the output 0ut2 of the R type D/A converter 32 becomes, but due to the coupling capacitor Ce, υC7 Ray type I)/A
Since it is superimposed on the output of converter 3, the D/A of the entire circuit
Viewed from the conversion output DAOut, it becomes 1//2N. Therefore, ut2 DAOuj = Outl + − N.

In addition, in FIG. 2, it is a 3ON'i inbegence converter. In addition, switch U5. U2 is D/A
Necessary to discharge the capacitor after the conversion has taken place.

FIG. 4 shows an example of the configuration of the decoder 34.
Figure a) is a circuit configuration diagram, and Figures (b) to (6) are diagrams for explaining the symbols shown in Figures (, l), respectively.

Upper bit of digital data) D, (Lowest bit M
SB) to DN (most significant bit LSB) are selectively supplied to each dart of a complementary logic setting MOS transistor group 36.

Then, a predetermined logic is set by the MO8) runnostar group 36, and the inverter circuit 37°37.37.
Output signal 02N-1"2N-2'ON via...
,... is now obtained. The relationship between this input and output is as shown in FIG. 3(b).

FIG. 5 shows the decoder, ? This circuit is for explaining another configuration example of 4. In this circuit, the logic setting section is configured by a single channel (N channel) type MOS transistor group 38, and its operation is synchronized with the clock signals φ and φ2. I'm letting you go. In FIG. 5, (a) is a circuit configuration diagram, (b) and (a) are diagrams for explaining the symbols shown in (a), respectively, and (d) is a clock signal φ! It is a figure showing the relationship between and φ2. In other words, the digital data D, ~DN are input to the OR circuits 39, 39°39, .
... is supplied to one input terminal of this OR circuit 39.3
9.39. The clock signal φ1 is connected to the other input terminal of
is supplied. The above OR circuit 39. 39, 39. ...
The outputs are supplied to each r-1 of logic setting MOS transistors #38. On the other hand, above! A link No. 1g φ2 is supplied to one end of the S transistor group 38, respectively.

It was a cabinet. The NOR circuits 40, 40, 40 . ... is connected, and an inverted signal of the clock 1g φl is connected
P-channel type MOS transistors 41, 41, 41 . A power supply vDD is connected via... The above NOR circuit 40°4θ, 40. A clock signal φ is supplied to the other input terminal of the . and,
NOR circuit 40°4θ, 40. ...output o2N,
, o□N-2, o□1°..., 01 are obtained. Here, the input of digital data D, ~D and the output 0. 0
．． 0...,0. and N2N-12N-22N-
5' is as shown in FIG. 3(b).

Incidentally, the decoder 35 in FIG. 2 may also have basically the same configuration as the +mth or -th circuit shown in FIG.

According to such a configuration, even if there are variations in the capacitance values of the capacitors C, C, . Moreover, since the capacitance values of the capacitors C1C2, . . . are the same, even if variations occur during manufacturing, the variations are canceled out by each other, so that a highly accurate output can be obtained.

FIG. 6 shows another embodiment of the present invention, in which an R-2R ladder resistor network 42 is used as the R type/Az converter 32 in FIG. In FIG. 6, the same components as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

In the above configuration, the digital data DAI, the data of the low-order bit, are connected in series between one electrode of the coupling capacitor C and the ground point via a resistor with a resistance value of 2R. . . , is supplied to each resistance connection point of 2R. Of course, even in such a configuration, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As explained above, according to the C-R type D/A converter of the present invention, the monotonically increasing output level is high, the error in the conversion output is small, and highly accurate D/A conversion characteristics can be obtained.
It is suitable for OS LSI and can be widely used in measurement control equipment, car electronics equipment, medical electronics equipment, transmission communication equipment, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a C-R type D/A converter according to the present invention, and FIG.
A circuit diagram showing one embodiment of the A converter, FIG. 3 is a diagram for explaining the relationship between the decoder's human power and output in the circuit of FIG. 2 above, and FIGS. 6 is a circuit diagram showing another embodiment of the present invention, and FIG. 7 is a conventional C-C type D/A converter. Diagram to explain, No. 8
The figure is a diagram for explaining a conventional C-R type D/A converter. 3I...C array type D/A converter, 32...R type D
/A converter, 33... Capacity supply means, 34, 35.
...Decoder, DAIn...Digital data, D input Q
ut0.・Analog output, C, C, ... Capacitor group. Applicant's agent Patent attorney Takehiko Suzue (a) Figure 7<b) (a) , 8 Figures

Claims (5)

[Claims] (1) A C array that includes a group of capacitors that have the same capacitance value and have one electrode connected in common, and a decoder that receives upper bit data of digital data and selectively controls charging and discharging of the capacitor group. type D/A converter, an R type D/A converter into which the lower bit data of digital data is input, and an output point of this R type D/A converter and the C array type D/A converter. A C-R type D/A, comprising a capacitive coupling means disposed between the C-array type D/A converter and the output point, and configured to obtain an analog output from the output point of the C-array type D/A converter. converter. (2) The R-type D/A converter has a first potential supply source and a second potential supply source.
A group of resistors connected in series with a potential supply source, a group of switch elements respectively disposed between each connection point of these resistor groups and the capacitance supply means, and data of lower bits of digital data. 2. The C-R type D/A converter according to claim 1, further comprising a decoder which receives an input signal and selectively controls switching of said switch element group. (3) The C-R according to claim 1, wherein the R-type D/A converter is composed of an R-2R ladder resistor network into which data of lower bits of digital data is input. type D/A converter. (4) The decoder outputs a number of "1" levels equal to the number expressed in binary code as digital data, according to claim 1 or 2. C-R type D/A converter. (5) The C-R according to claim 1, wherein the capacitive coupling means comprises a capacitor having a capacitance equal to that of each capacitor of the capacitor group of the C-array type D/A converter. type D/A converter.