JPS5946052A - Resin seal insulated type semiconductor device - Google Patents
Resin seal insulated type semiconductor deviceInfo
- Publication number
- JPS5946052A JPS5946052A JP15642082A JP15642082A JPS5946052A JP S5946052 A JPS5946052 A JP S5946052A JP 15642082 A JP15642082 A JP 15642082A JP 15642082 A JP15642082 A JP 15642082A JP S5946052 A JPS5946052 A JP S5946052A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- radiating plate
- heat sink
- thin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 25
- 229920005989 resin Polymers 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000009413 insulation Methods 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 2
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010445 mica Substances 0.000 description 2
- 229910052618 mica group Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 244000175448 Citrus madurensis Species 0.000 description 1
- 235000017317 Fortunella Nutrition 0.000 description 1
- 241000981595 Zoysia japonica Species 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はトランジスク、ダイオード、ザーｒリスタ、
トライアック等の半導体素子のケース及びリードフレー
ムの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION This invention relates to transistors, diodes, ZARristors,
The present invention relates to the structure of a case and a lead frame of a semiconductor device such as a triac.
半導体素子は電流を流すことにより内部より発熱しその
熱を外部へ逃がす心安から放熱板と呼ばれる熱放散の良
い材料を用いて直接ラジェターへネジで取付けて使用し
ている。この際ラジェターは素子放熱板は電気的にｖｆ
−電位になるのでラジェターを絶縁させて使用必要のあ
る場合にはラジェターを直接回路を絶縁するか、素子と
ラジェターをマイカ等で絶縁する必要があった。この為
に素子の取付時に時間と材料が余分に必要であり素子自
体で絶縁された構造のものが要求されてきた。Semiconductor elements generate heat from inside when current is passed through them, and for the safety of dissipating that heat to the outside, a material with good heat dissipation called a heat sink is used, and it is attached directly to the radiator with screws. At this time, the radiator element heat sink is electrically VF
- potential, so if it was necessary to insulate the radiator and use it, it was necessary to insulate the radiator directly from the circuit, or to insulate the element and the radiator with mica or the like. For this reason, extra time and materials are required when mounting the element, and a structure in which the element itself is insulated has been required.
素子自体絶縁＋１り造とする方法は半導体チップと放熱
板の間を絶縁する方法と放熱板を外部と絶縁する方法の
２種類があるが前者においては部品１組立の為の時間等
がかかｐ後者の方が望ましい、 １〜かし、製法として
は薄い絶縁層を均一に放熱板に設けなければならずかな
り歩留、精度等円４°・Ｉ「を伴う。There are two ways to insulate the element itself + 1 structure: one is to insulate between the semiconductor chip and the heat sink, and the other is to insulate the heat sink from the outside, but the former takes time to assemble one part, and the latter It is more desirable to use 1 to 1. However, the manufacturing method requires that a thin insulating layer be uniformly provided on the heat sink, which results in a considerable yield and accuracy of 4°·I.
この発明では素子自体を放熱板と外部との間で絶縁する
為に要易な製法を得る為の構造を提供するものである。The present invention provides a structure that allows an easy manufacturing method to insulate the element itself between the heat sink and the outside.
本発明においては以上述べた欠点を解決する為樹脂封止
絶縁型半導体装置の封入金型、に入る部分の放熱板をあ
らかじめ放熱板と外部ラジェターの絶縁層を形成する曹
い樹脂部と反対方向に１０〜１００曲げた放熱板を用い
封入金型に挿入し７だ後絶縁層を形成する部分と反対側
の厚い樹脂部の方向より放熱板を修正するピン穴を設け
、かつ絶縁層を形成する薄い樹脂部の外部リードの中央
部より（ＩＪ脂油注入口設けた素子構造とする、。In the present invention, in order to solve the above-mentioned drawbacks, the heat dissipation plate of the part that enters the encapsulation mold of the resin-sealed insulated semiconductor device is placed in the opposite direction to the carbon resin part that forms the insulating layer of the heat dissipation plate and the external radiator. A heat sink bent 10 to 100 degrees is inserted into the encapsulating mold, and after 7 days, a pin hole is made to modify the heat sink from the direction of the thick resin part on the opposite side to the part where the insulating layer is to be formed, and an insulating layer is formed. From the center of the external lead of the thin resin part (device structure with an IJ oil inlet).
この様にした素子は封入金柑ｌの中でｎ（熱板が下方へ
曲げらり、て絶縁層を形成する薄いイｐ７脂部の厚さを
正確）てコントロールすることができる。又４／ｊｔ脂
注入口を外部リードの中央部に置くことによりこの位置
より絶縁層を形成する薄い樹脂部にすきまを作ることな
く完全に樹脂を充填することができる。The device constructed in this way can accurately control the thickness of the thin layer forming the insulating layer by bending the hot plate downwards inside the encapsulated kumquat. Also, by placing the 4/jt fat inlet in the center of the external lead, the thin resin part forming the insulating layer can be completely filled with resin from this position without creating any gaps.
次に図面を用いて本発明の一実施例につき謄、明する。Next, one embodiment of the present invention will be described with reference to the drawings.
第１図、′π２図には従来の絶縁型でない半導体装置を
示しているが１７Ｆ熱板２け外部ラジェター（（取りつ
けらＪする際には別の部品としてマイカ板等を必要とし
た。第３図、ｇ＋ｒａ図は本発明の一例であるが樹脂１
が放熱板２の裏側の部分７に寸で入り込む構造となって
いる。この場合絶縁胛７の厚さは放熱板の形状、加工精
度等により変わり熱抵抗、絶縁耐圧性にバラつきを生じ
させる原因となる。又４＃脂１を充填する場合に注入口
１０をとの位置以外の場所に設けた場合は絶縁層７に均
一に充填されず樹脂のピンホール等を生じ、絶縁耐圧の
劣化につながる。そこで本発明では第５図（で示す様に
ｊｉ（ｒ ？板２を封入金型の−１−：型１０と下型１
１の間にＶ、を込み込んだ状ウリでは上方に３°稈攻曲
げてあり上型１０と下型１１を完全に締めつけて、上方
より１１＜’、 熱板固定用のピン８によ−、て下方へ
修正する、。Figures 1 and 2 show a conventional non-insulated semiconductor device, including a 17F two-piece external radiator (which required an additional component such as a mica plate to install). Figures 3 and g+ra are examples of the present invention, but resin 1
The structure is such that the heat dissipation plate 2 enters the back side portion 7 of the heat dissipation plate 2 by a short distance. In this case, the thickness of the insulator 7 varies depending on the shape of the heat sink, processing precision, etc., and causes variations in thermal resistance and dielectric strength. Further, when filling the 4# resin 1, if the injection port 10 is provided at a location other than the above position, the insulating layer 7 will not be filled uniformly, resulting in resin pinholes and the like, leading to deterioration of the dielectric strength. Therefore, in the present invention, as shown in FIG.
In the case of a shape with a V inserted between 1 and 1, it is bent upward by 3 degrees, and the upper mold 10 and lower mold 11 are completely tightened, and the pin 8 for fixing the hot plate is inserted from above by 11 −, to correct downward.
この様にするとｌｉ！ｌ ％、板２と下型１１との間（
・でできるすき寸が絶縁層７となりその）ワさは上型１
０と下型１１との加工精度で維持できる。又樹脂注入口
９を絶縁Ｒ７を形成する薄い（′７Ｉ脂？’ｔ１５の〃
［γりｌ５１）−ドの中央部より樹脂注入口を設（つる
ことによりピンホール等の樹晰充填不良を缶くすことが
できる。If you do it like this, li! l %, between plate 2 and lower mold 11 (
・The gap created by is the insulating layer 7, and its width is the upper die 1
0 and the lower die 11 can be maintained with the machining accuracy. Also, the resin injection port 9 is insulated with a thin film ('7I resin?'t15) that forms the insulation R7.
By installing a resin injection port from the center of the [γri l51)-domain, defects in tree filling such as pinholes can be eliminated.
第１図は従来の半ｙ、１９体の平面図、第２図はその横
断面図、第３図は本発明の半導体の平面図、第４図はそ
の横断面図、第５図は封入金型に挿入した際の断面図、
を示す。
なお図において、１・・・・・・樹脂部、２・・・・・
・放熱板、３・・・・・・ネジ市め用穴、４・・・・・
放熱板固定用ピン穴、５・・・・・・外部ベース用す−
ド、６・・・・・°外部エミッター用リード、７・・
・・・・絶縁用樹脂部、８・・・・・・放熱板修正用ピ
ン、９・・・・・・樹脂注入口、１０・・・・・・封入
金型上型、１１・・・・・封入金型下型、である。
代理人 弁理士 内 原 晋１□ ゛″パ手続補
正書（方式）６゛
７゜
特許庁長官 殿
１、事件の表示 昭和５７年特 許願第１５６４
２０号２、発明の名称 ＋ｊｔｔ脂封止絶ｆ≠型半導
体装置３、補正をする音
事件との関係 出 願 人東京都港区芝／
ｉ、 Ｉ’ Ｌｌ ３３番］、 、７；。
（４２３） 日本電気株式会社
代表ｈ 関本忠弘
４、代理人
”−’−’ （連絡先 ）１４＜７１しし株
式会ン１． ｔＹ：ｉ’１部）５、 １ｉｌｉ正命令の
日付
昭和５７年１１月：Ｓ Ｏ＋」（発フカ「」）補正の対
象
図面（第５図）
補正の内容
別紙のとおりFig. 1 is a plan view of a conventional half Y, 19 body, Fig. 2 is a cross-sectional view thereof, Fig. 3 is a plan view of the semiconductor of the present invention, Fig. 4 is a cross-sectional view thereof, and Fig. 5 is an enclosure. Cross-sectional view when inserted into the mold,
shows. In the figure, 1...resin part, 2...
・Radiation plate, 3... Holes for screw insertion, 4...
Pin hole for fixing heat sink, 5...For external base.
Lead, 6...°Lead for external emitter, 7...
...Insulating resin part, 8...Pin for fixing the heat sink, 9...Resin injection port, 10...Upper mold of the sealing mold, 11... ...This is the lower mold of the encapsulation mold. Agent Patent Attorney Susumu Uchihara 1□ ゛''Paper Procedural Amendment (Method) 6゛7゜ Commissioner of the Japan Patent Office 1, Indication of Case 1982 Patent Application No. 1564
No. 20 No. 2, Title of the invention +jtt fat-sealed absolute f≠ type semiconductor device 3, Relationship with the sound incident to be corrected Applicant: Shiba, Minato-ku, Tokyo /
i, I' Ll No. 33], , 7;. (423) NEC Co., Ltd. Representative h Tadahiro Sekimoto 4, Agent "-'-" (Contact information) 14 < 71 Shishi Co., Ltd. 1. tY: i' 1 part) 5, 1ili Date of formal order 1982 November 2017: Drawings subject to amendments to S O+ (Figure 5) Contents of amendments are as shown in the attached sheet.
Claims (1)
放熱板をあらかじめ放熱板と外部ラジェターの絶縁層を
形成する薄い樹脂部と反対方向に１°〜１００曲げだ放
熱板を用い封入金型に挿入した後絶縁層を形成する部分
と反対側の厚いｆ３ｖ脂部の方向より放熱板を修正する
ビン穴を設け、かつ絶縁層を形成する薄い樹脂部の外部
リードの中央部より樹脂注入口を設けた構造を特徴とす
るζ１′ｄ脂封止絶縁型半導体装置。Encapsulation equipment for resin-sealed insulated semiconductor devices. Bend the heat sink of the part that will enter the mold in advance by 1° to 100 degrees in the opposite direction to the thin resin part that forms the insulation layer of the heat sink and the external radiator. Using the heat sink, encapsulate the metal. After inserting it into the mold, make a bottle hole to modify the heat sink from the direction of the thick F3V resin part on the opposite side to the part where the insulation layer will be formed, and pour the resin from the center of the external lead of the thin resin part that will form the insulation layer. A ζ1'd fat-sealed insulated semiconductor device characterized by a structure with an inlet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15642082A JPS5946052A (en) | 1982-09-08 | 1982-09-08 | Resin seal insulated type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15642082A JPS5946052A (en) | 1982-09-08 | 1982-09-08 | Resin seal insulated type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5946052A true JPS5946052A (en) | 1984-03-15 |
Family
ID=15627358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15642082A Pending JPS5946052A (en) | 1982-09-08 | 1982-09-08 | Resin seal insulated type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5946052A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6474746A (en) * | 1987-09-17 | 1989-03-20 | Toshiba Corp | Resin-insulated semiconductor device |
-
1982
- 1982-09-08 JP JP15642082A patent/JPS5946052A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6474746A (en) * | 1987-09-17 | 1989-03-20 | Toshiba Corp | Resin-insulated semiconductor device |
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