JPS5945548A - Method and device for generating address of bit map memory - Google Patents

Abstract

PURPOSE:To minimize the capacity of a program memory so that numerous kinds of graphics can be dealt with, by using an RAM as a program memory and making the rewrite of a program possible by means of external control. CONSTITUTION:The function code of an arithmetic logic calculation circuit 4 and data and control data used at the time of calculation are stored in a microprogram memory 6 and an address and data are generated at 1-machine cycle by using one step of the program. The address and data are calculated by the circuit 4 and the result of the operation is added to a condition judging circuit 1 through a bus line, and then, a condition judge signal is generated based on the result of the calculation and the control data of the program. This signal controls a location counter 2 and LC controller 3. The location is fixed at an optional step of the microprogram and the capacity of the memory 6 is reduced, and then, address generation and operation are performed correspondingly to various graphics.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and device for generating addresses using a bit map and a map. The purpose of this is to generate addresses.

Conventionally, the address generator of the hit map memory and the L counter are used to jump to the required address, or
Since address calculation was performed using software rather than a computer, it was difficult to increase the speed at which problems occurred.

In recent years, with the large-scale 8!8 stacking of memories, bit map memories have become more quantifiable and multidimensional, and the number of times address generation has increased, so speeding up the sieving speed of the address generator has been advocated. .

The present invention (7 addresses of d-bit map memory +i%
Is it something that is generated repeatedly, depending on the number of rX between bases in memory? It has a numerical arithmetic logic operation circuit (ALLL), and these ALu
It has a micro program memory that stores the function code of L, the take used for @true, and the control take in the same 7 addresses, and uses one address Vouta generation stage in the fulcrum l step 4, and 1 Along with the machine cycle 1, this conquest 2. Based on the results of the rudder control data, it is determined whether the error (g) is sent to the control line, which controls the location counter and the control pulse generation circuit, and controls the location counter and control pulse generation circuit in the micro program memory. In the following steps, the location is fixed and address generation is simulated.

FIG. 1 shows an embodiment of the present invention, which is an address generator for a two-dimensional bit map memory.

1 is a conditional IU circuit that sends out control signals, and 2 is a location counter (■
[C), 3 UI, C controller, 4 is the same number of basic theory immediate calculation circuits (ALLL) as the order of the human map memory
, 5 is a bus line register that temporarily stores the calculation results, and 6 is the function code of the ALU (F
') and the store/take (DJ) and control take (J) used for calculations in the micro program memory in the 76-bit map memory, and the output circuit that sends the pass line data η to the 76-bit map memory. , 8 is a control pulse generation circuit for timing operation of 1-77.

With the above configuration, the microprogram shown in Table 1 is stored in the memory 6, and the rectangle ABCD and its internal 7 addresses are generated on the two-dimensional (x, y) human map memory as shown in Figure 2. ? The 6 microprograms to simplify the operation of this example consist of 5 steps from step 0 to step 4 (hereinafter referred to as frame cycle).
Each corresponds to 0 to 4 of the second meat.

The function code (F) in Table 1 is based on the function code in Table 2, and the
Select the LL4 operation.

Table 2 The '11 Kawamuka I theta (J), which is the anion of micro program 6, is determined by the comparator 1o and y of the
Coordinate comparator 11 ((original comparison) - ta (xJl!/
J) and act as output mask data.

As an initial setting, set the coordinate value of the starting point A (X+y+) in Figure 2, line register 5 (ICG) constant L, location counter (], C) 2 to step 0) L,
LC controller 53u micro flow column 5 steps (1 Freno, 1, 2, 3, 5 steps) Ko,! : Set the VC application counter to send 2 pulses and repeat this frame cycle operation 5 times (Fig. 2 - V).

A, L (L 4 is the function FX.

According to FM (Table-1), “XDIM”! D (Table 2), and from the store data D in Table 1, xD=
1, yD: 1, and performance: n U x 1X
D. x + i, y + yD - y +1.

In other words, F:) ALL4 adds 1 to both x and y from A (X, Yx) in FIG. 2, and the result is stored in bus line register 5 by -11? j is stored, and the data on this bus line is sent out from the output circuit 7 as an address of the hit map memory. In this operation, the data on the bus line is sent to the control signal from the condition judgment circuit 1 to the location counter 2.
and is held (the location is fixed) until it is sent to the control pulse generation circuit 6, and step () is repeated.

The condition judgment circuit 1 is configured as shown in FIG. 3, and the control data (J) of the micro program memory 6 is sent to a comparator 10 that compares the bus line data X and the judgment value x7, and the bus line data y and A comparator 11 that compares the judgment value y.
In step O, setting i'+J constant a: l'IXJr YJ and masking control of each output, x=x
When the condition 5 (x=x2) is satisfied, that is, when the point B (x2y2) in FIG. 2 is reached, the location advances to step l. In step 1, the function ALLJ, 4 is selected as )(+l, yl)(J(and condition y-y1
Execute step 1 with the soil that is filled with the sill ring from step O to step 4! The line is -3VC/l. Te 4
→4'' 4-Article ← Published Ji → Ma-1-3 4f-4 or Up 4 This is a condition that has already been met at t14 when the application progresses to 4, and the process proceeds to the next step O in 1 machine cycle. . Program execution is terminated by initializing the number of frames/cycles (execution of steps O to 4) in the rJC controller 3.
1'lJ1, 1 circuit l, add the end signal generation circuit shown in Fig. 4 to the circuit shown in Fig. 3, and generate bus input data x.
, y and the end point coordinate value of 12, the end point coordinate value of Rensta, XB,
yM are compared by the comparators 137 and 14, respectively, and when they are equal, an end signal is sent to the LC controller 3 and the control pulse generating circuit 8. Rectangle ABC in Figure 2
When address operations are to be performed one after another on several figures that are similar to D, the starting point A ( It is possible to generate address calculations for graphics simply by setting the end point (XIM+) and the end point (XxYx).

Table 4 shows the contents of the micro program memory 6 when generating address operations for triangle ABC as shown in FIG. The processing status of each step is shown below.

Table-4 SI SO'I SOxD YD >X+=x<
x ]], the cormorant point C(x2y
There are two cases in which 1) is reached, but the process x: x in Figure 4
2. y: y, then execute the program.

Dragon-5 This is an example of generating one or more address operations in Cram and processing one figure using a microprogram of only a few steps. This takes advantage of the fact that there is a regularity in the addresses that are generated sequentially in the p4 operation, and when an address without regularity is generated, one address is calculated and generated in the l step and b, i.e. It is necessary to create as many microprograms as there are addresses to be generated. In either case, promptness is guaranteed by generating one address in one machine cycle.

In actual use, if the micro program memory is random access memory (J(,AM)) and the program can be changed and changed using an external controller, a wide variety of types can be created with a small amount of micro program memory. It can correspond to the following shapes.

Simple n of the drawing; (, Figure 1 is the T male side of the present invention, lθF conditional p) 1 circuit, 2-digit location callan') (LC>, 3dLC
Controller, 4 is Mei (jutsu logic pond τ11 circuit (AT) L
1. ), 5 is the bus line register, 6 is the micro
70 crumb memory, 7-output circuit, 8 ri Ili
ml pulse generation circuit. Figures 2 and 5 ]v,
1-2 is an example of the occurrence of a hit/f/memory/j' address based on the ζ example. , Fig. 3 (r2・, thread f
4 size W) 1 circuit 1 has &&I parent, 10
, l 1 iL comparison, micro program
Memory 6 and Has Rhino antiυηiii h line (
Figure 1) 4th lq, +v, t 7th period ends execution. Go 7111 departs from 1ro 1ro °'t12 i-j terminal station (xl, l, y
, ), l 3 , l 4 &, i this XP, +3'p
+ and lotus line song Li: (iK
It is an f6 comparator.

Figure 1 Figure 2 Figure 3 F-1 system P data CJ)-1- Figure 4

Claims (2)

[Claims] (1) In the bit map memory address generation method, a microprogram that stores the arithmetic logic circuit (ALLL) fan, action code, data not used during operation, and control data in the same address is used. Then, using this blockrum in one step, one machine contest cycle t address one data generation operation is performed for the first time, and from the result of this operation and the control data of the program, a function case 1 number is generated, and the μ cage, 1. A method for generating an address for a bit map memory, characterized in that the address generation operation is performed by controlling the count and control pulse generation, and fixing a location at an arbitrary step of a previous Ht micro program. (2) an arithmetic logic circuit (ALu), a microprogram memory that stores the function code of the ALLL, the AI, the data used at 1 o'clock, and the control p+ data in the same address; Based on the calculation result generated during the progress of the micro program and the above-mentioned control data, the condition 1゛
11 The yarn sent to Tsukuda 1 line 1-1” disconnection and Of
lFii (function to change the number of digits by control I'11 data and function to execute or hold count by the conditional Iζ11 information), and the front is a location counter that addresses the self-microphone program memory. , a control pulse generation circuit that is controlled by the agency JMe condition 'l'-IIIJ1 signal and controls the timing @1'l=k of each part, and an output circuit that outputs the address determined by the previous Bt AL (1). k J:j (lit) Hit map memory Q, address generator