JPS5943864B2 - data receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data receiving device, and more particularly to a data receiving device for a start-stop synchronization signal that can receive data divided into data blocks and transmitted without causing start-stop synchronization deviation. be.

Conventionally, when this type of data receiving device receives an asynchronous signal, when the power of the receiving device is turned on, the polarity corresponding to the start bit is set regardless of the data bit or start bit of the asynchronous signal. When we detect the bit of
Since reception starts immediately, there is a drawback that a start-stop synchronization error occurs. Further, in the receiving device, it is necessary to turn on the power before the transmitting device sends data, which has the disadvantage of wasting power. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks by detecting consecutive stop polarities between data blocks provided in a transmitting device to enable a receiving device to receive data. It is an object of the present invention to provide an economical and highly reliable data receiving device that can be powered on at any time.

According to the present invention, in a device that receives an asynchronous signal having stop polarity at times other than data transfer, a counting circuit counts the time of stop polarity and detects when the stop polarity reaches a preset value; There is obtained a data receiving device characterized in that it has a holding circuit that holds the detection signal from the counting circuit, and is permitted to receive data based on the output signal from the holding circuit.

Next, embodiments of the present invention will be described with reference to the drawings.

The data of the start-stop synchronization signal received by the receiving device of the present invention is
As shown in Figure 1, each character of the data block,
In other words, the code STX indicating the beginning of the block) each data
The characters T1, T2, . . . Tn and the characters indicated by the block code ETX are consecutive.

In addition, as shown in FIG. 2, the stop polarity can be set at any position between the data block heads, that is, between data block A and data block B, and between data block C and data block D. It has some dummy time. As shown in FIG. 3, this dummy time continues longer than the sum of time T of the stop bit SP and all data bits B1, b2, b3 . . . , B8 constituting one character. FIG. 4 shows a data receiving device according to an embodiment of the present invention, in which 1 is a demodulation circuit that demodulates the modulated signal a and converts it into a DC signal, and 2 is a demodulation circuit that converts the DC signal from the demodulation circuit 1 into a logic level signal. This is a DC conversion circuit that converts into

G1 is a not gate circuit that inverts the output signal of the DC conversion circuit 2, G2 is an AND gate circuit whose input conditions are the output signal of the NOT gate circuit G1 and the clock pulse signal b which is a timing signal, and G3 is a not gate circuit that inverts the output signal of the DC conversion circuit 2. This is an AND gate circuit whose input conditions are an output signal and a clock pulse signal b, which is a timing signal. G4
is the output signal of the AND gate circuit G3 and the power-on signal.
OR gate circuit with reset signal C as input condition, C1
is a counting circuit whose input condition is the counting power d from the AND gate circuit G2 or the counting prohibition input e from the OR gate circuit G4. F, is a flip-flop circuit which inputs the counting output signal f from the counting circuit C1 and the power-on reset signal C, and G is the output signal of the DC converter circuit 2 and the output signal of the flip-flop circuit F1. This is an AND gate circuit whose input condition is . 3 is a serial/parallel conversion circuit that converts the serial signal from the AND gate circuit G5 into a parallel signal, and 4 is a reception control circuit that controls the parallel signal from the serial/parallel conversion circuit 3.

According to the data receiving device having the above configuration, when the modulated signal a modulated from the line is manually input to the demodulation circuit 1, the demodulation circuit 1 detects, for example, - Outputs a DC signal of 8±2(7),
Further, when the modulation signal a has a frequency corresponding to the start polarity, the demodulation circuit 1 outputs a DC signal of +8+2 (V).

These DC signals enter the DC conversion circuit 2, and this DC conversion circuit 2 has a logic level of 1 when the input is +8±2 (V).
When the input is -8±2 (V), the logic level is "O".
The output signal of the DC conversion circuit 2 is input to the NOT gate circuit G1, the AND gate circuit G3, and the AND gate circuit G5. The value becomes ``0'', and when it passes through the not gate circuit G1, it becomes the logical value ``1''.The output of the not gate circuit G is outputted from the AND gate circuit G.
2, and is sampled by clock pulse signal b, which fully anticipates the reception margin. Therefore, while the modulation signal a has the stop polarity, the AND gate circuit G2 outputs the clock pulse b. The output signal of the AND gate circuit G2 is connected to the counting input d of the counting circuit C1, and the counting circuit C1 counts the output pulses of the AND gate circuit G2. The AND gate circuit G3 outputs a clock pulse signal b when the output signal of the DC conversion circuit 2 has a logical value of "1", that is, when the modulation signal a has a start polarity.
4, and the output of the OR gate circuit G4 is input to the counting inhibit input e of the counting circuit C1. The counting circuit C is set to a threshold when the count prohibition input e has a logical value of 81'', that is, when the modulation signal a has the start polarity.Counting circuit C1
The output f of is set to a logical value of 1 to the count prohibition input e when a predetermined number of pulses of the counting force d continues, that is, after the start of counting.
When ゜゛ is not applied, the logic value becomes 1. Therefore, if the counting circuit C1 is set to count the number of clock pulse signals b corresponding to the continuous time t of stop polarity, when the output f of the counting circuit C1 reaches the logical value "1", This corresponds to the fact that the modulation signal a has been in the stop polarity continuously for a predetermined period of time or more. The output f of the counting circuit C1 is
It is connected to the set input of flip-flop F1, and when this output f has a logic value of 6F', the output of flip-flop F1 becomes a logic value of 81'' and maintains that state.

When the output of flip-flop F1 becomes the logical value "F",
The output of the DC converter circuit 2 is given to the serial-parallel converter circuit 3 through the AND gate circuit G5, and the serial-parallel converter circuit 3 converts the output of the DC converter circuit 2, given through the AND gate circuit G5, into a parallel signal in character units. , to the reception control circuit 4. This reception control circuit 4 distinguishes the character signal applied from the serial/parallel conversion circuit 3 into a control code and data and performs data block processing. Here, the signal C is a power-on reset signal, and has a logic value of "1" for a certain period of time after the power is turned on.This signal causes the counting circuit C1 and the flip-flop circuit F1 to
It remains in the set state for a certain period of time after the power is turned on. After being set by the counting circuit C1, the flip-flop circuit F1 is powered on regardless of the output f of the counting circuit C1.
It is not reset until the reset signal C reaches the logical value "1". Therefore, according to the receiving apparatus of the embodiment of the present invention, the stop signals constituting one character as shown in FIGS.・Bit SP and all data ・Bit Bl,b
2, b3 . - Start receiving from bit ST. Therefore, even if the power is turned on arbitrarily on the receiving side, a start-stop synchronization error will not occur. As explained above, the present invention provides a stop block in which each character constituting a data block is continuous and at least one character is located at an arbitrary position between a data block and a data block.
A dummy time detection unit is configured to receive an astop synchronization signal having a continuous stop polarity exceeding the time of the sum of the bit and all data bits, detect the continuous time of the stop polarity, and start data reception. Because I am doing
Start-stop synchronization deviation can be prevented even if the power is turned on at any time.

Further, due to the reception start-stop synchronization signal requirement, reception can be started from the beginning of the data block, and characters in which all data bits have the same stop polarity can be used as codes, resulting in high performance and economy.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an example of a data block of an asynchronous signal received by the data receiving device of the present invention, and FIG. 2 is a block diagram showing an example of the data block and dummy time received by the data receiving device of the present invention. FIG. 3 is a time chart showing an example of the last character and dummy time of the data block received by the data receiving device of the present invention, and FIG. 4 is a diagram showing an embodiment of the data receiving device of the present invention. It is a block wiring diagram. 1...Demodulation circuit, 2...DC conversion circuit, 3...Series-parallel conversion circuit, 4...Reception control circuit, C1...・Counting circuit, G, not gate circuit, G2, G3, G5...AND gate circuit, G4...OR gate circuit, F1...
...Flip-flop circuit.

Claims (1)

[Claims] 1. In a receiving device that receives an asynchronous signal having stop polarity for a predetermined time between data blocks including a plurality of data characters, the gate circuit outputs a detection signal while the signal has stop polarity; It has a counting circuit that measures a signal application time and detects when the predetermined time has elapsed, and a holding circuit that holds the detection signal from the counting circuit, and stores data by the output signal from the holding circuit. A data receiving device characterized by starting a receiving operation.