JPS5943529A - 樹脂封止型電子部品の製造方法 - Google Patents

樹脂封止型電子部品の製造方法

Info

Publication number
JPS5943529A
JPS5943529A JP15410982A JP15410982A JPS5943529A JP S5943529 A JPS5943529 A JP S5943529A JP 15410982 A JP15410982 A JP 15410982A JP 15410982 A JP15410982 A JP 15410982A JP S5943529 A JPS5943529 A JP S5943529A
Authority
JP
Japan
Prior art keywords
resin
lead frame
lower surfaces
tablets
type electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15410982A
Other languages
English (en)
Inventor
Hirokuni Mamiya
間宮 洋邦
Teruyoshi Shibata
柴田 輝義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP15410982A priority Critical patent/JPS5943529A/ja
Publication of JPS5943529A publication Critical patent/JPS5943529A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明M t↑で、子r部器、電電機器等に用いられる
樹脂肘+lz型電子部品の製造方法に関するもので、そ
の目的とする七ころt・」少量多品種生産、連続生産を
可6F)ならしめ且つ不良発生率を低−「すしめること
にある。
fK来の同脂封1):型電子部品の製造方法は第1図に
示すよう(でり−1゛フト′−ム1に素子2全ダイポン
デイングし、てからインナーポンディング3し次にパッ
シベーション4してからトランスファー成形して素P全
樹脂5で封1にして樹脂封[上型電子部品全仁)るもの
て゛、大量少品抑牛ρr、ハツチ牛θjパに好i1:’
liであるが少1負多品tr+r生9t・、連δ・、Y
生産Gて不向さで叶つ不良発71−.; 、’i(!も
6〜7%と、1イ、いものでちった。
本発明は上記欠点を解決−1−イ)も・′)で、11−
ドフレームの一1二1:1酊に1i覧形月第1タフ゛1
・、1・を夫々1□1己むンし成IFJ一体後、該Iル
:形品に二ノ;千を・q″イインリーボンテ′イング千
プハら塁子金ボ、ディングで1寸1F−するプこめ少6
(名品4′i17生産、連Bj牛近をijl 6F+な
らしめ且つ不良発生率を1〜2%((低トをぜることが
できたものである。
以F本発明の一実施例を・、i< 21’、l 4) 
lン、1面により熟1明する。1は金属製リード7レー
ノ・で、リードフレーム1の上ト面(lイ“−)1ノー
ルJ、177脂、エボNシ樹脂、不pp、 Jlilポ
リエステル樹脂、リアリルフタレーを嗣脂、シリコン樹
脂、メラミン!、%! IIFi、ポリアミド、ポリイ
ミド、ポリフヌジエン、ポリスフレフメン、ポリウレタ
ン等の」1独又に71i合物又C」乃・[スト物からな
る成形拐料タプレ、、) トロ 、 6’を夫々配設し
7圧縮i成形等で成形一体後、核酸1[・品7[半丁2
をグイインナーポンディング8してかG、素了2ヲ7丁
ノール槓111!t、工+J−゛ギシt、ソ)脂、イ\
II、←1じ↑ζリエスラール11”111[旨、シプ
リルフタレート4+;、l 1lii、シリコンT「j
 lij 。
ポリアミド、ポリ、(ミド、ボリブグジ]ン、ポリスル
ーフnン、ポリウレクンt′厚の、F4j口中又し、i
汀414合′抄クタートり−1変4’l物からなるt1
’ 7[> nNでボ、アイング9で1\t +lして
(5′H脂封11〕c!! ?jj子部品を・tζ)る
もソフ)である。成形(]料ダブレ、1シiリードフレ
ームの十Fi4“11に夫々配設゛ずろことが必ガ[で
、好ましく 1′:f 、l・「−而(τ夫々1 n5
il配置投′するととが5′Jまし2い。なお素子、ダ
イインーノ″−ホンディンク、ソー1゛フレー 1− 
表面’ Vr +#; ’Itt44料や11・形相と
の拌′着・叶を白子させるためσ)61J処fJ1+ 
、ゴーティンゲタjl ill等のン占・j生化処用1
を加1−ておくこともできるものである。
息子説、明シy’r−ヨウlK本発明(7) f<l+
I脂tst l夕1すfl、c :r一部品の1lll
l造ノj法(でよれば少幇多品神/:1τ産、連続生産
苓T実上]ルすることができ一目つり一ドフレームの鴬
(形が全く々いブこめ不良発生率を従来方法より5%低
Fさゼることかできだものである。
【図面の簡単な説明】
第1図を」従来の樹脂材Iヒ型電子1(1つ品の製41
方法”tf(了j)111品ノミ1す+11j :、f
j法ノlf’+E略エイ’+゛l l−C:F> ;ニ
ー 、、1(」リードフ1/−ム、2((:′、イ、8
j1インナーボン1イング、46.(バ、シベーシオン
、5HJl+’七1′、♀。 6 、6’ )、!成4E4;を料ダブl/、I’、7
fノ1++い13品、8(′Jグイインナーー)iンデ
ィング、()t1ボ、ディングであ2)、 特ボ1出ハ自人 挨17屯−■丁(l)、会社社 代用1人方即士  竹 尼 1改 九 (i’(か2名) ;i’; 11.″ /7 ・i’t2i、1

Claims (1)

    【特許請求の範囲】
  1. fi+  リードフレームのヒ「而に成彬セ月タブレ、
    ト金夫々配設し成形一体後、核成形品に素子をグイイン
    ナーポンディングしてから素子をポツティングで月11
    −するととを特徴とする樹脂封1に型電子部品の囮、イ
    5方法。
JP15410982A 1982-09-03 1982-09-03 樹脂封止型電子部品の製造方法 Pending JPS5943529A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15410982A JPS5943529A (ja) 1982-09-03 1982-09-03 樹脂封止型電子部品の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15410982A JPS5943529A (ja) 1982-09-03 1982-09-03 樹脂封止型電子部品の製造方法

Publications (1)

Publication Number Publication Date
JPS5943529A true JPS5943529A (ja) 1984-03-10

Family

ID=15577117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15410982A Pending JPS5943529A (ja) 1982-09-03 1982-09-03 樹脂封止型電子部品の製造方法

Country Status (1)

Country Link
JP (1) JPS5943529A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06283655A (ja) * 1993-03-26 1994-10-07 Kyocera Corp 半導体素子収納用パッケージ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06283655A (ja) * 1993-03-26 1994-10-07 Kyocera Corp 半導体素子収納用パッケージ

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