JPS5942506B2 - Multiplexed circular bus system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circular bus that connects one computer and another computer or one computer and peripheral devices with a circular bus consisting of stations and transmission lines to perform communication. The present invention relates to bus systems, and in particular to improvements in means for multiple use of buses.

Recently, with the expansion of computer utilization technology, there have been many cases in which work cannot be accomplished with a single computer system alone.

For example, an office computer and a production line control computer may be combined to manage the production line from a management level. One of the methods for connecting computers and peripheral devices in this way is the so-called circular bus method. FIG. 1 shows a typical configuration example of the circular bus system. 51, S2, S in the diagram
n (generally referred to as S) is called a station, and has a function of receiving a signal flowing in one direction shown by an arrow on bus B, and relaying and amplifying the signal. P,, P2, P33, p32, p33,
. . , pn-1, pn (generally referred to as P) are computers or peripheral devices, and one or more of them are connected to one station. Generally, Pi has a considerable processing ability and performs processing independently, but communicates via this circular bus B when reporting the processing results to other Pi.

Now, the case where Pi transmits to Pj will be explained.

1Pi sends data including Sj as the partner name to Si.

2Si checks that bus B is free and sends a message addressed to Sj onto bus B.

3Sj constantly monitors messages at the input end (receiving end), and when a message addressed to it comes, it receives it and sends it to PJ.

3. Perform arbitrary Si-Sj communication by repeating the above operation.

In this way, since there is one bus B for 11n stations S in the data highway system, communication can be carried out freely and efficiently even when the amount of communication is relatively small.

However, when the amount of communication increases, bus B imposes a limit on the amount of communication. In this respect, it is inferior to the star-like coupling system shown in FIG. However, in the star-coupled system shown in Fig. 2, it is necessary to prepare a communication path (cable) in advance in order to communicate between any Pl and Pj, and the use of the communication path is poor. Cost becomes an issue. The present invention was made with these circumstances in mind, and its purpose is to provide a multiplex bus system that does not increase cable installation costs and can dramatically increase communication volume. be.

Another object of the present invention is to provide a multiplexed ring bus system for clearing faulty buckets and bypassing faulty stations.

The details of the present invention will be explained below based on embodiments shown in the drawings.

FIG. 3 is a diagram showing a schematic configuration of the ring bus system of the present invention, where S,, s2,...Sn are stations, Pl, p2
, . . . Pn indicates a computer, and SYN indicates a synchronizer. Here, for simplicity, we will discuss the case where one computer is connected to one station, but of course it is also possible when multiple computers are connected to one station.The signal on bus B is It is divided by fixed-length channels, allowing multiple communications at the same time.

FIG. 4 shows the format of signals flowing on bus B. In Fig. 4a, one frame consists of four channels, but the optimum number of channels (the number is determined by the number of stations). Fig. 4b shows the data structure of the channels. In Fig. 4b, SP (indicates the beginning of the Gochanel, SF can indicate the beginning of the frame depending on its contents, and DA (the destination station address, SA is the source station address, C is the command, CRC2 is the error detection of the transmitted signal) A block of data is called a bucket.C in Fig. 4b, that is, a command, is shown in more detail in Fig. 4c. Indicates the first packet when divided, F
(This shows the final bucket command. COM is a bus command, and there are various types.

FIG. 5 is a diagram showing the structure of the station in the above embodiment.

1 is a receiver, 2 (or a transmitter), and switches 3, .
It is connected to bus B via 32.

After the signal from bus B is amplified and shaped by receiver 1,
It is sent to the reception shift register 4. The control circuit 5 sends the contents of the shift register 4 to the receiving buffer 6 when the contents are intended for this station. If the contents of shift register 4 are not intended for this station, they are sent to transmitter 2 by signal A, and after power amplification, they are sent to bus B.
send to. On the other hand, when the computer wants to send a signal (well, when the data to be sent is sent to the sending shift register 8 via the sending buffer 7, this data is sent to the bus B via the transmitter 2 by the signal A. Transmission buffer 7
, the receiving buffer 6 adjusts the input/output speed of the computer and the transfer speed of the bus B. In addition, when the station (well, it has a bypass path 9), and the station's power supply is OFF or a failure in the transmitter/receiver etc. is detected (the switches 31 and 32 are switched and the bypass path 9 is activated). It is configured.

In addition, the bypass route can be used when the operator discovers a malfunction in the station (by the operator's operation, or when the computer discovers a malfunction in the station (or by a command from the computer). Although not shown in the figure, the station is equipped with a circuit that automatically returns a bucket containing a NACK bus command when a transmission request is received from another station when the station is in the receiving or transmitting state. The synchronizer performs l) synchronization, 2) traffic monitoring, and 3)
It has error detection and correction functions.

First, the synchronization function will be explained. In FIG. 3, it is sufficient to carry a signal of l frame length on the circular bus B, and the signal exists at the bus B1 station S and the synchronizer SYN. The amount of signals on bus B fluctuates due to signal delays due to environmental changes such as temperature.
Further, the signal within station S decreases by one station when station Si is bypassed due to a failure. For this reason, as shown in FIG. 6, the synchronizer has a variable length buffer, and compensates for the fluctuation in the signal amount so that the sum of the signal inside the buffer and the external signal always becomes one frame. The signal amount is being adjusted.
Traffic monitoring, on the other hand, is auxiliary and is intended to monitor the signals on bus B and obtain information regarding the usage status of the channel.

This advisory will be used as a guideline for improving the design of multiplexed ring bus systems. Next, data transmission and reception operations in the multiplexed circular bus system will be explained. In FIG. 3, it is assumed that computer P transmits data to computer P2 via stations Sl and S2. First, the computer P1 internally prepares the transmission data shown in FIG. 7a. When computer P1 outputs a transmission command to station S, station S1 accepts it unless it is in a receiving state. Next, station S1 searches for an empty channel, and when an empty channel is found, it divides the data in computer P into a plurality of packets as shown in FIG. 7b, and sends them out one after another using the same channel. As already mentioned, the L flag is set for the first packet, and the F flag is set for the last packet. When the transmission is completed, the used channel is returned to the free channel. Note that the free channel is set according to the contents of DA. If it is DA-0, it is an empty channel, and if it is DA\O, it is a channel in use.Meanwhile, station S2 constantly monitors the signal on bus B, and if it finds a packet addressed to itself, it will It receives packets from the same channel and synthesizes the data as shown in Fig. 7c in computer P2.
FIG. 3 is a diagram showing a more detailed configuration of the synchronizer shown in the figure. The signal received by the receiver 10 is amplified and shaped, sent to the reception shift register 11, and converted into parallel data. When the synchronization detection circuit 12 detects the beginning of a frame from the contents of the shift register 11, it returns the reception address counter 13 to its initial value. Parallel data from receive shift register 11 is written via write buffer 14 to buffer memory 15 designated by address counter 13. FIG. 8 shows a case where one frame is composed of four channels. On the other hand, when the SP-SF generator 16 outputs the beginning of the frame, the transmission address counter 1
7 is returned to its initial value, and the contents of the buffer memory 15 indicated by this are read out and sent to the transmission shift register 18. The transmission shift register 18 converts the read data into a serial signal and supplies it to the transmitter 19. The variable length buffer surrounded by a broken line 20 in FIG. 8 is adjusted by the above operation so that a signal of one frame length is placed on the bus. In FIG. 8, the received signal (variable length buffer 20
At the same time, the signal is sent to the error detection circuit 21 and the traffic monitoring circuit 22.

In the error detection circuit 21, the SA check circuit 23 first checks whether the contents of the SA are equal to any address of a station participating in the bus at that time. If the SA check circuit 23 determines that the SA of the received signal is not equal to the address of any station, the number of the received channel is known from the contents of the reception channel counter (CHC) 24, and the control circuit 25
Accordingly, the corresponding channel stored in the buffer memory 15 is set as an empty channel. FIG. 9 shows the SA check circuit.

For ease of explanation, stations Sl, S2, S3
Suppose that is connected to the bus. The station addresses participating in the bus are checked using the method described below.
Participating station flags 31, 32, and 33 are set to field Gh when the corresponding station is participating in the bus. When the content of the SA of the received signal is set in the SA buffer 34, it is decoded by the decoder 35, and the AND gate group 36 checks whether the station address is participating in the bus. The addresses of the stations participating in the bus are examined by the participating station monitoring circuit 26 in FIG.

The participating station monitoring circuit 26 periodically sends the packet shown in FIG. 10a to each station. If each station is not in the transmitting/receiving state (hereinafter this state will be referred to as an idle state), it returns the packet shown in FIG. 10b, and if it is in the transmitting/receiving state, it returns the packet shown in FIG. 10c.

The monitoring circuit 26 sets a flag for the corresponding station address when the packet shown in FIG. 10b or c is returned, and if no packet is returned,
Defeat the appropriate flag. To make this possible, each station has a function of automatically returning the packet shown in FIG. 10b when it receives the packet shown in FIG. 10a in an idle state. In this way, abnormal packets whose SA content is other than the participating station address are erased, but abnormal packets whose SA contents are equal to any of the participating station addresses continue to monopolize the channel on the bus.

In order to solve this problem, the present invention monitors the SA when it is idle, and displays its contents on your station.
When the packet is equal to the address (or the station has a function to rewrite the contents of SA to zero), packets with SA of zero are erased by the synchronizer function described above. If the circuit for erasing packets operates normally, all abnormal packets will be erased, but considering the possibility that the circuit may fail, the CRC27 in Fig. 8 detects and detects abnormal packets using the CRC method. Erasure is also performed at the same time.

For example, if a station that was participating in the bus is switched to a bypass route due to a failure or other reason and does not participate, or if a station that was not participating joins, the bus is switched by a switch, and the noise generated at this time is There are songs that may cause the channel to be in use.

It is also conceivable that when a nearby power switch is turned on or off, noise is spread and the channel becomes in use. According to the present invention, abnormal packets generated in this manner can be erased, thereby eliminating the impact on the communication capability of the bus. Referring again to FIG. 8, the bus abnormality detection and recovery circuit 28 determines that the bus is abnormal if 1) SP does not arrive, and 2) abnormality is detected in n consecutive packets by the CRC method.

This state may be caused by a transmission line being disconnected or a station failure. In the former case, it is difficult to automatically restore the bus function, but in the latter case, the bus function can be restored by bypassing the failed station. In order to make this possible, the station bypass path was improved as shown in Figure 11, and the switch SW
The station is equipped with a circuit that processes commands to switch the

Synchronizer (When an abnormality is detected on the bus, a synchronizer bypasses a certain station by command, checks whether the bus is functioning normally, and if the result of the check is still abnormal, returns the station to the bus.) You can change stations and repeat this operation until bus function is restored.

[Brief explanation of drawings]

1 and 2 (showing the conventional bus system, FIG. 3 (showing the multiplexed ring bus system according to the present invention), and FIGS. 4A, b, and c show the multiplexed subsystem according to the present invention. Figure 5 shows the configuration of the station; Figure 6 shows the schematic configuration of the synchronizer; Figure 7 A, b,
FIG. 8 is a diagram showing the detailed configuration of the synchronizer, FIG. 9 is a diagram showing the configuration of the SA check circuit, and FIG.
Figures A, b, and c are diagrams showing the packet structure when checking stations participating in the bus, and Figure 11 is a diagram showing an improved station.

Claims (1)

[Claims] 1. In a circular bus system in which communication is performed between one computer and another computer or between one computer and peripheral devices by connecting them with a circular bus consisting of stations, synchronizers, and transmission lines, The synchronizer includes means for storing stations participating in the bus by periodically communicating with the stations, and a means for receiving signals on the transmission path and transmitting the signals from the stations participating in the bus. A multiplexed ring bus system comprising: means for detecting that the signal is not a signal; and means for erasing the signal on the transmission line based on the detection output of the detecting means. 2. The multiplexed circular bus system according to claim 1, wherein the synchronizer checks the signals on the transmission line using a CRC method and eliminates abnormal signals. 3. The synchronizer is characterized by comprising means for detecting an abnormality in the bus, and means for detecting the function of the bus by causing any one of the stations to not participate in the bus when the abnormality is detected by the means. A multiplexed circular bus system according to claim 1.