JPS5942336B2 - digital signal stabilizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal stabilization device, which removes instability of the digital signal by performing logical bit processing on the input digital signal, and can be used in any digital signal processing system. An object of the present invention is to provide a digital signal stabilizing device that can output a stable digital signal.

FIG. 1 shows a block diagram of an example of a conventional digital signal stabilization device.

In the figure, an analog signal input to an input terminal 1 is supplied to an AD converter 2, where it undergoes analog-to-digital conversion and is output as an n-bit digital signal. This n
The digital signal of bits is used for the processing system or control system 4 which is controlled by being supplied with the digital signal of m (m<n) bits. The bits are simply truncated and the upper m bits of the digital signal are stored in the latch 3 in synchronization with the clock pulse indicated by CK,
Furthermore, it is applied to the processing system or control system 4. Here, the n-bit digital data that is the output of the AD converter 2 is
When the value is monotonically changing or stopping while having instability equivalent to B (vibration, etc.), the point at which the value is located as shown in Figure 2 is considered to be uniformly distributed in terms of probability. .

Now, as an example, if nm is 3, the values of n-bit digital data are all "o", and the output data D is monotonically increased from this value. As can be seen from Figure 2, the value of the least significant bit (the 4th bit from the LSB of n-bit digital data) first becomes ``1''. (also the LSB of n-bit digital data) is from ゛゛o'' to electric power 1, , , and. Denden 1,93
) radenden. ,,Aa:):! 5[! :7[,V
This is the point when the number has changed C8 (::23) times. That is,
The second 3-bit LSBI shift of Dr changed 8 times.
Output data D only when the value "1" shown second from the top of the figure changes to the value "o" shown first.

The least significant bit of changes from ゛゛o'' to ``1'', and at the point of seven changes outside of that, it becomes D. The least significant bit of is unchanged. Therefore, m-bit output data D. is 1/8(-
The value becomes unstable with a probability of 1/23). This is the same in other cases, and as a result, the value of data consisting of the upper m bits becomes unstable with a probability of 1/2 (n-m). In order to reduce this instability, a latch 3 is provided to latch m bits on the output side of the AD converter 2 as shown in FIG. In some cases, the setting is made several hundred times larger, but this does not solve the essential problem that the AD conversion accuracy deteriorates and the output data of the latch 3 becomes unstable due to probability. -o In the past, control systems or digital signal processing systems were used to handle digital signals that could become stochastically unstable, which significantly reduced the reliability of the control system θ, or caused the operation of the digital signal processing system to become unstable. It had the disadvantage that it could be made into something.

The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described with reference to FIG. 3 and subsequent figures. FIG. 3 shows a circuit diagram of an embodiment of the digital signal stabilizing device according to the present invention. In the figure, the same parts as in Figure 1 are given the same numbers.
The explanation will be omitted. Of the n-bit digital signal (shown in FIG. 4A) of the AD converter 2, the upper m bits are supplied to the latch 3, while the remaining nm bits (
Two bits ((LSB+1) bit and (LSB+2) bit) excluding the LSB (3 bits as an example) are applied to latch 5, where they are latched by clock CK2. Of the outputs of latch 5 (LSB+1)
After the polarity of the positive bit of the bit is reversed by the inverter 6, the positive polarity of the (LSB+2)th bit from the latch 5 and the positive polarity of the A
After being ANDed by the ND circuit 7, it is applied to the 2-input AND circuit 8, where it is ANDed with the delayed clock obtained by delaying the clock CK2 from the delay circuit 9 by a fixed time τ, and the clock is applied to the latch 3. is applied to latch 3 as a latch command signal. Here, the output waveform of the AD converter 2 shown in FIG. 3 is shown in FIG. 4A, and the clock CK2 is shown in FIG. 4B.

Further, the output signal waveforms of the AND circuit 7, the delay circuit 9, and the AND circuit 8 become as shown by C, d, and e in FIG. This causes latch 3 to set the (LSB+1)th bit to logic
゛, only when the (LSB+2)th bit is logical 3 bits,
The storage digital signal is output, and in other cases, a holding operation is performed. In other words, when transmitting a digital signal by discarding the lower three bits, (LSB+4
) is the least significant bit of the valid output bits, but
This is from 0n to 11F' or (from 1F2 to τmi 0F
', the switching occurs at the human-powered data switching threshold level shown at I or in Figure 5, and in the direction shown by the arrow within the range shown in Figure 5, which is between these threshold levels I, The level at which the signal changes to is the level held and output to the latch 3 of this embodiment, and is the output side data switching threshold level.

Therefore, it can be seen that according to this embodiment, by setting the output side data switching threshold level as described above, a digital signal can be obtained with the instability of the lower bits removed. That is, when the input analog signal (original analog signal) at input terminal 1 monotonically increases or decreases, and when it stops at a certain value on average but is accompanied by instability (e.g. vibration) equivalent to the LSB level. In any case, the digital signal output to the processing system or control system 4 changes smoothly or is held at a constant value according to this embodiment. As described above, the digital signal stabilizing device according to the present invention is capable of controlling the output m for the first data switching threshold level of the upper m bits (m<n) of the n-bit input digital signal. The lower side of the input digital signal (
a detection section that detects a second data switching threshold level using some of the n-m) bits; is supplied as a holding control signal, and when the detection section detects the second data switching threshold level, it outputs the upper m bits of data, and when the detection section detects the second data switching threshold level, it outputs the data of the upper m bits. Since it consists of a holding section that holds the upper m bits of data at the time of detection, the instability of the input digital signal can be removed, and a digital control system that uses analog and digital can be controlled stably. The digital signal processing system supplied with m-bit digital signals can operate stably, and the required circuit configuration is simple, so it can be constructed with almost no increase in cost.

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing an example of a conventional digital signal stabilizing device, Fig. 2 is a diagram for explaining instability of digital signals, and Fig. 3 is a circuit system showing an example of the device of the present invention. 4A to 4E are signal waveform diagrams for explaining the operation of FIG. 3, respectively, and FIG. 5 explains the input side data switching threshold level and the output side data switching threshold level in FIG. 3. This is a diagram for 1...Analog signal input terminal, 2...
AD converter, 3, 5...Latch, 6...
・Inverter, 7, 8...AND circuit, 9...
...Delay circuit.

Claims (1)

[Claims] 1 Output m-bit second data switching threshold level is shifted from the first data switching threshold level of the upper m bits (m<n) of the n-bit input digital signal. a detection unit for detecting the second data switching threshold level using some of the lower (nm) bits of the input digital signal to set the data switching threshold level to an intermediate portion; The data of the upper m bits of the signal are supplied, and the output signal of the detection section is supplied as a holding control signal, and when the detection section detects the second data switching threshold level, the upper m bits of the data are supplied. 1. A digital signal stabilizing device comprising: a holding section that outputs data of the first m bits and holds the upper m bits of data when the second data switching threshold level of the detecting section is not detected.