JPS5941231B2 - pattern recognition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention traces the outline of an input pattern, defines a direction between each bit, converts the input pattern into a direction code string, and uses the converted direction code string to It relates to a pattern recognition device and aims to improve recognition speed by compressing direction code strings.

First, the direction code string etc. will be explained using FIGS. 1 and 2.

In FIG. 2, 21 is a terminal to which the output signal from the binarization circuit is applied, 22 is a pattern memory that stores the signal applied to the terminal 21, and 23 is a coding device that traces the contour of the input pattern and generates a predetermined code. A conversion unit 24 is a direction code memory that stores this code; 25 is a determination unit that compares the storage contents of the direction code memory 24 with the output of the memory 26 that stores the standard pattern; and 2T is the determination unit 26; This is the output terminal of The signal applied to the input terminal 21 is recorded in the memory 22 as a pattern as shown in FIG. 1A, for example. The encoding converter 23 generates eight direction codes as shown in FIG. 1C, and the starting point is at the lower right corner of the input pattern. Therefore, the first
In the case of the pattern shown in Figure A, as shown in Figure 1,
Starting from position a, encoded signals are sequentially output. FIG. 12 shows the signal.

This signal is temporarily stored in the memory 24, and compared with the standard pattern output from the memory 26, and the determination unit 25 determines what the input pattern is. Here, there are various methods for the determination in the determination unit 25, such as dynamic programming, contour structure analysis, etc., but the determination method is related to converting the input pattern into the code string as described above. It's exactly the same.

However, when attempting to recognize an input pattern by converting it into a code string as described above, there is a drawback that the recognition speed becomes slower as the number of converted codes increases.

Furthermore, as the input pattern becomes larger, the number of codes increases and the recognition speed becomes slower. Therefore, when the input pattern is large or there are too many codes, the code string is compressed to increase recognition speed. Further, an increase in the capacity of the memory 24 is prevented by its compression. A conventional compression method will be explained with reference to FIG.

What is shown in FIG. 3A is the original code information, and when compressing it to %, every other code is sampled.
%, two of the three are sampled. For example, in the figure, the white circle code is sampled when the compression rate is %, and the result at this time is shown below. The code compressed in this way is considerably deformed compared to the original pattern. Particularly in this example, a problem arises in that the component in direction 2 disappears. Also, × mark is %
The results were sampled in the case of , and the results are shown in Figure C. Even if the compression ratio is set to % in this way, the original pattern will be considerably deformed. The present invention provides a pattern recognition device that compresses direction code strings while minimizing deformation to the original pattern.

This will be explained below along with examples.

Here, the direction code shown in FIG. 6 is used.
In other words, conventionally, "O" to "7" were used to express eight directions.
However, in this example, a value of "8" or more is given, and it is +1 (plan 1) for every % rotation clockwise, and vice versa. The direction code is such that it increments by -1 (minus 1) every time it rotates. FIG. 6 is expressed in hexadecimal. When applied to the direction code of the pattern shown in FIG. 4A, the code becomes "9-A-9-A...C-D" as shown as 51 in FIG. 5A. Furthermore, this figure 5A explains the case of compressing a direction code string to %.Adjacent direction codes and the remainder from the previous operation are added, the result is halved, and this value is new. At the same time, the remainder generated at this time is added to the next addition. In this way a new direction code, shown as 52, can be created. In addition, in the case of calculation of direction code 74, since it is the first code, 1
There is no remainder from the previous operation, and the value of direction code 70 is “9”.
” and the value “A” (expressed in hexadecimal) of the direction code 71, and convert to %. The result is "9", with a remainder of "1" (75 indicates the remainder). Next, in the case of calculation of direction code J Mo V, the value of direction code 72 is "9" and direction code 7
Add the value "A" of 3 and the value "1" of the remainder 75 and halve.
Therefore, the result is "A", and the remainder 76 is "0".
become. The direction code 52 is obtained by repeating the calculation in the same manner. The direction code 52 is converted into the direction code "O" to "7" as described in the conventional example.
3, which can be easily obtained by having only the lower three bits of the direction code 52. The pattern reproduced from this direction code is shown in Figure 4. It is not significantly deformed compared to the original pattern. In other words, with the conventional method, the direction code 2 component would have disappeared, but
This inconvenience can be prevented. Also, Figure 5 is the direction code%
This example shows the case of compression.

The method of calculation and the processing of the remainder are the same as in the case of compression to % as explained in conjunction with FIG. In other words, direction code 81 is calculated by adding direction codes 70 and 71 and calculating %
The result becomes "9".

The remainder at this time is code 85. The direction code 82 is calculated by adding the codes 71 and 72 and the remainder 85 and converting it to %. The remainder at this time is 86. To calculate code 83, skip one code, add codes 73 and 80, and the remainder 86, and calculate %. Repeat the same process below.

Column 55 shows the calculation results at this time. Column 56 is a value containing only the lower three bits of the direction code in column 55. Figure 4C shows a pattern reproduced from this direction code, which is not significantly deformed compared to the original pattern shown in Figure 4A. I mentioned the method of compressing to %, %, but similarly, %,
，′! Compression of A...(N-1)/N is also %,%
You can apply the case of

If the compression ratio is (N-1)/N, the operation of adding up to N direction codes and the remainder from the previous operation and halving the result is (N-1). If the calculation is repeated several times, and each time the number of direction codes exceeds N, the remainder resulting from the calculation is left as is, and the calculation is restarted using newly adjacent direction codes, thereby achieving a compression of (N-1)/N.

FIG. 7 shows the configuration of a device that realizes this idea.

31 is an input terminal to which the output from the binarization circuit is applied, and 32 is a memory for storing input patterns.

33 is a command shift pulse of the control circuit 34, which changes the code to 1.
The record converters 35 and 36 that output the record converter 35 and 36 are shift registers that store the output of the code converter 33 in response to shift pulses from the control circuit 34.

Note that for the contents of shift register 35, shift register 3
The content of 6 is the previous code. 37 is an adder circuit,
The outputs of the shift registers 35 and 36 (ie, adjacent codes) and the remainder from the % circuit 38 are added.

This % circuit 38 is a circuit which halves the output of the adder circuit 37, and returns the resulting remainder to the adder circuit 37 and inputs the lower three bits of the output to the code string memory 39. 40 is a standard pattern memory, and a determination circuit 41 receives the output of the code string memory 39 and the standard pattern memory 40.
Compare the output from , and output what pattern (character) it is.

Note that the encoding conversion section 33 outputs a code as shown in FIG. Further, the addition circuit 37 and the % circuit 38 are connected to the control circuit 34.
The respective calculations are performed according to the calculation instructions from the . 8th
The figure shows the operation of the control circuit 34 when compressing a coded string to (N-1)/N. %, processing 94 must be performed every time processing 91 and 92 are performed. That is, one calculation is performed using two shift pulses, and this is the same operation as shown in FIG. 5A.

When compressing to %, processing 94 will be performed every time processing 91 and 92 are performed twice, and by performing the calculation twice with three shift pulses, the same operation as shown in Figure 5 will be performed. Become. The control circuit 34 is controlled so that two shift pulses are output at the start of code string scaling, and the remainder from the frequency divider circuit 38 is O (zero). That is, under the control of the control circuit 34, the encoding converter 33, shift registers 35, 36, adder circuit, and % circuit 38 perform predetermined operations as described above to obtain a compressed encoded signal.

This signal is stored in the memory 39, and compared with the contents of the memory 40 by the determination circuit 41 to perform a determination operation.
In addition, although one block is provided as the % circuit 38 in FIG. 7, in the actual circuit configuration, the adder circuit 37
The lower 1st bit of the output is the remainder, and the 2nd, 3rd, and 4th bits are output and input to the code string memory 39.

In the above practical example, as shown in the direction code Figure 6, for every % rotation clockwise, +1 (plus 1) % counterclockwise.
-1 (minus 1) is added each time it rotates, thus giving a value of "7" or more.

The reason for doing this is to add the two direction codes and convert the result into a percentage. For example, when the direction code changes from "7" to "O", if this is directly added and converted into a percentage, the direction becomes "3", which is a completely different direction. If we add +1 for each % rotation in the clockwise direction as in this proposal, the direction of "O" when it changes from "7" to "0" is "8".
], and the result of the direction code calculation is "7", which is convenient. The direction code is 3 bits, from "O" to "
If the number is up to 7, the direction code will be from 0 to 7.
, or when it changes from "7" to "0", it becomes discontinuous and becomes inconvenient for the calculation of the direction code. However, the direction code does not have to be 3 bits or more as shown in FIG. 6; it may be calculated using 3 bits if the above-mentioned discontinuity is taken into account.

That is, it is detected whether the direction code crosses from "0" to "7" or from "7" to "O" (discontinuous point) or not (in the encoding conversion section), and if it does not cross, Perform normal calculations, and if it crosses (changes discontinuously), "7"
should be calculated by setting it to -1, [6] to -2, and "5" to -3. As is clear from the above practical example, according to the present invention, the input pattern can be compressed in a state closer to the actual pattern, and more accurate pattern recognition can be performed.

[Brief explanation of the drawing]

Figures 1A to 2 and 3A to 3C are diagrams each explaining the pattern encoding and compression method in the conventional device; Figure 2 is a block diagram of a conventional pattern recognition device; , Fig. 5A and Fig. 6 are diagrams illustrating a pattern encoding and compression method by a pattern recognition device according to an actual example of the present invention, Fig. 7 is a block diagram of the same device, and Fig. 8 is a It is an operation diagram of the main part. 33... Code converter, 34... Control circuit, 35, 36... Shift register, 37...
.... each addition time, 38 ...% circuit, 41 ... judgment circuit.

Claims (1)

[Claims] 1. Track the contour of the input pattern, convert each bit to a direction code string defined by direction, and use this converted direction code string to perform pattern recognition in a device that stores the direction code. a second shift register that stores the output of the first shift register; a 1/2 circuit that halves the output of the adder circuit and outputs the remainder to the adder circuit; the addition circuit that adds the output of the first shift register, the output of the second shift register, and the remainder from the 1/2 circuit; and a code memory section that stores the quotient that is the output of the 1/2 circuit. , output N-1 shift pulses to the first and second shift registers for N direction codes, and
and a control unit configured to write N-1 quotients from the two circuits as new direction codes into the code memory section, and compress the direction code string to (N-1)/N. pattern recognition device.