JPS5940797A - Time switch circuit - Google Patents

Abstract

PURPOSE:To realize a time switch having a high through-put with few hardware, by constituting a channel memory with a multiplexer formed into pipeline and a shift register so as to execute sequential write and random read at the same time and forming the operating speed depending on the operating speed of the register. CONSTITUTION:The multiplexers 23-28 select either one of two inputs give output according to a common control signal S1. The address is split into three partial addresses A1(1-bit), A2(1-bit), A3(2-bit) corresponding to the number of the stages of the pipeline of the multiplexers. The partial address A1 of the least significant is decoded at a decoder 44 and applied to the 1st stage multiplexer groups 23-28 as the control signal S1. The most significant partial address A3 is decoded at a decoder 46 via a two-stage shift register 43 driven with a clock pulse CLK1 and applied to the 3rd stage multiplexer 32 as the control signal S3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a time switch circuit that plays a central role in a communication path device of a digital exchange together with a space switch.

[Prior art]

As is well known, time switches are used in communication path devices of digital exchanges, and have the function of performing time-division switching by changing the temporal order of input data.

A conventional example of this type of time switch will be explained with reference to FIG. That is, the conventional time switch is composed of a call memory 1, a holding memory 2, and a counter (not shown in FIG. 1), and input data to the call memory 1 in a fixed order using the output from the counter as an address. The time order of input data is exchanged by repeating writing, ie, sequential writing, and reading, ie, random reading, using an arbitrary address using the output of the holding memory 2 as an address. Since this is realized with memory, it is suitable for I,S* nuclear technology, and has rapidly developed with the recent progress in LSI technology.

However, in the switch using the memory described above, the throughput of the switch is limited by the cycle time of the memory. The cycle time of memory is slower than the operation time of registers and logic gates, and the cycle time tends to increase as the storage capacity increases. On the other hand, to improve the processing power of the time switch,
It is necessary to simultaneously increase memory capacity and reduce cycle time. For this reason, it has been extremely difficult to improve processing performance with conventional time switches that use memory.

[Purpose of the invention]

The present invention solves the above-mentioned conventional problems and realizes a high throughput time switch with a small amount of hardware.

[Summary of the invention]

In order to achieve the above object, the present invention configures a call memory with a shift register and a pipelined multiplexer so that sequential write and random read can be executed simultaneously, and the operation speed is determined by the operation speed of the register. This is what I did.

[Embodiments of the invention]

FIG. 2 is a diagram illustrating the principle of the present invention, and for convenience, shows four time switches. In Figure 2, ]1 is 4 for #1 to #4.
12 is a multiplexer with a storage function, and 13 is a holding memory. The multiplexer 12 with a storage function includes a latch 12-1 that stores four pieces of data, a multiplexer 12-2 that selects and outputs one of the four input data according to the address information ADR supplied from the holding memory 13, and It consists of a latch 12-3 that holds the output data of the multiplexer 12-2. Shift register 11, latch 12
-3, the holding memory 13 operates with the clock pulse CLK, and the latch 12-1 operates with the frame pulse FP having a frequency a four times that of the clock pulse CLK.

A timing chart for explaining the operation of FIG. 2 is shown in FIG. In the frame shown in FIG.
-B4 input data Din are sequentially input to the shift register 11 one by one per clock pulse CLK following A1 to A-1 taken into the shift register 11 in the previous frame.

On the other hand, data A1 to A4 stored in #1 to #4 of the shift register 11 are simultaneously captured into the latch 12-1 by the frame pulse FP. In this frame, the holding memory 13 converts address ADR into clock pulse C
#3, #1, -#:4 according to LK.

Suppose that #2 is output. According to this address A, Drt, the multiplexer 12-2 outputs the corresponding data A3,
AI, A4. A2 is sequentially outputted via the latch 12-3. Therefore, in this frame, data 81 to B
Writing of A1 to A4 and reading of A1 to A4 are executed simultaneously.

Figure 4 shows an embodiment of the present invention that is a development of Figure 2, with 12
An example of a multiple time switch circuit is shown. In this embodiment, the number of bits of data will be explained as 1 bit, but if the data is 8 bits, eight circuits shown here may be provided, and the present invention can be applied to data of any number of bits. Needless to say.

In FIG. 4, 21 is a 12-stage shift register, 22 is a 12-bit latch, 23 to 31 are two-way multiplexers that output either one of two input data according to a control signal, and 32 is a 12-stage shift register. Which one of them is a three-way multiplexer that outputs one in accordance with a control signal, and 32 to 41 are delay elements for pipelining multiplexers 23 to 32, each of which is constructed of the same circuit as one bit of the shift register 22. be done. 42 is a register, 43 is a two-stage shift register, and as expected,
This provides a delay to the control signal when pipelining the multiplexer. 44 and /15 are 1-bit decoders, and 46 is a 2-bit decoder. 47 is a circular shift register, which has the function of a holding memory for storing random addresses. 48 is a 1-bit latch.

The shift register 21 receives a clock pulse c L K i
VC is a well-known shift register that takes in input data Din and shifts it to the next stage. The latch 22 simultaneously captures and holds data in all stages of the 21 shift registers in accordance with the frame pulse FP. The output of this latch 22 is connected to each input terminal of multiplexers 23-28.

Each of the multiplexers 23 to 28 follows a common control signal S1, and one of the two selects and outputs the selected one. This output is taken into registers 33-38 which operate according to clock pulses CT, K1. Registers 33.311 are connected to multiplexer 29, registers 35.311 are connected to multiplexer 29, and registers 35.
36 is connected to the multiplexer 30, and registers 37 and 38 are connected to the multiplexer 31.

These multiplexers 29 to 3] share a common control signal S2.
Accordingly, either one of the two human forces is output. This output is stored in registers 39-41 which operate according to clock pulse CT. Registers 39-4
The output of 1 is connected to a 3-way multiplexer 32. The multiplexer 32 selects and outputs any one of the three input data according to the control signal S3. The circular shift register (holding memory) 47 stores 121 pieces of 4-bit address information in arbitrary order that designate any stage of the 12 stages of the shift register 21, and is output in accordance with the clock CLK1. . This address consists of three partial addresses A1 (1 bit), A2 (1 bit), A, 3 (
2 bits). The lowest partial address A1 is def-upped by the decoder 44, and as a control signal S1,
It is supplied to the first stage multiplexer group 23-28. The next partial address A2 is decoded by the decoder 45 via the register 42 driven by the clock pulse cLKl, and is supplied to the second stage multiplexers 29 to 31 as the control signal s2. The most significant partial address A3 is decoded by a decoder 46 via a two-stage shift register 43 driven by four clock pulses CLK1.
The control signal s3 is supplied to the third stage multiplexer 32.

FIG. 5 is a timing chart for explaining the operation of FIG. 4. A frame pulse FP indicates a frame division, and in each frame, 12 pieces of data are taken into the shift register 22 and 12 pieces of data taken in the previous frame are read out. Between 1 and 120 of CLK1, data 1)1 to l]12 are taken into the shift register 21 (FIG. 5C). Similarly, C.L.K.
Data 01-c12, CL K between 13-24 of 1
Data (11 to d 12 are taken in between 25 and 36 of CL K 1. Frame pulse FP is generated at the 12th of CL K 1, and data l that was taken into the shift register 21 in the previous frame) 1 to b12 is taken into the latch 22 (FIG. 5D). Similarly, data c1 to c12 are taken in at the 24th position of CLK1.

On the other hand, the read address for the data captured in the previous frame is sent out from the holding memory 47 in synchronization with CLK1. For example, during 12 cycles from the 12th cycle of CL Kl, random addresses bA-bL for reading data bl-b12 are sent out. Focusing on bA among these addresses, the decode signal 81 (FIG. 5E) of the lowest address bAl is input to multiplexers n to a, and the data (+) selected by each multiplexer 23 to 28 is input to multiplexers n to a. AI) is taken into registers 33-38K (FIG. 5-1). That is, six pieces of data are first selected from among the data b1 to b12 in the latch 22 and held in the registers 33 to 38. After the partial address bA2 is delayed by one clock, it is supplied to the decoder 45 and becomes the decoded signal S2 (FIG. 5F).
). In response to this signal, data (bA2) is selected by multiplexers 29-3 and taken into registers 39-41 (FIG. 5, 1). Therefore, among the data b1 to b12, registers 39 to 41 contain partial addresses bA1 and b.
The three pieces of data selected in A2 are retained. After the most significant part address is further delayed by one clock, it is supplied to the decoder and becomes the decoded signal S3 (FIG. 5G). This signal causes the multiplexer 32 to select one of the three data (bA2) stored in the registers 39-41.

This is held in the latch 27 as (bA3) and output to the outside.

The above operations are performed continuously for addresses bB, old and old, . . . bL, and so on. That is, by pipelining the multiplexers, reading of random addresses is executed in parallel at the same cycle as input data is taken into the shift register. Moreover, since taking in data to the shift register is equivalent to sequential writing, it is clear that the device has a time switching function using sequential writing and random reading.

In the embodiment shown in FIG. 4, the registers 33 to 41 used for pipeline formation all have the same function as one bit of the shift register 21, and are two registers that operate with opposite phase clocks. Consists of a latch. That is, while data is being taken in by the former stage latch, the latter stage latch holds the data that has already been taken in. If this front-stage latch is regarded as the front-stage multiplexer, and the rear-stage latch is regarded as the storage function of the latter-stage multiplexer, each multiplexer becomes a circuit module with the same configuration, each having a latch at its input end and output end. For example, multiplexer 23
A multiplexer a1 with a memory function consisting of a latch 22 and a front-stage latch of a register 33, a multiplexer 29 with a memory function, a rear-stage latch of registers 33 and 34, and a front-stage latch of a register 39; Lunch 4
It can be seen as a multiplexer C with a memory function consisting of 8.

FIG. 6 shows an example of a circuit in which a multiplexer with a memory function is constructed of MOS transistors. FIG. 6(a) shows a configuration in which a mask lunch 50, a multiplexer 51, and a slave latch 52 are each provided in a stand, all of which are well-known circuits.

The master latch 50 includes a transfer gate T1 and an inverter 1, and a transfer gate T2 and an inverter 12.
Two dynamic latches consisting of The input data INI and IN2 are input to the inverter ■ when the transfer gates T1 and T2 are made conductive by the clock φ.
1 and ■2 are captured and held in the gate capacitances of 2.

This data is input to the slave latch 52 by selecting one of them by a two-man multiplexer 51 consisting of transfer games T3 and T4. The slave latch 52 is connected to the transfer gate T5 and the inverter ■3.
It is driven by a clock j having an opposite phase to the clock φ of the master latch 5o, and captures and holds data. The transfer gate T5 of this slave latch 52 outputs the selection signal A1B to the multiplexers T3 and T4 of 51.
can also be omitted by using signals A-a and B-oka that are synchronized with the clock signal Oka. Figure 6 (1)
) shows this.

〔Effect of the invention〕

As explained above, according to the present invention, sequential writing is performed in a shift register, and random reading is performed in a pipeline multiplexer made up of a register and a multiplexer, so both operations are executed at approximately the operating speed of the shift register. be done. This is extremely fast compared to memory cycle times. Furthermore, since writing and reading can be performed simultaneously, the number of cycles required is half that of a memory in which writing and reading are performed separately. Furthermore, since data is written to memory circuits such as registers and latches every cycle or every frame, dynamic circuits can be used. Therefore, it can be realized with a small number of elements and low power consumption. Furthermore, since small-scale multiplexer modules with memory functions can be repeatedly arranged in parallel, design is easy and high-density integration is possible, making it suitable for LSI. That is, high speed and large scale, which are impossible with conventional memories, can be achieved at the same time, and there are five advantages in that digital exchanges can be made smaller, consume less power, and become more economical.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional time switch circuit, Fig. 2 is a diagram of the principle configuration of the present invention, Fig. 3 is a timing diagram for explaining the operation of Fig. 2, and Fig. 4 is an implementation of the present invention. FIG. 5 is a timing diagram for explaining the operation of FIG. 4, and FIG. 6 is a diagram showing a circuit example of a multiplexer with a memory function. 11...° shift register, 12...Multi with memory function Fig. 2 11

Claims (2)

[Claims] (1) Consisting of a first means for storing time-division multiplexed input data according to the input order and reading it according to an address supplied from the outside, and a second means for supplying an address to the first means. , in the time switch circuit for outputting the time-division multiplexed and input data in an order different from the order in which the data was input, the first means;
a shift register that sequentially stores the time-division multiplexed and input data; and a plurality of data stored in the shift register are latched in parallel and selected one by one according to the address supplied from the second means. What is claimed is: 1. A time switch circuit comprising a multiplexer with a memory function for outputting a time signal. (2) The multiplexer with a memory function has a small-scale multiplexer module with a memory function arranged in a tree shape.
2. The time switch circuit according to claim 1, wherein the time switch circuit is configured to be connected in multiple stages, and each stage is operated in a pipeline.