JPS6381691A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily realize a serial memory with a storage capacity to meet a use by outputting data held in the corresponding bits of a data register before an input data are inputted to them. CONSTITUTION:In the respective period of a serial clock signal, the input data to be inputted in the serial memory are inputted alternately in written data registers WRA, WRB, and at the next period, they are inputted in the corresponding bits of the data register. Besides, the data of the data register to be outputted are read-out to a read-out data register RRA or RRB. Similar operations are repeated thereafter. Accordingly, the plural number of the data register of s-number of dual port memories connected in a series state function as if they are shift register connected in a series state. Then, the serial memory with the storage capacity to meet the use can be easily realized without providing any external parts other than the chip of a semiconductor memory device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
This article relates to a technology that is particularly effective when used in dual-boat memory, etc., which has both a random access boat that performs random input/output in units of one bit or several bits, and a serial access boat that performs serial input/output in units of word lines. It is something.

[Conventional technology]

Regarding dual boat memory, which is used as frame buffer memory for images to display characters, figures, etc. on the screen of a CRT (cathode ray tube), for example,
It is described on pages 243 to 264 of Nikkei Electronics J, March 24, 1986, published by Nikkei McGraw-Hill.

[Problem that the invention seeks to solve]

The serial access boat of the dual boat memory described above is provided with data registers corresponding to the multiple data lines that make up the memory array, and each bit of the data register is sequentially used for serial input/output. A data selector is provided for connection to the complementary common data line. Each switch MO3 that constitutes the data selector
A data register selection signal is supplied to the gates of the FET pair, which is formed by loop-shifting a logic 11'' signal that is sent to the first bit specified by the Y address signal supplied from the outside at the pointer. This allows data of any bit length to be input/output from any focus to a data register that holds data at a fixed position.

However, as the quality of image systems becomes higher and the pixels of CRTs become more precise, the bit length corresponding to one word line, or one horizontal scanning line, increases, and a large-capacity serial memory is required. It's starting to look like this. In order to construct such a serial memory using relatively small-capacity dual-boat memories, multiple dual-boat memories must be logically connected in series. dual boat
Memories do not have the ability to be cascaded in serial form as is. Therefore, it is necessary to adopt a method in which a plurality of dual boat memories are connected in parallel to the address bus and the data bus, and these dual boat memories are apparently connected in a cascaded manner. In this case, it is necessary to provide a counter circuit and a timing control circuit outside the memory chip to sequentially supply chip selection signals to the plurality of dual boat memories, which not only increases the cost of the serial memory but also increases the cost of the serial memory. This complicates the control process.

An object of the present invention is to provide a semiconductor memory device such as a dual port memory having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical embodiments disclosed in this application is as follows. That is,
The external terminal for serial data output outputs the data held until then at the pin point before inputting the input data that is input from the external terminal for serial data input in synchronization with the serial clock signal to the corresponding bit of the data register. This is what is output to.

[For production]

According to the above means, logically consecutive addresses are assigned by connecting a plurality of semiconductor memory devices in series/column form, and the external terminal for serial data output is assigned a next logically consecutive address. By coupling to the external terminal for serial data input of a storage device, multiple data registers on D'Z on multiple semiconductor substrates can be used as a continuous shift register with a large focus length, and the memory of each semiconductor storage device can be It is possible to realize a serial memory having an arbitrary storage capacity that is equivalent to the number of memory cells.

〔Example〕

Figure 3 shows a dual boat boat to which this invention is applied.
A block diagram of one embodiment of a memory is shown. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The dual boat memory of this embodiment has a basic configuration of dynamic RAM, and includes a random access boat that is accessed in 4-bit units, and a serial access boat that performs serial input/output of stored data in word line units. A boat will be provided. This allows the dual boat memory to perform a series of serial I/O operations while simultaneously accessing random access boats. The random input/output circuit RIO included in the random access boat is provided with a logic operation circuit for performing rask operations, etc., and is provided with a function control circuit FC for controlling this logic operation circuit. The serial access boat has a serial input/output circuit SIO.
is provided, and normally four serial input/output terminals 5rO1-
Through Sr04, storage data corresponding to the four memory arrays is serially input/output simultaneously. However, in certain modes of operation of dual boat memory,
The serial input/output terminal 5IOI is dedicated as an external terminal for serial data output, and the serial input/output terminal 5I02 is dedicated as an external terminal for serial data input, and the stored data corresponding to the four memory arrays is used as an external terminal for serial data input and serial data output. The data is input and output in time series through external terminals, and has a so-called x1 bit configuration.

The dual port memory receives a row address strobe signal RAS and a column address strobe signal CA used in normal dynamic RAM from an external device.
In addition to control signals such as S and write enable signal WE, there is also a data transfer control signal DT10B used to control data transfer between the random access boat and the serial access boat, and input/output switching of the serial access boat. Serial output control signal SO used for control
E and a serial clock signal sc used as a synchronization signal during serial input/output are input.

Although not particularly limited, the random access boat of the dual boat memory of this embodiment is provided with four memory arrays M-ARYI to M-ARY4, and sense amplifiers SAI to SAI correspond to the respective memory arrays. S
A4. Column switches C3WI to C3W4 are provided. Furthermore, a random access boat column address decoder RCD and a row address decoder RD are provided in common to memory arrays M-ARYI to M-ARY4. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. FIG. 2 exemplarily shows the memory array M-ARYI and its peripheral circuits.

In Figure 3, the memory array M-ARYI has m+1 word lines WO to Wm arranged in the vertical direction of the figure and n+lMi complementary data lines DO-Maki to Dn arranged in the horizontal direction of the figure. -D and (m+1)X (n+1)( arranged at the intersections of these word lines and complementary data lines)
[! il memory cells.

Each word line is coupled to a row address decoder RD;
One word line designated by the X address signal AXO=AXi is selected and designated.

Row address decoder RD is row address buffer R.
Complementary internal address supplied from ADB ・Signal -ax
Q ~ axi (here, for example, X supplied from the outside)
An internal address signal axO having the same phase as the address signal AXO and an internal address signal axQ having the opposite phase are collectively expressed as a complementary internal address signal axO. The same applies hereinafter) is decoded, one word line designated by the X address signals AXO to AXi is selected, and set to a high level selected state. The word line selection operation by the row address decoder RD is as follows:
This is performed according to the word line selection timing signal φX supplied from the timing control circuit TC.

Row address buffer RADB receives a row address signal supplied from address multiplexer AMX, forms complementary internal address signal axo-axi, and supplies it to row address decoder RD. In the dual boat memory of this embodiment, the X address signals AXO to AXi for specifying the row address and the Y address signal AYO=AYi for specifying the column address are transmitted through the same external terminals AO to Ai. A so-called address multiplex method is adopted in which data is supplied in a time-divided manner. Therefore, in synchronization with the falling of the row address strobe signal RAS, the X address signals AXO to AXi are applied to the external terminals A, and in synchronization with the falling of the column address strobe signal CAS, the Y address signals AYQ to AYi are applied to the external terminal A.
It is supplied to O to Ai. Further, the dual port memory of this embodiment is provided with an automatic refresh mode power (a word line to be refreshed in this automatic refresh mode) for reading and rewriting the data stored in the memory cell within a predetermined cycle. A refresh address counter REFC is provided for sequentially specifying.

Address multiplexer AMX operates according to timing signal φref supplied from timing control circuit TC.
X address signals AXO to AXi supplied via external terminals AOxAi and refresh address counter REF
Refresh address signal cxQ-c supplied from C
xi is selected and transmitted to the row address buffer RADB as a row address signal. That is, in a normal memory access mode in which the timing signal φref is at a low level, the X address signals AXO to AXi supplied from an external device via the external terminal A O-A i are selected, and the timing signal φref is at a high level. In the automatic refresh mode, the refresh address signal c x Q - c x i output from the refresh address counter REFC is selected.

As mentioned above, since the X address signals AXO to AXi are supplied to the external terminals AO to At in synchronization with the falling edge of the row address strobe signal RAS, the acquisition of the row address signal by the row address buffer RADB is controlled by the timing control circuit. This is performed in accordance with a timing signal φar generated by detecting the fall of row address strobe signal 7X1 at TC.

On the other hand, complementary data line DO- of memory array M-ARYI
DO-Dn-Dn is coupled to the corresponding switch MO3FET of the column switch C3WI on one side, and is further selectively connected via these switches MO3FET to the complementary common data line DI (herein, the complementary common data line DI). The non-inverted signal line CDI and the inverted signal line CDL constituting the data line are collectively expressed as a complementary common data line CDO (the same applies hereinafter).

The column switch C3WI is constituted by a fi+l pair of switches MO3FET each coupled to a corresponding complementary data line. These switches MOS FET
The other terminal of the pair is commonly coupled to a non-inverted signal line CDI or an inverted signal line CDI forming a complementary common data line. Thereby, column switch C3WI selectively connects complementary data lines Do-Do to [)n-pn and common complementary data line CDI. The gates of each pair of two switches MO3FET constituting the column switch C3WI are connected in common, and are supplied with a data line selection signal formed by a column address decoder RCD for a random access port.

The random access port column address decoder RCD decodes the complementary internal address signals ayQ to ayi supplied from the column address buffer CADB, and selects the data line according to the data line selection timing signal φyr supplied from the timing control circuit TC. A selection signal is formed and supplied to column switches C3WI to C3W4.

The column address buffer CADB receives a timing signal φac generated by detecting the fall of the column address strobe signal ξτ3 in the timing control circuit TC.
Accordingly, the Y address signal AYO-AYi supplied via the external terminal AO-Ai is input and held, and the complementary internal address (K No. a)'O-a)'1
is formed and supplied to the random access port column address decoder RCD.

Complementary data line DO・]~l of memory array M-ARY1
) n −1) n is the sense amplifier S on the other hand.
It is coupled to the corresponding unit circuit of AI, and further serially
It is coupled to a corresponding unit circuit of the data register DR1 of the access port.

Each unit circuit of the sense amplifier SAO has a launch consisting of two cross-connected CMOS inverter circuits as its basic configuration. These sense amplifier unit circuits receive a timing signal φp supplied from a timing control circuit TC.
1. Amplify the minute read signal of the memory cell which is activated by a and is output to the corresponding complementary data line. It is a binary signal of high level/low level.

A complementary common data line CDI to which complementary data lines designated by Y address signals AYO to AYi are selectively connected is coupled to a random access boat input/output circuit RIO. This random access port input/output circuit RIO includes memory arrays M-ARY2 to M-ARY.
Complementary common data lines CD2 to CD provided corresponding to 4
4 are similarly combined.

The random input/output circuit RIO is brought into operation by the timing signal φr- supplied from the timing control circuit TC in the random access port write operation mode of the dual port memory, and the input/output terminal I
The write data supplied from an external device via 01 to IO4 is used as a complementary write signal, and the complementary common data line -
It is transmitted to CD1 to -C4D4. In the random access boat read operation mode of the dual boat memory, the dual boat memory is put into an operating state by the timing signal φrr supplied from the timing control circuit TC, and the complementary common data is transmitted via the edges D1 to CD4. The read binary signal of the memory cell is further amplified and sent from input/output terminals 101 to 104.

Furthermore, this random input/output circuit RIO performs various operations between the data read from the memory cell and the input data and rewrites the data using an operation write cycle similar to the read/modify write function, although this is not particularly limited. A logical operation circuit is provided to perform the following.

This logic operation circuit is provided with various operation modes for performing rask operations and the like.

The operation mode of the logic operation circuit is selected and specified by the function control circuit FC. Function control circuit FC is connected to external terminal A
It includes a code register that holds the operation code supplied via O-A3, and a decoder for decoding the operation code and selecting and specifying the operation mode of the logic operation circuit. The operation code is column address strobe signal CAS
is set to a low level prior to the row address strobe signal positive π1, and is supplied to the dual port memory via external terminals AO to A3 in an operation mode setting cycle in which the write enable signal WE is set to a low level at the same time. Further, although not particularly limited, a specific combination of operation codes may be achieved by dedicating the serial input/output terminal 5IOI as an external terminal for serial data output and dedicating the serial input/output terminal 5IO2 as an external terminal for serial data input, as described later. It is used as an internal control signal sm for setting the serial memory mode.

On the other hand, the serial access port of the dual port memory of this embodiment includes n+l bit data registers DRI to DR4 provided corresponding to complementary data lines of each memory array, and data selectors DSL1 to DSL.
4, a pointer PNT provided commonly to these data registers and data selectors, a serial access boat column address decoder SCD, and a serial input/output circuit SIO. Note that a plurality of pointers PNT and serial access boat column address decoders SCD may be provided depending on the arrangement of the memory array on the semiconductor substrate.

As will be described later, the data register DRI corresponds to a flip-flop consisting of two cross-connected CMOS inverter circuits provided corresponding to each complementary data line of the memory array M-ARY1, and input/output nodes of these flip-flops. It is composed of n+1 pairs of MO3FET switches for data transfer provided between a non-inverted signal line and an inverted signal line of complementary data lines. The data transfer switch MOSFET is controlled by the data transfer timing signal φdt supplied from the timing control circuit TC.
They are turned on at the same time.

Each bit of data register DPI is further coupled to a corresponding switch MOSFET pair of data selector DSLI. Data selector DSLI is data register D
Each bit of RI and complementary common data for serial input/output are C
Selectively connect D5I. Data selector DSL1f
c Each pair of switch MO5FETs making up the pointer P
It is turned on according to the data register selection signal supplied from NT. When the dual boat memory is in serial memory mode, the data selector DSLI selects the corresponding bit of the data register DRI in accordance with each cycle of the serial clock signal SC supplied from an external device. The data held up to that point is output via the external terminal for serial data output, and the input data supplied via the external terminal for serial data input is input to the data register DRI corresponding to each cycle of the serial clock signal SC. It has a function of selectively shifting the data register selection signal sent from the pointer PNT in order to input it to the previous bit I.

The pointer PNT is constituted by a shift register of fi+l bits, and the output terminal ps of the last bit is coupled to the input terminal of the first bit.

Pointer PNT performs a loop-shaped shift operation in accordance with shift clock timing signal φC supplied from timing control circuit TC in various serial input/output operation modes of the dual port memory. Each bit of pointer PNT is further coupled to a corresponding output terminal of a serial access boat column address decoder SCD.

The serial access boat column address decoder SCD decodes the complementary internal address signals yO~a-yi supplied from the column address buffer CADH, and decodes the first bit of serial input/output specified by the Y address signals AYO~AYi. pointer PNT corresponding to
In other words, in the serial input/output mode, the X address signals AXO to AX
The word line is selected by i, and the Y address signal AYO
~AYi specifies the first column address for serial input/output. Pointer PNT by column address decoder SCD for serial access boat
The logic "1" signal written in the designated bit is shifted in a loop within the pointer PNT according to the timing signal φC. By shifting this logic '1'' signal, a high-level data register selection signal is sequentially supplied to the data selector DSL1, and each bit of the data register DR1 is sequentially transferred to the complementary common data line CDS for serial input/output. This allows the dual port memory of this embodiment to start serial input/output of stored data from any column address and end at any bit.

As will be described later, the serial input/output circuit SIO includes main amplifiers MA1 to MA4 and write amplifiers WAI to WA4 provided corresponding to each serial input/output complementary common data set DSI to CD54, and a serial input/output terminal 5IOI.
~Data input buffer D provided corresponding to 5I04
IBI~DIB4, data output buffer DOB1~D
Two write data registers WRA to hold input data in OB4 and serial memory modes.

Data output buffers DOBI to DOB 4, including WRB and two read data registers RRA, RRB, etc. for holding output data, are supplied from the timing control circuit TC in the read data transfer cycle of the dual boat memory. It is activated by the high level of the timing signal φsr, and the read data that is output via the corresponding complementary common data for serial input/output 13cDs1-CDS4 and amplified by the corresponding main amplifier is sent to the serial input/output terminals 5101 to 5104.
Output from to an external device. Further, the write amplifiers WAI to WA4 of the serial input/output circuit 310 are put into an operating state by the high level of the timing signal φsw supplied from the timing control circuit TC in the serial data writing cycle of the dual port memory, and Write data supplied from an external device via input/output terminals 5IOI to 5I04. It is used as an IF write signal and is transmitted to the corresponding complementary common data lines for serial input/output DS1 to DS4.

In the dual port memory of this embodiment, the serial output signal of the normal serial input/output circuit S20 is simultaneously outputted in 4 bits via the four serial input/output terminals 5I01 to 5104 as described above. However, in the case of a serial memory mode in which a large capacity serial memory is configured by connecting multiple dual boat memories in series and assigning logically consecutive addresses, the serial input/output terminal 3101 is used for serial data output. The serial input/output terminal 5IO2 is dedicated as an external terminal and as an external terminal for inputting serial data. Serial input/output circuit S in such serial memory mode
The operation of IO will be explained in detail later in 9. ■Explain. In addition, this serial memory mode uses random input/output circuit R.
It is specified by an internal control signal sm which is set to high level in a specific combination of operation codes of IO.

The timing control circuit TC receives a row address strobe signal R, a column address strobe signal σAS, and a write enable signal 71. which are supplied as control signals from the outside. The various timing signals mentioned above are formed and supplied to each circuit using the data transfer control signal T10E and the serial output control signal SOE. Furthermore, a timing signal φC and the like for synchronizing serial input/output operations is formed using a serial clock signal SC supplied from the outside, and is supplied to the pointer PNT and the serial input/output circuit SIO.

The operation mode of the dual port memory is specified by appropriate combinations of control signals. For example, first the row address strobe signal RAS becomes low level, then the column address strobe signal CAS becomes low level. If the write enable signal WE is at a high level at this point, the normal random access boat read operation mode is set. Row address strobe signal RAS and column address strobe signal σA
Write enable signal WE at both falling edges of S
is low level, normal random access
This is considered to be the boat's moss-filling operation mode. Furthermore, if the write enable signal WE is at a high level when the row address strobe signal RAS falls and is at a low level when the column address strobe signal CAS falls, an operation write cycle using various operation modes of the logic operation circuit is performed. It is said that Further, at the falling edge of the row address strobe signal RAS, the write enable signal WE is at a high level, and the data transfer control signal DT
When 10E is at a low level, it is a read data transfer cycle for transferring read data from the memory array to data registers DRI to DR4 and outputting it serially in synchronization with the serial clock signal SC. In this read data transfer cycle, after the data read from the memory cell connected to the selected word line is completed and the data transfer control signal DT10E is returned from low level to high level, the data transfer timing signal φd
t is formed and the read data is transferred to the data register DRI.
~Transfer to DR4 and serial clock signal SC
Serial output operation is started in synchronization with .

Next, when the data transfer control signal DT10E and the write enable signal WE are at a low level and the serial input/output control signal SOE is at a high level at the falling edge of the row address I/lobe signal RAS, a serial data write cycle is started. Serial input/output terminal 3
Serial write data supplied via 101-5IO4 is sequentially input to data registers DRI-DR4.

Furthermore, if the write enable signal WE is at a low level together with the data transfer control signal DT10E at the falling edge of the row address strobe signal RAS, and the serial input/output control signal SOE is at a low level, it is considered a write data transfer cycle, and the transfer timing is Signal φ(H
is supplied to data registers DRI-DR4. As a result, the data transfer switches MOS FET are turned on all at once, and the write data set in the data registers DRI to DR4 by the serial data write cycle is coupled to the selected word line of the memory array (n+1 bits). are input to all memory cells at once. A serial write operation using a serial access port is accomplished by performing the serial data write cycle described above followed by a combination of write data transfer cycles.

On the other hand, when column address strobe signal 7τ lower is changed from high level to low level prior to the fall of row address strobe signal RAS, so-called σ
The τ1 before RAS refresh mode is set. At this time, if the write enable signal W1- is at a low level at the falling edge of the row address strobe signal rX3, it is considered an operation mode setting cycle, and the external terminal AO
~The operational code supplied via A3 is the function control circuit F.
It is loaded into a register in C.

FIG. 1 shows a circuit block diagram of an embodiment of the serial input/output circuit SIO of the dual port memory shown in FIG.

As mentioned above, the dual port memory of this embodiment is provided with four memory arrays M-ARY1 to M-ARY4, and complementary common data lines for serial input/output CDSL/ CD31～CD
S tunnel/CD54 is provided. Serial input/output circuit S1
0, these complementary common data lines are coupled to the input terminals of the corresponding main amplifiers MAL-MA4 and to the output terminals of the corresponding write amplifiers WAI-WA4. The main amplifiers MAL to MA4 further amplify the read signals serially output via the corresponding complementary common data lines for serial input/output. The output terminals of the main amplifiers MA2 to MA4 are coupled to the input terminals of the corresponding data output buffer sofas DOB2 to DOB4, and the two read data registers RRA and RRB.
is coupled to the input terminal of the corresponding bit. Further, the output terminal of the main amplifier MAL is coupled to the first input terminal of the read data selection circuit RDS, and also coupled to the first bit input terminals of the two read data registers RRA and RRB.

The read data register RRA is a dual port
In the serial memory mode of the memory, the high level of the timing signal φra supplied from the timing control circuit TC causes the output signals of the main amplifiers MAI to MA4 to be input in parallel to the respective corresponding beams/ The signal is output serially according to the timing signal φrsa. Similarly, in the serial memory mode of the dual boat memory, the read data register RRB converts the output signals of the main amplifiers MAL to MA4 into corresponding bits by the high level of the timing signal φrb supplied from the timing control circuit TC. The timing signal φrs is taken in parallel and supplied from the timing control circuit TC.
Output serially according to b. Output terminals of these read data registers are respectively coupled to second and third input terminals of the read data selection circuit RDS. The read data registers RRA and RRB are in the dual boat memory serial memory mode.
They are brought into operation in a complementary manner alternately every four cycles of the serial clock signal SC.

The read data selection circuit RDS selects the main amplifier MAL and the read data register according to an internal control signal sm supplied from the function control circuit FC and internal selection signals sa and sb formed by a circuit (not shown) in the serial input/output circuit SIO. One of the output signals of RRA and read data register RRB is selected and transmitted to data output buffer DOB1. That is, in each normal operation mode in which the internal control signal Sm is at a low level, the output signal of the main amplifier MAL is directly transmitted to the data output buffer DOB1. In addition, the internal control signal s
In the serial memory mode in which m is at high level, the output signal of read data register RRA or RRB is selected according to internal selection signals sa and Sb, and transmitted to data output buffer DOB1.

The data output buffers DOB1 to DOB4 are activated by the high level of the timing signal φsr supplied from the timing control circuit TC, and read data obtained as an output signal of the read data selection circuit RDS or the main amplifier MAI-MA4. , and output to an external device via serial input/output terminals 5IOI to 5I04.

When the timing signal φsr is at a low level, the outputs of the data output buffers DOBI to DOB4 are placed in a high impedance state. In addition, in the serial memory mode of dual boat memory, the data output buffer D
Only OB1 is in the operating state, and the data output buffer FDO
The outputs of B2 to DOB4 are always in a high impedance state.

On the other hand, serial input/output terminals 5IOI to 5IO4 are coupled to input terminals of corresponding data buffers DIB1 to DIB4. Data manual buffer DIBI and DIB
3. The output terminal of DIB4 is connected to the corresponding write data selection circuits WDSI and WDS3. It is coupled to a first input terminal of WDS4.

Further, the output terminal of the data manual buffer DIB2 is coupled to the first input terminal of the write data selection circuit WDS2, and also to the input terminals of the two write data registers WRA and WRB. The output terminals of the first to fourth bits of the write data register WRA are respectively coupled to the second input terminals of the corresponding write data selection circuits WDSI to WDS4. Similarly, the output terminals of the first to fourth bits of the write data register WRB are the output terminals of the third bits of the corresponding write data selection circuits WDSI to WDS4.
are respectively coupled to the input terminals of . Output terminals of write data selection circuits WDSI-WDS4 are coupled to input terminals of corresponding write amplifiers WAI-WA4, respectively.

Write data registers WRA and WRB receive a timing signal φwsa supplied from a timing control circuit TC.
or alternatively and complementarily activated according to φwsb,
Data manual buffer D from serial input/output terminal 5I02
Serially captures input data supplied via IB2.

The write data selection circuits WDSI to WDS4 select the data manual buffers DIBI to DrB4 according to an internal control signal Sm supplied from the function control circuit FC and internal selection signals sa and Sb formed by a circuit (not shown) in the serial input/output circuit SIO. , write data register W
The output signal of RA or WRB is selected and transmitted to the corresponding write amplifiers WA1 to WA4. That is, in various normal operation modes in which the internal control signal sm is at a low level, write data supplied from the serial input/output terminals 5101 to 5I04 via the data input cover sofas DIRI to DIB4 is transmitted to the write amplifiers WA1 to WA4. do. Furthermore, in the serial memory mode in which the internal control signal sm is at a high level, the internal F! ! The output signal of the write data register WRA or WRB is selected according to the FJ selection signals sa and sb, and the write amplifier WAI
- communicate to WA 4.

Write amplifiers WAI to WA4 are timing control circuits T
It is activated by the high level of the timing signal φsw supplied from C, and the write data supplied via the corresponding write data selection circuits WDSI to WDS4 is used as a complementary write signal, and the corresponding complementary common data line for serial input/output is activated. CD51・CD51~CD54・CD
54. When the timing signal φsw is at a low level, the outputs of the write amplifiers WAI to WA4 are placed in a high impedance state.

FIG. 2 shows a circuit diagram of one embodiment of the data selector DSLI in the dual port memory of FIG. Data selectors DSL2 to DSL4 also have the same circuit configuration as in FIG. 2.

Note that all MOSFETs shown in the figure are of N-channel type.

In FIG. 2, n+1 sets of complementary data lines DO, DO to Dn-Dn constituting the memory array M-ARY1 are connected to data transfer switches MO3FE'T pairs Q1, Q2 to
It is coupled to corresponding unit circuits UDRO-UDRn of data register DRI via Q5 and Q6. Each unit circuit of the data register DRI further includes a data selector DSL.
I corresponding switch MO3FET pair Q7, Q8~Ql
It is selectively connected to complementary common data lines CD51 and CDS1 for serial input/output via I and Q12.

The gates of these switch MOS FET pairs are connected in common, and the corresponding Nantes gate 1-way NA
It is coupled to the output terminals of G7 to NAG9.

One input terminal of these Nantes gate circuits NAG7 to NAG9 is connected to the corresponding Nantes gate circuit NAG1 to NA
G3 is coupled to the output terminal, and the other input terminal is coupled to the output terminals of the corresponding Nant gate circuits NAG4 to NAG6, respectively.

Corresponding data register selection signals SO-Sn are supplied from the pointer PNT to one input terminal of the Nant gate circuits NAG1-NAG3. Nantes gate circuit NAG
The other input terminals of I to NAG3 are all commonly connected,
Timing signal φr is supplied from timing control circuit TC. On the other hand, data register selection signals S1 to Sn and SO of the corresponding data register selection signals are supplied from the pointer PNT to one input terminal of the Nant gate circuits NAG4 to NAG6. Further, the other input terminals of the Nant gate circuits NAG4 to NAG6 are commonly connected, and a timing signal φW is supplied from the timing control circuit TC.

The timing signals φr and φW supplied from the timing control circuit TC are dual-ported, as will be described later.
Complementarily formed in the serial memory mode of the memory. That is, in the serial memory mode of dual port memory, memory arrays M-ARYI to M
-ARY4 is serially input/output via an external terminal for serial data input (serial input/output terminal 5IO2) and an external terminal for serial data output (serial input/output terminal 3101). Therefore, the timing signal φC for shifting the pointer PNT is generated once every four cycles of the serial clock signal SC. Furthermore, the first two cycles of these four cycles are used as write cycles to the data registers DRI to DR4, and the timing signal φW is set to a high level. Similarly, the latter two cycles of the four cycles are used as read cycles from the data registers DRI to DR4, and the timing signal φr is set to high level. The timing signal φC is formed in synchronization with the timing of a change from a write cycle to a read cycle.

The input data supplied in synchronization with the serial clock signal SC is once serially input into write data registers WRA or WRB in 4 bits, and then input into data registers DRI to DR in the subsequent write cycle.
4 is input in parallel. On the other hand, data register DR
The data held in the corresponding bits of I to DR4 are read out simultaneously in 4 bits and stored in the read data register R.
After parallel input to RA, serial clock signal S
It is output serially in the next four cycles of C. Therefore, as described above, when viewed from the pointer PNT's output signal, that is, the data register selection signal, which is shifted at the timing of changing from a write cycle to a read cycle, although it is synchronized with the read address of the data register, , write data register W
The input data held in RA-WRB is shifted by one from the write address input to the data register. Therefore, in the data selectors DSLI to DSL4, in the write cycle in which the timing signal φW is at high level, the pointer PNT The data register selection signals SO to Sn outputted from the registers are shifted and supplied to the switch MO3FET pair corresponding to the previous address, respectively.

That is, in FIG. 2, when the timing signal φW goes high, the output signals of the Nant gate circuits NAG4-NAG6, whose corresponding data register selection signals S1-Sn and SO go high, go low. As a result, the output signals of the Nant's gate circuits NAG7 to NAG9 corresponding to the next address of the data register selection signal become high level, and the switch MO5FET pair Q7, Q8 to Q11, Q corresponding to the Nant's gate circuit becomes high level.
12 is turned on. Therefore, the input data held in the write data register WRA or WRB is input to the data register unit l path corresponding to the address immediately preceding the address designated by the current data register selection signal. In a read cycle in which the timing signal φr is at high level, the pointer PN
According to the high level of the data register selection signals SO to Sn sent from T, the output signals of the corresponding Nantes gate circuits NAG1 to NAG3 become low level, and further the output signals of the corresponding Nantes gate circuits NAG7 to NAG9 become high level. Become. Therefore, the address of the data register unit circuit output to the read data register RRA or RRB is the same as the address specified by the data register selection signal.

FIG. 5 is a block diagram of an embodiment in which a plurality of dual boat memories of this embodiment are connected in series to configure a large-capacity serial memory to which logically consecutive addresses are assigned. It is shown.

As mentioned above, three dual boat memo IJME
MI to MEMs are all set to serial memory mode by setting their operation codes to a predetermined combination, and their serial input/output terminal 3101 is an external terminal for serial data output, and their serial input/output terminal 5102
is dedicated as an external terminal for serial data input.

Therefore, the serial input data Sin supplied from the memory drive device is first input to the serial input/output terminal 5I02 of the leading dual boat memory MEMI. Serial input/output terminal 5IOI of dual boat memory MEM1 is coupled to serial input/output terminal 5I02 of dual boat memory MEM2 to which the next logically consecutive address is assigned. Similarly, dual boat memory MEM2 serial input/output connector 5
lot is coupled to the serial input/output terminal 5I02 of the dual boat memory MEM3, and the serial input/output terminal S02 of the dual boat memory MEMs is coupled to the serial input/output terminal 5101 of the dual boat memory MEMs-1. be done. The output signal of the serial input/output terminal 5101 of the dual boat memory MEMs at the end is the serial output signal 5out of the serial memory configured by these dual boat memories.
Output to the memory drive device.

External terminals RAS, CAS, WE, DT10E of dual boat memories MEM1 to MEMS.

The SOE and SC receive a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal W from the memory driver.

A data transfer control signal DT10E, a serial output control signal 70,001, and a serial clock signal SC are commonly supplied. Also, dual port memo 'JMEMI~M
The external terminal AO-'=Ai of E M s has X address signals AXO to AXi and Y address signals AYO to AY.
i are commonly supplied by the address multi-break method.

FIG. 4 shows a serial data write cycle for inputting write data serially supplied from an external memory drive device to data registers DRI to DR4 in the serial memory mode of the dual port memory of this embodiment. A timing diagram for one embodiment is shown.

In FIG. 4, the dual port memory is activated by the fall of a row address strobe signal RAS supplied as a control signal from the outside from a high level to a low level. Prior to the fall of the row address strobe signal RAS, the write enable signal WE and the data transfer control signal DT10E are set to low level, and the column address strobe signal CAS and serial output control signal SOE are set to high level. Also, external terminal A
O to Ai contain the row address r of the word line to which write data input to data registers DRI to DR4 in the previous serial data write cycle should be transferred.
is input. The internal control signal sm that specifies the serial memory mode of the dual port memory is generated by inputting a predetermined operation code to the function control circuit FC in the operation mode setting cycle executed before startup.
It is already considered to be at a high level.

Next, a little later than the fall of the row address strobe signal RAS, the column address strobe signal CAS is changed from the high level to the low level. Furthermore, prior to the fall of the column address strobe signal CAS, the leading column address C of the data registers DRI to DR4 to which write data should first be input is input to the external terminals AO to At.

Furthermore, at the timing when the selection operation of the dual port memory is completed, the row address strobe control signal DT1
0E is returned to high level, and the serial clock signal SC
is input, and this serial clock signal SC
Serial input data Sin is input to the serial input/output terminal 5I02 in synchronization with the falling edge of .

In the dual port memory, at the falling edge of the row address strobe signal RAS, the column address strobe signal CAS and the serial output control signal SOE are at high level and the write OE is at low level, so it is a serial data write cycle. is identified. Further, a timing signal φar is generated in synchronization with the fall of the row address strobe signal RAS, the row address r is taken into the row address buffer RADB, and a word line selection operation is started.

Furthermore, at the time when this word line selection operation is completed, a timing signal φdt is generated, and the write data input in the previous serial data write cycle is input in parallel to the word line specified by the row address r.

Next, timing signal φac is generated in synchronization with the fall of column address strobe signal CAS, column address C is taken into column address buffer CADH, and a logic "1" signal is written to the corresponding bit of pointer PNT. .

Further, the timing signals φr and φW for controlling the selection operation of the data selectors DSLI-DSL4 are set as a read cycle by setting the timing signal φr to high level from the beginning of this serial data write cycle, and are specified by the pointer PNT. The focus of the data registers DRI to DR4 is selected as is. By writing a logic “1” signal to the corresponding bit of pointer PNT, data registers DR1 to
The bit corresponding to column address C of DR4 is connected to complementary common data lines CD5I to CD54 for serial input/output. A timing signal φra is first formed at the time when the data held in the data register corresponding to each serial input/output complementary common data line is established, and these data are input to the corresponding bits of the read data register RRA.

Row address strobe signal RAS, column address.

The dress strobe signal CAS etc. are returned to high level,
By inputting the serial clock signal SC,
Serial input data Sin supplied to serial input/output terminal 5IOI is first input to write data register WRB. That is, a timing signal φwsb for four cycles is generated in synchronization with the serial clock signal SC, and serial input data Sin is strobed at the rising edge of the timing signal φwsb, and is sequentially inputted to the write data register WRB while being shifted. On the other hand, the internal selection signal sa is set to high level and the timing signal φrsa for four cycles is formed in synchronization with the serial clock signal SC, so that the read data of the data registers DR1 to DR4 held in the read data register RRA is but,
Data output buffer DOBI and serial input/output terminal 5
It is output via the IOI to the dual port memory where the next logically consecutive address is assigned.

In addition, in the serial data write cycle of the dual port memory that constitutes the serial memory, these read data initially output to the serial input/output terminal are essentially useless data, but the dual port memory Storage capacity 4x per 10 addresses (
n+1) bits and 7,14x (n+1)+1 and subsequent input data are input to the serial input/output terminal 5IO2, the input data after data d1 input at the beginning of this serial data write cycle are sequentially input. Output. That is, input data exceeding the storage capacity of the dual port memory is output as if it were pushed out by the shift register consisting of data registers DRI-DR4.

At an intermediate point in time when the first 4 bits of data are input/output, the first timing signal φC is formed in synchronization with the serial clock signal SC, and the logic “1” signal held in the pointer PNT is 1 bit. Shift by minute. As described above, regarding the timing signals φr and φW for switching the selection operations of the data selectors DSLI to DSL4, the timing signal φr is initially set to a high level, and when the first four cycles are completed, the timing signal φr becomes a low level. , the timing signal φW becomes high level.

In the next cycle of the serial clock signal SC in which the timing signal φC is generated, the timing signal φrb is generated, and the data held in the data registers DRI to DR4 corresponding to the row address (+1) is input to the read data register RRB. At this time, since the timing signal φr is still at high level, the data selector DSL
In I-DSL4, the C+1th bit of the data registers DRI-DR4 is selected in direct response to the data register selection signal Sc+1 supplied from the pointer PNT. In addition, C+ of these data registers DR1 to DR4
The read data of the first bit is output from the serial input/output terminal 5101 in the next four cycles.

When the first four cycles are completed, the internal selection signal sa becomes low level and the internal selection signal sb becomes f level in synchronization with the fall of the serial clock signal SC. Also, almost at the same time, the timing signal φr becomes low level, the timing signal φW becomes high level, and the data selectors DSLI to DSL4 enter a write cycle. In the serial input/output circuit SIO, timing/No. 3 φrsb and φwsa are formed for 4 cycles each, and input data supplied via the serial input/output terminal 5I02 is serially input to the write data register WRA. The read data of the data registers DRI to DR4 inputted to the read data register RRB in the previous four cycles is serially outputted via the serial input/output terminal 5roi. In synchronization with the 1st bit of the timing signal φ-sa, the timing signal φS control is generated, and the input data input to the write data large register WRB in the previous four cycles is sent to the write data selection circuits WDSI to WDS4 and the write amplifier. The signals are input to data registers DRI to DR4 via WA 1 to WA 4 and complementary common data lines for serial input/output CD5I to CD54. At this time, since the timing signal φW is at a high level, the data selectors DSLI to DSL4 are in a write cycle. Therefore, although pointer PNT specifies column address c+l, these input data are input to the bits corresponding to column address C of data registers DRI to DR4, respectively.

That is, in each of the four cycles of the serial clock signal SC, the input data that is serially input is serially input to the write data registers WRA and WRB alternately, and in the next four cycles of the serial clock signal SC, the input data that is input serially is serially input to the write data registers WRA and WRB. It is input to the corresponding bit of DR4. Also, the serial clock signal S
The data in the data registers DRI-DR4 to be output in each of the four cycles of C is read out to the read data register RRA or RRB in the four cycles before the serial clock signal SCO. Therefore, in the data selectors DSLI to DSL4, in a write cycle in which the input data held in the write data register WRA or WRB is input to the data registers DRI to DR4, the data register selection signal supplied from the pointer PN'l' SO to Sn are shifted as the previous data register selection signal.

Hereinafter, the same operation is repeated every four cycles of the serial clock signal SC, and the same operation is repeated in the dual boat memory and subsequent dual boat memories to which the next logically consecutive address is assigned. An action is taken.

Thereby, the data registers DRI to DR4 of the three dual port memories connected in series function as if they were shift registers connected in series. That is, these S dual boat memories connected in series have a storage capacity of 4 for each 10 address of the dual boat memories.
S dual ports connected in series with zero or more operations can act as a serial memory with a storage capacity of 5x4x (n+1) bits per 10 addresses, where X(n+1) bits. By putting these dual boat memories into write data transfer mode all at once, the serial input data pushed into the memory in sequence is coupled to the specified word line in the write data transfer cycle in a total of 5X4X.
The data is input to (n+1) bits of memory cells all at once.

The serial data write cycle operation of the dual port memory shown in FIG. 4 can be directly contrasted with the read data transfer cycle operation. In other words, the 5 signal connected to the word line of the row address specified at the falling edge of the row address strobe signal RAS.
The read data output from the X4X (n+1) memory cells is transferred to the corresponding data register DRI according to the timing signal φdt generated by returning the data transfer control signal DT10E to high level.
~Input to DR4. Thereafter, in synchronization with the timing signal φC, 4 bits each are read out from the data register RRA.
or RR] 3, and is output serially in response to 4s/f of the serial clock signal SC. Further, these output data are input as serial input data Sin of the dual port memory to which the next logically consecutive address is assigned. In such a read data transfer cycle, the data output to the serial input/output terminal 5101 of the dual port memory connected at the end as a serial memory becomes meaningful data from the first bit.

As described above, the dual boat memory of this embodiment reads the data held in the bit before inputting the input data supplied via the serial input terminal to the corresponding bit of the data register. It has the function of outputting to the outside via the serial output terminal, and in order to realize these functions, it holds input data and output data read from the data register until it is input/output in synchronization with the serial clock signal. Multiple sets of registers are provided for the purpose of Therefore, by cascading multiple dual boat memories, the data registers of those dual boat memories can function as shift registers, and any storage capacity can be achieved without the need for external components. It is possible to realize a serial memory with

As shown in the above-described embodiment, when the present invention is applied to a semiconductor storage device such as a dual port memory used as an image processing memory, the following effects can be obtained. That is, (1) Before inputting the input data that is input from the external terminal for serial data input in synchronization with the serial clock signal to the corresponding bit of the data register, read the data held in that bit until then and output the serial data. By outputting to the external terminal for serial data output, logically consecutive addresses are assigned by connecting multiple semiconductor memory devices in series, and the next logically consecutive address is assigned to the external terminal for serial data output. By coupling to an external terminal for serial data input of a semiconductor memory device, an effect can be obtained in that a plurality of data registers of a plurality of semiconductor memory devices can be operated as a continuous shift register with a large bit length.

(2) In item (1) above, the input data input serially and the output data read from the data register are held until these data are input/output in synchronization with the serial clock signal. Therefore, by providing two sets of registers, it is possible to synchronize the serial input/output operations of a plurality of semiconductor memory devices connected in series with the serial clock signal.

(3) According to items (1) and (2) above, multiple semiconductor storage devices having serial input/output functions can be cascade-connected without providing any external components other than the chip of the semiconductor storage device; This provides the advantage of being able to configure a serial memory with a storage capacity that suits the purpose.

(4) Items (1) to (3) above provide the effect that it is possible to realize a serial memory with simplified control, lower cost, and increased capacity.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and may be modified in various ways without departing from the gist thereof. For example, the serial input/output circuit S! of FIG. 0 is serial input/output terminal 5roi
and 5r02 may be used as external terminals for serial data output, and serial input/output terminals 5IO3 and 5104 may be used as external terminals for serial data input, or external terminals exclusively for serial input/output may be provided from the beginning. Also, read data register RRA
, RRB and write data registers WRA and WRB may be ordinary registers, and a counter circuit, a decoder, and a data multiplexer may be added to provide the same function as a shift register. Nant gate circuit NA provided in
The selection circuit consisting of 01 to N8G9 has a pointer PNT (
! ! Memory arrays M-ARY1 to M-A may be provided in memory arrays M-ARY1 to M-A, which may be provided in memory arrays J and shared by data selectors DSLI to DSL4, and which constitute random access board I in FIG.
RY4 may have a static type RA PJ as its basic configuration.

Furthermore, the dual boat memory shown in FIG.
Various embodiments can be adopted for the block configuration and combinations of control signals, such as a column address counter circuit and a column address decoder that can be initialized by O to AYE.

The above explanation mainly describes the invention made by the present inventor in the field of application, which is the dual boat
Although we have explained the case where it applies to memory, it is not limited to that, and for example, it can be applied to other multi-board
It can also be used in various semiconductor storage devices such as memory. The present invention is applicable to semiconductor memory devices having a small number of data registers and serial/parallel conversion circuits using the data registers.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, before inputting the input data that is input from the external terminal for serial data input in synchronization with the serial clock signal to the corresponding bit of the data register, the data held in that bit up to that point is read out and the serial data is output. By outputting to the external terminal for serial data output, logically consecutive addresses are assigned by connecting multiple semiconductor memory devices in series, and the next logically consecutive address is assigned to the external terminal for serial data output. By coupling to the external terminal for serial data input of a semiconductor memory device, multiple data registers of multiple semiconductor memory devices can be operated as a continuous shift register with a large focus length, and it is possible to , it is possible to relatively easily realize a serial memory with a storage capacity suitable for the purpose without installing any external parts.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of a serial input/output circuit of a dual boat memory to which the present invention is applied. FIG. 2 is a data selector of a dual boat memory to which the present invention is applicable. FIG. 3 is a block diagram showing an example of a dual port memory including the serial input/output circuit and data selector of FIGS. 1 and 2; FIG. 4 is a circuit diagram showing an example of the dual port memory; A timing diagram showing an example of a serial data write cycle when dual boat memories to which this invention is applied are connected in cascade. FIG. FIG. 2 is a connection diagram showing an example of a serial memory configured by. Si2...Serial input/output circuit, MAL~MA4...
・Main amplifier, WA1 to WA4... U, light amplifier, RRA, RRB... Read data register, WR
A, WRB...Write data register, RDS...
・Read data selection circuit, WDSI to WDS4...
Write data selection circuit, DIBI~1) IB4...
Data input buffer, DOB1 to DOB4...Data output buffer, DRI...Data register, DSL1...Data selector, M-ARYl...Memory array, PNT...
...boink, TC...timing control circuit, UDR
1~UDRn...Data register unit circuit, Ql-Q
l2...N channel MO3FET, NAGI~NA
G9...Nant gate circuit. SAI... sense amplifier, C3WI... column switch, RCD... column address decoder for random access boat, SCD... column address decoder for serial access boat, RD... row address decoder, RIO...Random input/output circuit, F
C...Function control circuit, CADB...Column address buffer, RADB...Row address buffer, AM
X: Address multiplexer, REFC: Refresh address counter. MEML~FAEMs...Dual Boat
memory. Figure 2 T (SIOIL Figure 3 Figure 4 (L l tl”l J (C+ll
(C+3) Figure 5

Claims (1)

[Claims] 1. A data register in which each bit corresponds to a plurality of data lines constituting a memory array, and input data serially supplied via an external terminal for inputting serial data to the above data. Serial-parallel mode in which read data is input sequentially to the register and input in parallel to the data register from multiple memory cells coupled to the selected word line, and is serially output to an external device via an external serial output terminal. The conversion circuit and the serial/parallel conversion circuit convert the input data that has been previously held in the corresponding bits of the data register before sequentially inputting the input data serially input from the external terminal for serial data input to the corresponding bits of the data register. 1. A semiconductor memory device comprising a signal path for sequentially outputting data from an external serial data output terminal. 2. The signal path is connected until the input data input in synchronization with the serial clock signal via the external terminal for serial data input is input to the corresponding bit of the data register in the next cycle of the serial clock signal. an input data holding circuit for holding the input data during the previous cycle of the serial clock signal; and an input data holding circuit for holding the data in the corresponding bit of the data register in the previous cycle of the serial clock signal. 2. The semiconductor memory device according to claim 1, further comprising an output data holding circuit for holding serial data until it is output from an external terminal for outputting serial data. 3. The signal path selects a corresponding bit of the data register in each cycle of the serial clock, outputs the data held in that bit until then to the output data holding circuit, and outputs the data held by the bit to the output data holding circuit, and The method of the present invention includes a selection circuit for selecting the bit immediately before the corresponding bit of the data register in each cycle of the data register, and inputting the input data held in the input data holding circuit. A semiconductor memory device according to scope 1 or 2. 4. The external terminal for serial data output is sequentially connected to the external terminal for input of serial data of a similar semiconductor memory device that is connected in series to constitute a serial memory and is assigned logically consecutive addresses. A semiconductor memory device according to claim 1, 2, or 3, characterized in that the semiconductor memory device is 5. The external terminal for serial data input and the external terminal for serial data output are usually used as external terminals for inputting and outputting multiple serial data, and when configuring the serial memory, the external terminal for serial input and the serial 5. The semiconductor memory device according to claim 1, 2, 3, or 4, wherein the semiconductor memory device is dedicated as an external output terminal.