JPS63225994A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of external terminals, by inputting/outputting an effective signal to the external terminal at a time when a prescribed time elapses after inverting the logic level of the external terminal once. CONSTITUTION:In a semiconductor memory device, an input data which becomes a write data, after whose logic level being inverted, is supplied to a data input/ output terminal DIO at the time when the prescribed time elapses. Therefore, the fact that the logic levels of complementary input data signals di and the inverse of di are inverted is detected at an input data detection circuit DTD, and after the prescribed time elapse following the formation of the output signal dtd of the circuit, a write timing signal phiwa is formed, and a write amplifier is set at an operating state. A timing control circuit TC outputs a various kinds of signal to every circuit based on a chip enable signal, the inverse of CE from the outside, a write enable signal, the inverse of WE, an address signal change detecting signal atd from an ATD, an input data change detecting signal dtd from the DTD, and a completion address detecting signal (ea) from an AC.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective when applied to, for example, a semiconductor memory device having a serial input/output function for stored data. It is something.

[Conventional technology]

There are semiconductor storage devices, such as dual port memories, that have the function of serially inputting and outputting stored data. In this dual port memory, the row address of the word line to be selected and the first column address at which the serial input/output operation should be started are supplied from external terminals for address input.

Further, a serial clock signal for synchronizing serial input/output operations of storage data is supplied from an external terminal for clock input.

Dual boat memory is described, for example, on pages 243 to 264 of Nikkei Electronics, published by Nikkei McGraw-Hill, March 24, 1986.

[Problem that the invention seeks to solve]

The conventional semiconductor integrated circuit device including the dual boat memory described above has a plurality of external terminals to which predetermined signals are input/output, and among these external terminals, the required number of address input external terminals is This is increasing as semiconductor integrated circuit devices become more highly integrated and have larger capacities, and in some cases may become a bottleneck in device implementation. In addition, for example, in a simple system that requires a large storage capacity but can satisfy the specifications by using a low-speed, low-function semiconductor integrated circuit device, increasing the number of external terminals can reduce the cost of the system. This is a factor that hinders

An object of the present invention is to provide a semiconductor integrated circuit device in which the number of external terminals is reduced.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
After the logic level of the external terminal is once inverted, a valid signal is input/output to the external terminal at the time when a predetermined period of time has elapsed.

[For production]

According to the above means, there is a signal change detection circuit that detects that the logic level has been inverted, and a timing control circuit that forms a timing signal for signal reception when a predetermined time has elapsed after the logic level has been inverted. By providing a register or the like that sequentially captures and holds signals according to this timing signal, it is possible to transmit multiple signals continuously in chronological order through one external terminal. It is possible to reduce the number of terminals and lower the cost of the system.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a semiconductor memory device to which the present invention is applied. Circuit elements constituting each circuit block in the figure are formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Although the semiconductor memory device of this example is not particularly limited,
The start address and end address each have the function of serially inputting and outputting stored data to and from multiple memory cells specified by the start address and end address. Through two address input external terminals AD,
The data is serially input to this semiconductor memory device. Further, a plurality of input/output storage data are similarly input serially to this semiconductor memory device via one data input/output external terminal DIO. As described later, these address signals and input/output data are supplied to each external terminal after a predetermined period of time after inverting the logic level of each external terminal, so input/output operations can be synchronized. No serial clock signal is required to read the data.

Therefore, the semiconductor memory device of this embodiment is provided with an address signal change detection circuit ATD and an input data change detection circuit DTD that identify when the logic levels of the address signal and input data are inverted. An address shift register ASR is provided that sequentially takes in address signals every time a predetermined time elapses. Also, an address counter AC is initialized by the start address taken into the address shift register ASR and is incremented each time the input/output operation of each stored data is completed.
An address comparison circuit AC is provided which compares TR, an end address register EAR that holds an end address, and the end address with the count value of an address counter ACTH to form an end address detection signal ea.

This semiconductor memory device also has a chip enable signal CE and a write enable signal WE as control signals.
External terminals CE and WE are provided, and external terminals VCC and GND are provided for supplying a power supply voltage and a ground potential. In other words, although this semiconductor memory device has a relatively large storage capacity and is highly functional, it is provided with only six external terminals in total.

In FIG. 1, the memory array M-ARY includes m+1 word lines arranged vertically in the figure, n+1 sets of complementary data lines arranged horizontally, and the combinations of these word lines and complementary data lines. (m+1)X (
(n+1) static type memory cells.

n+1 arranged in the same row of memory array M-ARY
The selection terminals of the memory cells are coupled to the corresponding word line. These word lines are connected to the row address decoder R
It is coupled to the DCH, and one of them is selectively selected.

Row address decoder RDCR is selectively activated in accordance with timing signal φX supplied from timing control circuit TC. In its operating state, row address decoder RDCR receives complementary internal address signals axQ to axi supplied from address counter ACTR.
(Here, for example, the non-inverted internal address signal axQ and the inverted internal address signal axQ are expressed together as a complementary internal address signal 1xO, the same applies hereinafter), and one corresponding word line is alternatively set to high. The level is selected.

On the other hand, the input/output terminals of the m+1 il& memory cells arranged in the - column of the memory array M-ARY are coupled to the corresponding complementary data lines. These complementary data lines are further connected to corresponding switches MO of column switch C3W.
It is selectively coupled to complementary common data lines CD-6 via 3FETs.

The column switch C3W is composed of n+1 pairs of switches MO3FET provided corresponding to the complementary data lines, respectively. These switch MO3FETs each have one terminal coupled to a corresponding complementary data line,
Non-inverting signal line CD whose other terminal is a complementary common data line
Or they are commonly connected to each stone with an inverted signal line. The gates of each pair of switch MOS FETs are commonly connected, and each is supplied with a corresponding data line selection signal from a column address decoder CDCR. The column switch C3W selectively couples the corresponding complementary data line to the complementary common data line CD-τ when the data line selection signal is alternatively set to a high level.

Column address decoder CDCR is selectively activated according to timing signal φy supplied from timing control circuit TC. Column address decoder CDC
In its operating state, R is the address counter ACT
Complementary internal address signals ayO to ayj supplied from R
is decoded, and the corresponding data line selection signal is alternatively set to high level. These data line selection signals are supplied to the corresponding switch MO3FET of the column switch C3W.

Address counter ACTR is constituted by a k+l bit binary counter circuit. This address counter ACTR is supplied with an initial setting timing signal φcs and a sidewalk timing signal φac from the timing control circuit TC, and is supplied with a +ll bit address signal ao-yak from the address shift register ASR.

Of these, the timing signal φCS is normally set to a low level, and is temporarily set to a high level when serial input of a start address is completed. In addition, the timing signal φac
Similarly, it is normally set to a low level, and is temporarily set to a high level each time the input/output operation of each bit of stored data is completed. That is, in this semiconductor memory device, as described above, the address input external terminal A has one start address and one end address for performing serial input/output operations of storage data.
It is input serially via D. These address signals are sequentially taken into the address shift register ASR one bit at a time via the address buffer AIB and held there. When the start address is taken in and the timing signal φcs is temporarily set to high level, the start address is transferred from the address shift register ASR to the address counter ACTR as an address signal aQxak, and is set as the initial count value. Furthermore, after all address signals have been captured and serial input/output operations of stored data have started, the timing signal φac is temporarily set to a high level each time input/output operations for each bit of stored data are completed. As a result, the address counter ACTR is incremented by l addresses.

The output signal of the address counter ACTR is not particularly limited, but its upper i+1 bits are sent to the row address decoder RD as the complementary internal address signal axQ-maxi.
CH, and its lower j+1 pins are supplied to the column address decoder CDCR as the complementary internal address signals ayO-ayj. Furthermore, these complementary internal address signals axO to xi and yO to yj are
It is supplied to one input terminal of the address comparison circuit AC.

Note that after the start address is transferred to the address counter ACTR, the end address taken into the address shift register ASR is transferred to the end address register EAR in accordance with the timing signal φrs.

The end address register EAR is constituted by a launch of k+l bits. This end address register EAR
, a timing signal φr is sent from the timing control circuit TC.
s is supplied, and an address signal aOyak is also supplied from the address shift register ASR. The timing signal φrs is normally set to a low level, and is temporarily set to a high level when the serial input operation of the end address by the address shift register ASR is completed. By temporarily setting the timing signal φrs to a high level, the end address taken into the address shift register ASR is transferred as an address signal aO-ak to the end address register EAR and held there. These end addresses are made into complementary internal address signals and are supplied to the other input terminal of address comparison circuit AC.

The address comparison circuit AC is connected to the address counter ACT.
The output signal of R and the end address signal held in the end address register EAR are compared for each pill. When all bits of these address signals match, the address comparison circuit AC sets its output signal, that is, the end address detection signal 6a, to a high level. This end address detection signal ea is sent to the timing control circuit TC.

The address shift register ASR is constituted by a shift register consisting of a k+1 bit master/slave flip-flop. This address shift register ASR is supplied with a timing signal φas for shifting from a timing control circuit TC, and is also supplied with a complementary input address signal ad-7 from an address input buffer AIB.

Of these, the timing signal φa3 is normally at a low level, and when the address signal change detection circuit ATD detects that the logic level of the address input external terminal, that is, the complementary internal address signal ad-ad is inverted, the output signal, that is, the address signal changes. When the detection signal atd is set to high level, it is temporarily set to high level. The complementary input address signal ad-ad is formed by the address manual buffer AIB based on the address signal supplied to the address input external terminal AD.

Address shift register ASR receives timing signal φa
According to s, input address signals supplied as complementary input address signals ad·Ti are taken in and sequentially shifted. When the start address or end address has been fetched and the address shift register ASR is full, the timing control circuit TC temporarily sets the timing signal φcs or φr3 to a high level, and the address signal aO
-ak to the address counter ACTR or end address register EAR.

The address manual buffer AIB uses the address signal serially supplied via the address input external terminal AD as a complementary input address signal ad-ad, and the address shift register ASR and the address signal change detection circuit ATD
supply to.

Although not particularly limited, the address signal change detection circuit ATD is configured by two sets of signal change detection circuits. One of the signal change detection circuits temporarily generates a high-level output signal when the complementary input address signal ad-ad changes from logic "0" to logic "1". The other signal change detection circuit also receives a complementary input address signal a.
When d-ad is changed from logic "1" to logic "O", it temporarily forms a high level output signal. These output signals pass through an OR circuit and are made into an output signal of the address signal change detection circuit ATD, that is, an address signal change detection signal atd. This address signal change detection signal atd
is supplied to the timing control circuit TC and used to form the timing signal φa3.

By the way, the complementary common data 1JIcD-co to which the complementary data lines are selectively coupled in sequence is coupled to the input terminal of the read amplifier RA and to the output terminal of the write amplifier WA. The output terminal of read amplifier RA is further coupled to the input terminal of data output buffer 7DOB, and the output terminal of data output buffer DOB is coupled to data input/output terminal DIO. Further, the input terminal of the write amplifier WA is coupled to the output terminal of the data manual buffer DIB,
The input terminals of the data manual buffer DIB are commonly coupled to the data input/output terminal DIO. The output terminal of this data manual buffer DIB is further coupled to the input terminal of an input data change detection circuit DTD.

In the read operation mode of this semiconductor memory device, read amplifier RA is selectively brought into operation according to timing signal φra supplied from timing control circuit TC. In this operating state, read amplifier RA:
Complementary common data line CD-C from the selected memory cell
Further amplify the read signal transmitted via D.

The output signal of read amplifier RA is sent to data output cover sofa D.
It is transmitted to OB.

In the read operation mode of this semiconductor memory device, the data output sofa DOB operates as a timing control circuit 'rC.
The device is selectively put into an operating state by the high level of the timing signal φoe supplied from the device.

In this operating state, the data output buffer DOB:
Read data transmitted from read amplifier RA is serially output from data input/output terminal 010. At this time, the data output cover sofa DOB inverts the logic level of the data input/output terminal L) 10 before outputting valid read data, and transmits the valid read data after a predetermined time has elapsed. Thereby, serial output operation of read data is realized without requiring a serial clock signal. When the timing signal φoe is set to a low level, the output of the data output buffer 1 is set to a high impedance state.

On the other hand, the data input cover 7 buffer DIB receives write data serially supplied via the data input/output terminal DIO, and supplies complementary input data (B di and di to the write amplifier WA and the input data change detection Transfer to circuit DTD.

Write amplifier WA is selectively brought into operation according to timing signal φ-a supplied from timing control circuit TC in the write operation mode of this semiconductor memory device. In this operating state, the write amplifier WA forms a complementary write signal according to the complementary data signal di-di- supplied from the data manual buffer DIB,
Output to complementary common data line CD-CD. When the timing signal φwa is set to low level, the write amplifier WA
The output of is in a high impedance state.

The input data change detection circuit DTD is composed of two sets of signal change detection circuits, similarly to the address signal change detection circuit ATD. One of these signal change detection circuits temporarily forms a high-level output signal when the complementary input data signal di-di changes from logic "0" to logic "1". The signal change detection circuit changes the complementary input data signals d1 and di from logic "1" to logic '0'.
", a high-level output signal is temporarily formed. These output signals are passed through an OR circuit and are used as the output signal of this input data change detection circuit DTD, that is, the input data change detection signal did. This input data change detection signal dLd is supplied to the timing control circuit TC and is used to form a timing signal φ-a that selectively puts the write amplifier WA into an operating state.

That is, in the semiconductor memory device of this embodiment, input data to be written data is supplied to the data input/output terminal DIO after a predetermined time has elapsed after the logic level is inverted, similar to the address signal described above. . Therefore, in this semiconductor memory device, the input data change detection circuit DTD detects that the logic level of the complementary input data signal di-di is inverted, and when a predetermined time has elapsed since the output signal dtd was formed. Later, a write timing signal φ-a is generated, and the write amplifier WA is brought into operation.

The timing control circuit TC receives a chip enable signal CE and a write enable signal WE supplied as control signals from the outside, an address signal change detection signal atd supplied from an address signal change detection circuit ATD, and an input data change detection circuit DTD. The various timing signals described above are formed based on the input data change detection signal dtd and the end address detection signal ea supplied from the address comparison circuit AC, and are supplied to each circuit. The evening timing control circuit TC includes a counter circuit for counting the address signal change detection signal atd and forming the timing signals φcs and φra.

FIG. 2 shows a timing diagram of an embodiment of the serial write operation mode in the semiconductor memory device of this embodiment. The figure exemplarily shows the operation when two serially input write data D1 to Dp are written in chronological order to addresses p(lli) from the start address Sa to the end address ea. The serial read operation mode of the semiconductor memory device is performed in almost the same procedure as the serial write operation mode.The outline of the serial write operation mode of the semiconductor memory device of this embodiment will be explained with reference to the figure.

As mentioned above, the address input external terminal AD and data input/output terminal DIO of the semiconductor memory device of this embodiment include:
A valid address signal or input data is supplied after a predetermined time has elapsed after the logic level is once inverted. That is, as exemplarily shown in FIG. 2, in this semiconductor memory device, after it is detected that the logic level of the address input external terminal AD is inverted and the address signal change detection fs number atd is formed, a predetermined signal is detected. By setting the timing signal φas to a high level when time T1 has elapsed, the effective 1-1 bit start address signals SAO to S
Ak and end-7 address signals EAO to EAk are sequentially taken into the address shift register ASR, and similarly,
When a predetermined time T2 has elapsed since it was detected that the logic level of the data input/output terminal DIO was inverted and the input data change detection signal dtd was generated, the coupling signal φ
By setting @a to high level, valid p+l bit write data D1 to D p @, Ik! Write to the next selected memory cell.

In FIG. 2, this semiconductor memory device is brought into a selected state and activated by changing the chimble enable f# signal τ1° supplied as a control signal from a high level to a low level. Prior to the fall of the chip enable signal σπ, the write enable signal “WE” is set to a low level, and the address input external terminal AD and the data input/output terminal DrO are released from the high impedance state. At this time, the address input external terminal AD and the data input/output terminal DIO can be set to any logic level.

By changing the chip enable signal CE from a high level to a low level, the address signal change detection circuit ATD is put into an operating state in the semiconductor memory device. By inverting the logic level of the address input external terminal AD, the output signal of the address signal change detection circuit ATD, that is, the address signal change detection signal atd, is temporarily set to high level, and a predetermined value is set to this address signal change detection signal atd. time T
After a delay of l, the timing signal φas is temporarily set to high level. As a result, address input external terminal A
The first focus SAO of the start address signal supplied to D is taken into the address shift register ASR. Also,
At the same time, a counter circuit (not shown) of the timing control circuit TC is incremented.

Thereafter, when the logic level of the address input external terminal AD is inverted and a predetermined time T1 has elapsed, valid start address signals SAI to SAk are sequentially supplied to the address input external terminal AD and sequentially taken into the address shift register ASR. It will be done. At the same time, a counter circuit (not shown) of the timing control circuit TC is incremented. The start address signal SAk of the final focus is taken into the address shift register ASR, and when the count value of a counter circuit (not shown) of the timing control circuit TC reaches +l, the timing signal φCS is temporarily set to a high level. As a result, the +ll bit start address signals SAO to SAk taken into the address shift register ASR are transferred to the address counter ACTR as a counting initial value, and the output number fa of the address counter ACTR becomes the start address sa.

Next, end address signals EAO to EAk are serially supplied to the address input external terminal AD in a similar manner and are sequentially taken into the address shift register ASR. When the end address signal EAk of the final bit is taken into the address shift register ASH, and the count value of a counter circuit (not shown) of the timing control circuit TC reaches +1, the timing signal φrs is temporarily set to a high level. As a result, the end address signals EAO to EAk of the +ll pits taken into the address shift register ASR are transferred to the end address register EAR.

The timing signal φrs is temporarily set to high level and the end address signals EAO to EAk are sent to the end address register E.
By being taken into the AR, this semiconductor memory device completes the input operation of the address signal. Further, the semiconductor memory device starts a selection operation of memory cells of the memory array M-ARY in order to prepare for a write operation. That is, in the semiconductor memory device, the timing signal φX is set to a high level by the falling edge of the timing signal φrs, and the timing signal φy is set to a high level a little later. The row address decoder RDcH receives the complementary internal address signal xQ- from the upper bits of the start address 3a.
Exi and column address decoder C
The lower bits of the start address 3a are supplied to the DCR as a complementary internal address signal yO-a-yJ.

By setting the timing signal φX to high level, the row address decoder RDCR outputs the complementary internal address signal ax.
One word line designated by Oxaxi is set to a high level selected state. As a result, the n+1 memory cells coupled to the designated word line are coupled to the corresponding complementary data lines. When the timing signal φy is set to high level with a slight delay from the timing signal φX, the column address decoder CDCR generates a data line selection signal for selecting a set of complementary data lines specified by the complementary internal address signals ayO to ayJ. is alternatively set to a high level. As a result, one memory cell corresponding to the start address sa is connected to the complementary common data line CD-τ
It is connected to the rat/ato amplifier WA via a stone. In this state, the semiconductor memory device waits for write data to be input to the data input/output terminal DIO.

When the serial input of the expected data is started and the logic level of the data input/output terminal DIO is inverted, the input data changes. 3 I) The output signal of TD, that is, the input data change detection signal dtd, is temporarily set to a high level. Further, when a predetermined time T2 has elapsed since the input data change detection signal dtd was set to high level, the timing signal φwa is temporarily set to high level. As a result, the first bit Di of the write data supplied to the data input/output terminal DIO is taken into the write amplifier WA, and further transferred to the selected memory cell, that is, the start address 3a, via the Aiura common data line CD-CD. written to the corresponding memory cell.

When this write operation is completed and the timing signal φwa is set to a low level, the timing signals φX and φy are set to a low level, and the row address decoder RDCR and column address decoder CDCR are rendered inactive.

As a result, the memory cell corresponding to the start address aa is released. Further, by setting the timing signals φX and φy to low level, the timing signal φac is temporarily set to high level, and the address counter ^CTR is incremented. Furthermore, when the walking operation of the address counter ACTR is completed, the f-ming signal φac is set to a low level, so that the timing signals φX and φy are set to a high level again. As a result, one memory cell corresponding to the address 3a+1 following the start address 3a is selected and connected to the write assive WA via the complementary common data line CD-τ. In this state, the semiconductor memory device waits for the next write data D2 to be supplied to the data input/output terminal DIO.

Thereafter, similar write operations are repeated, and the write data D1 to Dp serially supplied to the data input/output terminal DIO are sequentially selected to write Wt to the p memory cells.
At the same time, the address counter ACTR
is incremented. When the hand value of the address counter ACTR reaches the end address ea, the end address detection signal ea
becomes high level. In this state, when the write operation to the memory cell corresponding to the end address aa is completed, the timing (R signal φac is not formed, and the timing signals 4φX and φy are also not formed. Therefore, the write operation of the semiconductor memory device is completed. The semiconductor memory device enters the reset state after waiting for the chip enable signal CE to return to high level. In this first reset state (here, the address counter ACTR is cleared and the end address detection signal ea is set to low level). Become.

As described above, address signals and input/output data for the semiconductor memory device of this embodiment are made valid after a predetermined time has elapsed after the logic level of the corresponding external terminal is once inverted. Via the external terminal,
Furthermore, serial input/output is performed without requiring a serial clock signal. Therefore, the number of external terminals of this semiconductor memory device is reduced to six, including the power supply voltage supply terminal and the ground potential supply terminal, even though this semiconductor memory device has a relatively large capacity and is highly functional. Ru. Therefore, a system including this semiconductor memory device can be simplified in configuration and reduced in cost.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device having a serial input/output function, the following effects can be obtained. That is, (1) A signal change that detects that the logic level has been inverted by inputting/outputting a valid signal to the external terminal after a predetermined time has elapsed after the logic level of the external terminal has been once inverted. By simply providing a detection circuit and a register, etc. that sequentially captures and holds signals according to a timing control circuit that is formed after a predetermined time has elapsed after the logic level is inverted, multiple bit signals can be transmitted through a single external terminal. The effect of being able to transmit data continuously in chronological order can be obtained.

(2) According to the above item (1), the semiconductor memory device has the effect that it can realize serial input/output operations of signals without requiring a special serial clock signal.

(3) The above items (11 and (2)) have the effect of reducing the number of external terminals of the semiconductor memory device and simplifying its control procedure.

(4) Items (1) to (3) above provide the effect that the configuration of a system including such a semiconductor memory device can be simplified and costs can be reduced.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, the memory array M-ARY of the semiconductor memory device shown in FIG. good. Furthermore, the serial input/output operation of a semiconductor memory device is not performed while incrementing an address counter, but by sequentially specifying a data register in which each bit corresponds to a complementary data line and each bit of this data register. In the embodiment shown in FIG. 1, the address signal and the input/output data are each input/output via one external terminal, which may be performed using a pointer. External terminals may be provided separately, or two or more external terminals may be provided for each, and only the address signal is input using the above method, and a predetermined serial clock signal is used for input/output data. You can also use it as Furthermore, various embodiments may be adopted, such as the block composition ratio of the semiconductor memory device shown in FIG. 1 and the timing conditions of control signals and the like shown in the timing diagram of FIG.

In the above description, the invention made by the present inventor was mainly applied to a semiconductor storage device having a serial input/output function, which is the field of application in which the invention was made, but it is not limited to this, and for example, , system buffers and audio storage devices used in digital communication systems.

The present invention can also be applied to various serial memories used in copying machines, TV printers, etc. The present invention includes a semiconductor integrated circuit device that inputs and outputs at least a multi-bit signal that can be serially transferred, and such a semiconductor integrated circuit device. Can be widely used in digital devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, after once inverting the logic level of the external terminal, a valid signal is input/output to the external terminal after a predetermined period of time has elapsed, thereby generating a special serial clock signal through one external terminal. It is possible to transmit multiple-bit signals continuously in time series without the need for a semiconductor integrated circuit device, which reduces the number of external terminals of a semiconductor integrated circuit device and simplifies its control procedure. The configuration of the system including the device can be simplified and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device to which this embodiment is applied, and FIG. 2 is a timing diagram showing an embodiment of a serial write operation mode in the semiconductor memory device of FIG. 1. be. M-ARY...Memory array, C3W...Column switch, RDCR...Row address decoder, CDC
R...Column address decoder, ACTR...Address counter, EAR...End address register, A
C...address comparison circuit, ASR...address shift register, AIB...address input cover sofa, AT
D...Address signal change detection circuit, RA...Read amplifier, WA...Write amplifier, DOB...Data output cover sofa, DIB...Data manual buffer, DT
D... Input data change detection circuit, TC... Timing control circuit.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device characterized by having an external terminal to which a valid signal is input/output when a predetermined time has elapsed after the logic level is once inverted. 2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of signals are inputted and outputted to and from the external terminal in a time-series manner according to the method described above. 3. The semiconductor integrated circuit device is a semiconductor memory device,
3. The semiconductor integrated circuit device according to claim 1, wherein the signals are address signals and input/output data. 4. The signal receiving section of the semiconductor integrated circuit device includes a signal change detection circuit that detects that the logic level of the external terminal is inverted, and receives an output signal from the signal change detection circuit when the predetermined time has elapsed. Claims 1 and 2 include a timing control circuit that forms a signal reception timing signal at a time, and a register that sequentially receives signals supplied to the external terminal according to the signal reception timing signal. Or the semiconductor integrated circuit device according to item 3.