JPS594068A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS594068A JPS594068A JP57113137A JP11313782A JPS594068A JP S594068 A JPS594068 A JP S594068A JP 57113137 A JP57113137 A JP 57113137A JP 11313782 A JP11313782 A JP 11313782A JP S594068 A JPS594068 A JP S594068A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- voltage
- integrated circuit
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical group [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は集積回路がサイリスク構造を有する場合に生ず
るランチアップ現象を起しにくくするようにした集積回
路に関する
（２）技術の背景
近時、アナログ−デジタル変換回路やデジタル−アナロ
グ変換回路を集積回路化したものが多く作られるように
なってきている。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an integrated circuit that is designed to make the launch-up phenomenon that occurs when the integrated circuit has a silicon risk structure less likely to occur. (2) Background of the Technology Recently, Many analog-to-digital conversion circuits and digital-to-analog conversion circuits are being manufactured as integrated circuits.
このようなアナログ回路ではアナログ回路動作用の二つ
の電源の外に比較用グランド電源等を必要とする。また
、デジタル−アナログ変換回路等では基準電源も必要と
する。このように複数の電源を必要とするアナログ回路
を集積化し、例えば相補型の金属酸化物半導体（以下Ｃ
−ＭＯ３と記す）構成の集積回路を作製した場合には複
数の電源間でサイリスク構造を生じてラフチアツブ現象
が生ずることがあった。Such an analog circuit requires a ground power source for comparison in addition to the two power sources for operating the analog circuit. Furthermore, a reference power source is also required for digital-to-analog conversion circuits and the like. In this way, analog circuits that require multiple power supplies are integrated, for example complementary metal oxide semiconductor (C
-MO3) When an integrated circuit is manufactured, a silicate structure may occur between a plurality of power supplies, resulting in a rough stubble phenomenon.
（３）従来技術と問題点
第１図は従来の（、−ＭＯ３構成の集積回路の一部側断
面図、第２図は第１図の等価回路であり、第１図におい
て１は例えばＮ型のシリコン基板でトランジスタＴｒ＋
はＰチャンネル構造でソースＳとドレインＤ用のＰ＋不
純物ドーピング領域２゜３が作られさらにゲートＧも形
成されている。(3) Prior art and problems Figure 1 is a partial side cross-sectional view of a conventional (,-MO3) integrated circuit, and Figure 2 is an equivalent circuit of Figure 1. In Figure 1, 1 is, for example, N Transistor Tr+ on a type silicon substrate
has a P channel structure in which P+ impurity doped regions 2.3 for the source S and drain D are formed, and a gate G is also formed.
Ｎ４″領域４は基板コンタクト用のものである。N4'' region 4 is for substrate contact.
さらにＮチャンネル構造のトランジスタＴｒ２を構成す
るためにＮ−基板１にＰ型物質の島５を形成し、該島内
にＮ＋不純物ドーピング領域６．７がソースＳ及びドレ
インＤ用に形成される。Ｐ＋領域８は島５内の電位を保
持させるためのコンタクトである。Further, in order to constitute a transistor Tr2 having an N-channel structure, an island 5 of P type material is formed on the N- substrate 1, and N+ impurity doped regions 6.7 for the source S and drain D are formed in the island. P+ region 8 is a contact for maintaining the potential within island 5.
上記構成において、Ｎ＋領域４に電圧ｖ１を、Ｐチャン
ネルトランジスタＴ ｒ ＋のソースＳ４こ電圧■２を
、ＮチャンネルトランジスタＴｒ２のソースＳに電圧ｖ
３を、Ｐ１領域８に電圧■４を加えるものとし、各電源
の電圧がＶｌ＞Ｖ２＞Ｖａ＞Ｖａの関係にあり、いま、
電圧■１と■４がオープン状態でＶ２及びＶａに電圧が
加えられたとすると、電圧ｖ２とｖ３間では第２図に示
すような等価回路のようにトランジスタＴｒｌソースの
Ｐ＋領域２一基板のＮ−領域１−島のＰ−領域５−トラ
ンジスタＴｒ２ソースのＮ＋領域６によってＰＮＰＮ接
合のサイリスク構成を生ずる。ここでＮ−領域１及びＰ
−領域５の電圧は不定であるため、例えば基板のＮ−領
域１とトランジスタＴｒ＋のソースＳのＰ＋領域２とが
順方向になる場合もあり得る。するとＰ＋領域２−Ｎ−
領域１（基板＞ −ｐ−領域５（島）のトランジスタは
「オン」状態となる。この状態では電圧Ｖ２に引っ張ら
れるためＮ−領域１−Ｐ−領域５−Ｎ＋領領域トランジ
スタＴｒ２のソースＳ）で構成するＮＰＮ領域も「オン
」状態となり、Ｐ＋領域２−Ｎ−領域１−Ｐ−領域５−
Ｎ＋領域６間、すなわち電圧Ｖ２と７３間では大電流が
流れる。このときの電圧条件はＶ２ Ｖｌ＞ＶＩＩＥ
またはＶａ−Ｖａ〉■ｇｐを満足した場合である。In the above configuration, a voltage v1 is applied to the N+ region 4, a voltage 2 is applied to the source S4 of the P channel transistor Tr +, and a voltage v is applied to the source S of the N channel transistor Tr2.
3, the voltage ■4 is applied to the P1 region 8, and the voltages of each power supply have a relationship of Vl>V2>Va>Va, and now,
Assuming that voltages 1 and 4 are open and a voltage is applied to V2 and Va, between voltages v2 and v3, the P+ region 2 of the transistor Trl source - N of the substrate is shown in the equivalent circuit shown in Figure 2. -Region 1-P-region 5 of the island-N+ region 6 of the transistor Tr2 source creates a PNPN junction silice configuration. where N-region 1 and P
Since the voltage in the - region 5 is undefined, for example, the N- region 1 of the substrate and the P+ region 2 of the source S of the transistor Tr+ may be in the forward direction. Then P+ region 2-N-
The transistor in region 1 (substrate> -p- region 5 (island) is in the "on" state.In this state, it is pulled by voltage V2, so that the source S of N- region 1-P- region 5-N+ region transistor Tr2 ) is also in the "on" state, and the P+ region 2-N- region 1-P- region 5-
A large current flows between N+ region 6, that is, between voltages V2 and 73. The voltage condition at this time is V2 Vl>VIIE
Or, this is a case where Va-Va>■gp is satisfied.
上記説明ではＶｌ、Ｖａを加えずＶ２．Ｖａの電圧を先
に印加した場合であるがその後電圧■１゜■４を加えて
ると上記した現象をトリガとしてラッチアップ現象が生
じ易くなる欠点を有していた。In the above explanation, V2. In the case where the voltage Va is first applied, if the voltage ■1°■4 is then applied, there is a drawback that the latch-up phenomenon is likely to occur triggered by the above-mentioned phenomenon.
（４）発明の目的
本発明は上記した従来の欠点に鑑み、４（Ｉｌｉ１以上
の電源を必要とするＣ−ＭＯＳの如き集積回路にいて、
電源投入順序によらずラッチアンプ現象を生じ難くした
集積回路を提供することを目的とするものである。(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides an integrated circuit such as a C-MOS that requires a power supply of 4 (Ili1 or more).
It is an object of the present invention to provide an integrated circuit in which the latch amplifier phenomenon is less likely to occur regardless of the order in which the power is turned on.
（５）発明の構成
この目的は本発明によれば、少なくとも複数のＰＮ接合
部を有する集積回路において、上記複数のＰＮ接合部に
４個以上の電源が接続されたサイリスタ構造のＰ’Ｎ接
合部の通當高電位電源が接続される側から低電位電源が
接続される側に順方向のダイオードを接続してう・７チ
ア・ノブ現象を防止するようにしたことを特徴とする集
積回路によって達成される。(5) Structure of the Invention According to the present invention, in an integrated circuit having at least a plurality of PN junctions, a P'N junction of a thyristor structure in which four or more power supplies are connected to the plurality of PN junctions. An integrated circuit characterized in that a forward diode is connected from the side to which the high potential power source is connected to the side to which the low potential power source is connected to prevent the U.7 chia-knob phenomenon. achieved by.
（６）発明の実施例
以下、本発明の一実施例を第３図及び第４図について説
明する。(6) Embodiment of the Invention An embodiment of the invention will be described below with reference to FIGS. 3 and 4.
第３図は本発明の集積回路の側断面図、第４図は第３図
の等価回路を示すものであり、第１図及び第２図と同一
部分には同一符号を付して重複説明を省略する。電圧Ｖ
１が加えられるＮ＋領域４（シリコン基板１のコンタク
ト用で−Ｎ領域）とトランジスタＴｒ＋のソースＳであ
るＰ＋領域間に基板１を順方向とするダイオードＤ１を
構成する。該ダイオードはＮ−のシリコン基板１にＰ＋
領域の島１１ａを作り、該島１１ａ内にＮ＋領域９ａ、
及びＰ＋領域１０ａよりなるアノードとカソードを形成
すると共に上記したＰ＋領＠２とダイオードＤＩ内のＰ
＋領域１０ａを接続し、電圧ｖ１の与えられるＮ＋領域
４とダイオードＤ１内のＮ＋領領域を接続する。FIG. 3 is a side cross-sectional view of the integrated circuit of the present invention, and FIG. 4 shows an equivalent circuit of FIG. 3. The same parts as in FIGS. omitted. Voltage V
A diode D1 whose forward direction is the substrate 1 is formed between the N+ region 4 (-N region for contact of the silicon substrate 1) to which 1 is added and the P+ region which is the source S of the transistor Tr+. The diode is connected to an N- silicon substrate 1 and a P+
A region island 11a is created, and within the island 11a, an N+ region 9a,
and the P+ region @2 and the P+ region in the diode DI.
+ region 10a is connected, and N+ region 4 to which voltage v1 is applied is connected to N+ region within diode D1.
同様に電圧Ｖ３の加えられるトランジスタＴｒ２のソー
スＳ、すなわちＮ＋領域６と電圧■４の加えられる島５
とコンタク１〜を取るＰ＋領域８間にダイオードＤ２を
Ｎ＋領域６を順方向として形成する。Similarly, the source S of the transistor Tr2 to which the voltage V3 is applied, that is, the N+ region 6, and the island 5 to which the voltage 4 is applied.
A diode D2 is formed between the P+ region 8 and the contact 1 with the N+ region 6 in the forward direction.
すなわち、基板ｌに島となるＰ＋領域１１ｂを形成し、
該島内にアノード及びカソードとなるＮ＋領域９ｂとＰ
＋領域１０ｂを形成し、上記したＮ＋領域６とダイオー
ドＤ２内のＮ＋領領域ｂ間を接続し、電圧■４の加えら
れるＰ＋領域８とダイオードＤ２内のＰ＋領域１０ｂを
接続させる。That is, a P+ region 11b serving as an island is formed on the substrate l,
In the island, there are N+ regions 9b and P which become an anode and a cathode.
A + region 10b is formed to connect the above-mentioned N+ region 6 and the N+ region b in the diode D2, and to connect the P+ region 8 to which the voltage 4 is applied to the P+ region 10b in the diode D2.
かくすれば、第４図の等価回路で示すような集積回路が
得られる。In this way, an integrated circuit as shown in the equivalent circuit of FIG. 4 can be obtained.
このようなＣ−ＭＯ３構成の半導体装置では上記したダ
イオードをＣ−ＭＯ３半導体と同一プロセス内で同時に
形成できることば明らかである。It is obvious that in a semiconductor device having such a C-MO3 structure, the above-mentioned diode can be formed simultaneously with the C-MO3 semiconductor in the same process.
上記実施例ではＮ型シリコン基板上に（、−ＭＯＳを構
成した場合について述べたがＰ型シリコン基板上にＣ−
ＭＯＳを構成させた場合にもダイオードを同時形成させ
てランチアンプ現象を生じないようにすることが可能で
ある。さらにＣ−Ｍ、Ｏ３構成に限らず例えばＰＮ接合
部で構成される抵抗器容量等を集積化した場合でも、そ
の構成においてサイリスク構成を形成するものに本発明
を適用し得ることは明らかである。In the above embodiment, the case where a (-MOS) was constructed on an N-type silicon substrate was described, but a C-MOS was constructed on a P-type silicon substrate.
Even when a MOS is configured, a diode can be formed at the same time to prevent the launch amplifier phenomenon from occurring. Furthermore, it is clear that the present invention can be applied not only to the C-M and O3 configurations, but also to those that form a si-risk configuration, for example, even when a resistor capacitance, etc. consisting of a PN junction is integrated. .
上述の如き構成によればＶ２−Ｖ＋≦ＶＪＩＥ 。According to the configuration as described above, V2-V+≦VJIE.
Ｖ３−Ｖａ≦ＶＩＩＥの条件が満足されればＰＮＰＮの
サイリスク構成でも電圧ｖ２とＶ３の加える領域間にダ
イオードＤ１とＤ２の作用で大電流が流れることはない
。If the condition of V3-Va≦VIIE is satisfied, no large current will flow between the regions to which voltages v2 and V3 are applied due to the action of diodes D1 and D2 even in the PNPN sirisk configuration.
（７）発明の効果
以上、詳細に説明したように本発明の集積回路によれば
ランチアンプ現象を生じない集積回路を提供しうる特徴
を有する。(7) Effects of the Invention As described above in detail, the integrated circuit of the present invention has the feature of providing an integrated circuit that does not cause the launch amplifier phenomenon.
第１図は従来の集積回路の側断面図、第２図は第１図の
等価回路、第３菌は本発明の集積回路の側断面図、第４
図は第３図の等価回路である。
１・・・シリコン基板、 ２．３・・・Ｐ＋不純物ドー
ピング領域、 ４・・・Ｎ＋領領域 ５・・・島、 ６
．７・・・Ｎ＋不純物ドーピング領域、 ８・・・Ｐ＋
領域、 ９ａ、９ｂ・・・Ｎ＋領領域 ｌｌａ、１ｌｂ
−・・島。
特許出願人 富士通株式会社FIG. 1 is a side sectional view of a conventional integrated circuit, FIG. 2 is an equivalent circuit of FIG. 1, third is a side sectional view of an integrated circuit of the present invention, and FIG.
The figure is an equivalent circuit of FIG. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2.3...P+ impurity doping region, 4...N+ region 5...Island, 6
．． 7...N+ impurity doping region, 8...P+
Area, 9a, 9b...N+ area lla, 1lb
-...Island. Patent applicant Fujitsu Limited
Claims (1)
、上記複数のＰＮ接合部に４個以上の電源が接続された
サイリスク構造のＰＮ接合部の通常高電位電源が接続さ
れる側から低電位電源が接続される側に順方向のダイオ
ードを接続してラッチアップ現象を防止するようにした
ことを特徴とする集積回路。In an integrated circuit having at least a plurality of PN junctions, a low potential power supply is connected from the side to which a high potential power supply is normally connected to the PN junction of a cyrisk structure in which four or more power supplies are connected to the plurality of PN junctions. 1. An integrated circuit characterized in that a forward diode is connected to the side to be connected to prevent a latch-up phenomenon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113137A JPS594068A (en) | 1982-06-30 | 1982-06-30 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113137A JPS594068A (en) | 1982-06-30 | 1982-06-30 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS594068A true JPS594068A (en) | 1984-01-10 |
| JPS6244426B2 JPS6244426B2 (en) | 1987-09-21 |
Family
ID=14604490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57113137A Granted JPS594068A (en) | 1982-06-30 | 1982-06-30 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594068A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509585B2 (en) * | 2000-03-20 | 2003-01-21 | Winbond Electronics Corp. | Electrostatic discharge protective device incorporating silicon controlled rectifier devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
-
1982
- 1982-06-30 JP JP57113137A patent/JPS594068A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509585B2 (en) * | 2000-03-20 | 2003-01-21 | Winbond Electronics Corp. | Electrostatic discharge protective device incorporating silicon controlled rectifier devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6244426B2 (en) | 1987-09-21 |
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