JPS6244426B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an integrated circuit which is made less likely to cause the latch-up phenomenon that occurs when the integrated circuit has a thyristor structure.

(2) Background of technology Recently, many analog-to-digital conversion circuits and digital-to-analog conversion circuits have been integrated into integrated circuits.

Such an analog circuit requires a ground power source for comparison in addition to the two power sources for operating the analog circuit. Furthermore, a reference power source is also required for digital-to-analog conversion circuits and the like. In this way, when analog circuits that require multiple power supplies are integrated to create an integrated circuit with a complementary metal oxide semiconductor (hereinafter referred to as C-MOS) configuration, it is necessary to create a thyristor structure between the multiple power supplies. This causes a latch-up phenomenon (i.e., in a complementary integrated circuit comprising a P-channel MOS transistor and an N-channel MOS transistor, the PNPN structure constituted by each impurity region and the substrate is turned on due to external noise, (a phenomenon in which current continues to flow) may occur.

(3) Prior art and problems Figure 1 is a partial side sectional view of an integrated circuit with a conventional C-MOS configuration, and Figure 2 is an equivalent circuit of Figure 1.
In FIG. 1, 1 is an N-type silicon substrate, for example, and a transistor Tr ₁ has a P channel structure, with P ⁺ impurity doped regions 2 and 3 for source S and drain D.
is made, and a gate G is also formed.

N ⁺ region 4 is for substrate contact.
Further, in order to configure a transistor Tr ₂ having an N-channel structure, an island 5 of P type material is formed on the N ^- substrate 1, and N ⁺ impurity doped regions 6 and 7 are formed for the source S and drain D in the island. . P ⁺ region 8 is a contact for maintaining the potential within island 5.

In the above configuration, voltage V ₁ is applied to N ⁺ region 4, P
A voltage V ₂ is applied to the source S of the channel transistor Tr ₁ .
Assume that voltage V ₃ is applied to the source S of N-channel transistor Tr ₂ and voltage V ₄ is applied to P ⁺ region 8, and the voltages of each power supply have a relationship of V ₁ > V ₂ > V ₃ > V ₄ , Now, voltages V ₁ and V ₄ are open and V ₂ and
Assuming that a voltage is applied to V ₃ , between the voltages V ₂ and V ₃ , the equivalent circuit shown in Figure 2 is as follows: P ⁺ region 2 of the transistor Tr ₁ source → N ^- region 1 of the substrate →
The P ^- region 5 of the island→the N ⁺ region 6 of the transistor Tr ₂ source produces a PNPN junction thyristor configuration. Here, since the voltages of the N ^- region 1 and the P ^- region 5 are unstable, for example, the N ^- region 1 of the substrate and the P ⁺ region 2 of the source S of the transistor Tr ₁ may be in the forward direction. Then P ⁺ area 2 → N ^- area 1
(substrate)→P ⁻ The transistor in region 5 (island) is in the “on” state. In this state, since it is pulled to the voltage V ₂ , the NPN region consisting of N ^- region 1 → P ^- region 5 → N ⁺ region (source S of transistor Tr ₂ ) also becomes "on" state, and P ⁺ region 2 → A large current flows between N ^- region 1 → P ^- region 5 → N ⁺ region 6, that is, between voltages V ₂ and V ₃ . The voltage condition at this time is V ₂ −V ₁
>V _BE or V ₄ −V ₃ >V _BE .

In the above explanation, the voltages V _{2 and V 3 are} applied first without adding V 1 and V 4, but if the voltages V ₁ and V ₄ are applied afterwards, the latch-up phenomenon is likely to occur with the above phenomenon as a trigger. It had drawbacks.

(4) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional technology, the present invention provides an integrated circuit that is less likely to cause a latch-up phenomenon regardless of the power-on order in an integrated circuit such as a C-MOS that requires four or more power supplies. The purpose is to provide the following.

(5) Structure of the invention According to the present invention, this object is achieved by at least a plurality of
In an integrated circuit having a PN junction, the side of the PN junction of a thyristor structure in which four or more power supplies are connected to the plurality of PN junctions, from the side to which a high potential power supply is normally connected to the side to which a low potential power supply is connected. This is achieved by an integrated circuit characterized in that a forward diode is connected to the terminal to prevent the latch-up phenomenon.

(6) Embodiment of the Invention An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 is a side sectional view of the integrated circuit of the present invention, and FIG. 4 shows an equivalent circuit of FIG. 3. The same parts as in FIGS. The explanation will be omitted. N ⁺ region 4 where voltage V ₁ is applied
A diode _D1 whose forward direction is the substrate 1 is formed between the -N region for contact of the silicon substrate ₁ and the P ⁺ region which is the source S of the transistor Tr1.
The diode has an island 11a of a P ⁺ region formed on an ^N- silicon substrate 1, and an N ⁺ region 9a, a
and a P ⁺ region 10a, and connect the P ⁺ region 2 and the P+ region 10a in the diode _D1 , and connect the N ⁺ region 4 to which the voltage _V1 is applied and the P ⁺ region 10a in the diode _D1. Connect with N ⁺ area.

Similarly, a diode D ₂ is connected between the source S of the transistor Tr 2 to which the voltage V ₃ is applied, i.e. the N ⁺ region 6 and the P ⁺ region 8 which makes contact with the island 5 to which the voltage _{V 4} is applied ^. form as.

That is, a P ⁺ region 11b serving as an island is formed on the substrate 1, and an anode and a cathode are formed within the island.
N ⁺ region 9b and P ⁺ region 10 are formed, and the above N ⁺ region 9b and P + region 10 are formed.
Connect between region 6 and N ⁺ region 9b in diode D ₂ and P ⁺ region 8 to which voltage V ₄ is applied and diode
Connect the P ⁺ region 10b in _D2 . In this way, an integrated circuit as shown in the equivalent circuit of FIG. 4 can be obtained. According to this circuit, even if the voltages V2 and V3 are applied first and the voltages V1 and V4 are not applied, and the potential changes due to noise being applied to the substrate 1 or the n-type region 6, the potential of each region is diode D
1 and D2, and the PN junctions formed by P-type region 2 and substrate 1 and P-type region 5 and N-type region 6, respectively, are prevented from turning on. Therefore, the thyristor with the PNPN structure is not conductive, and the latch-up phenomenon can be prevented from occurring.

It is clear that in a semiconductor device having such a C-MOS configuration, the above-mentioned diode and the C-MOS semiconductor can be formed simultaneously in the same process.
In the above embodiment, a C-MOS is placed on an N-type silicon substrate.
Although we have described the case in which a C-MOS is constructed on a P-type silicon substrate, it is possible to prevent the latch-up phenomenon by forming diodes at the same time. Furthermore, C-MOS
It is clear that the present invention can be applied not only to the configuration but also to those forming a thyristor configuration, for example, even when a resistor capacitor or the like constituted by a PN junction is integrated.

According to the above configuration, V ₂ −V ₁ ≦V _BE , V ₃ −
If the condition of V ₄ ≦V _BE is satisfied, no large current will flow between the regions to which voltages V ₂ and V ₃ are applied due to the action of diodes D ₁ and D ₂ even in the PNPN thyristor configuration.

(7) Effects of the Invention As described above in detail, the integrated circuit of the present invention has the feature of providing an integrated circuit that does not cause the latch-up phenomenon.

[Brief explanation of the drawing]

FIG. 1 is a side sectional view of a conventional integrated circuit, FIG. 2 is an equivalent circuit of FIG. 1, FIG. 3 is a side sectional view of an integrated circuit of the present invention, and FIG. 4 is an equivalent circuit of FIG. 3. . 1... Silicon substrate, 2, 3... P ⁺ impurity doped region, 4... N ⁺ region, 5... Island, 6,
7...N ⁺ impurity doped region, 8...P ⁺ region, 9a, 9b...N ⁺ region, 11a, 11b...
…island.

Claims (1)

[Claims] 1 In a complementary integrated circuit comprising a P-channel transistor and an N-channel transistor, a region of one conductivity type and a region of the opposite conductivity type forming a PN junction are clamped to clamp the potential difference between the two regions. An integrated circuit characterized in that a diode is provided to prevent a junction from being turned on.