JPS5940661A - Image forming device - Google Patents

Abstract

PURPOSE:To shorten a copying time, by starting operation of at least one of the 2nd processing means which transfer plural visible images before the 1st processing means for forming a latent image finishes operation. CONSTITUTION:When an electric power source is turned on, a screen heater 18, etc., are turned on to enter a preparation state. Then, when the number of sheets is set on a console panel 61 and a key ''SING'' or ''MULT'' for starting copying operation is pressed, a motor for a screen drum rotates. A primary latent image is formed on a screen simultaneously with the operations of a primary electrostatic charger 4 and a secondary destaticizer 6. When a copy start key is operated, a dust figure transferring a charger 36, etc., turn on. After the primary latent image is formed, the motor is turned off and a motor for an insulating drum is turned on to start the copying operation. Thus, the copying time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image forming apparatus such as a copying machine, etc. 1. The applicant of the present application has previously proposed an apparatus that repeatedly forms visible images from the same latent image (Japanese Patent Application No. 5O-143178).

In this method, visible images are repeatedly formed even if the operation of the processing means necessary for forming the primary latent image is completely stopped.Therefore, when copying several sheets, there is an inconvenience that 1411 is required when copying.

The present invention eliminates the above drawbacks.

Fourth, by using this example, 7-
It is possible to program the sequences in chronological order, which has a feature that makes it extremely easy to change the sequence.

Furthermore, this example allows the high beam gtt corpse of the circuit to be 1
It has the feature of greatly reducing the number of parts.

Furthermore, this embodiment has the feature that sequence control of different copying apparatuses can be performed by using the same circuit and using only the program.

Furthermore, in this example, in order to drive a predetermined device, it is impossible to perform any necessary steps until the process 'f leading to driving the device has been completed, so there is no malfunction caused by an erroneous input signal.

Furthermore, this embodiment has the feature that there is no inconvenience in sequence control because the PC system is used to monitor the execution of the four-gram pattern at predetermined points in the progress of the actual copying process, such as the drum home position.

Hereafter, a primary latent image is formed from the original, a secondary latent image is repeatedly formed from this primary latent image, and a secondary latent image is formed on the L7 lever. 4 retention copying machines that develop and transfer to produce multiple copies.
The present invention will be explained using an example in which sequence control is performed by a bit-parallel processing microcomputer.

The copying process will be outlined with reference to FIG. 1, a cross-sectional view of a copying machine, and FIG. 2, a time chart. 61
is the key operation panel, and 51 is the manuscript manual? 52 is an exposure lamp, 55, 54.56, 57.58 are reflective mirrors, 5
5 is a lens system, 1 photosensitive drum, 5 is a front irradiation lamp, 4
is a primary charger, 6 is a secondary static eliminator, 7 is a full-surface irradiation lamp,
16 is a pre-modulation bander, 11 is a modulation charger, 8 is an insulating drum, 24 generators, 33 is a paper feed roller, 34 is a timing roller, 56 is a transfer charger, 75 is a separation claw, 70.7
2 is a paper detector, 45 is a fixing roller, 47 is an output tray,
51 is transfer paper, 14 is a blower.

Reference numeral 18 denotes a heater, and the photosensitive drum 1 has a mesh-like photosensitive member (for example, detailed in Published Patent No. 19455 published in 1975) having a transparent insulating layer and a photoconductive J-5 conductive layer all around the drum. Also, the wide charger is temporally
It is spatially divided into front and rear parts.

The operation of the copying machine is performed by commands from operation C→61. Consists of an operation panel 61 and two indicators 62°63.2 (same pilot lamps 65.66 and a keyboard 64. Numerical keys from "O" to "9" on the keypad 64 indicate the number of copies. The contents of each press are entered in the display 62. The "Oo" key means an infinite number of times, and lights up the pilot lamp 65 of Lr0OJ.

Next, the key [RJ (1'l'lj;N'l'TON) is formed on the screen q 7″ci times of silence 1; along the image t
r is used to set the number of copies of n that can be obtained repeatedly. The contents are displayed on the display 65 or pilot lamp 66.

"co" [cR1 key is used for each set number of hitting surfaces.

1'-8TNGJ is the copy amount f (@ VCl[MU
LTJ selects l- at the beginning of Ijrl for multiple copies using numerical keys.
8TOjl is used to stop copying before the set number of copies are completed.

Next, the time chart shown in FIG. 2 will be explained. When the power switch is turned on, the screen heater 18, fixing roller heater, etc. are turned on, and after a waiting time, the preparation state is entered. Then, the number of sheets is set from the operation panel 61, and then the screen drum motor 71 rotates when the T, Tl keys are pressed to start copying. When the fireworks clutch is activated, the first reflecting mirror 53, which is installed integrally with the original 11θ light rung 52 and the lamp reflecting mirror, moves at a speed [Vl] that is mutually synchronized with the circumferential speed of the screen drum 1. Therefore, as described below, the optical system home position is set and the exposure process is started.During the original illumination lamp 1@ irradiation, the screen and drum motor 111 rotates at V1, and this turns off.
Motor for insulated drum 1. When f1' is turned on at the same time, v
At r, both drums increase to about twice the speed of 1tLV2.

While the screen and drum motor M1 is rotating, the front irradiation lamp 3 and the entire surface irradiation lamp 7 are turned on and the entire exposure is performed14. T
An optical cooling fan is driven to prevent heat from accumulating in the optical system due to illumination by the illumination lamp 52. and - wide charger 4,
60 works of secondary static eliminator +l+! Form the image on the screen -H with + as described above.

My father, the aforementioned copy start key is Lmh <, and the powder image transfer band/t
The M device 56, paper separation charger 57, insulated drum static eliminator 50, and paper separation suction fan are turned on and turned off at the end of the copying operation. However, since the chargers 56, 37, and 50 have the circumferential speed of the screen and drum motor and the rotational speed J of the insulating drum, the excess charge is not charged on the insulating drum.
- Reduce the potential so that it does not occur.

When the next VC1-next residue image formation 1 & screen drum motor is turned off and the insulated drum motor is turned on, modulation-3
'q, copying operations such as image-paper transfer-separation are started. After modulation, the first sheet of copying is completed by three revolutions of the screen drum, but after that, one sheet of copying is completed every time the screen drum makes one revolution.

The rotation of the Ichigozu drum is the motor M1'p for the insulated drum.
When c +J+ changes, VC1 modulation front band 'I+c unit 15
Then, the conveyor roller clutch for transmitting the chipping of the cleaning motor to the conveyor belt 38 (?4', '1) is turned on. As the rotation progresses and the screen drum returns to its home (r (228 degrees from 4), the screen drum
The modulation charger 11, which is used to transfer the 1 to 18 yen noise formed on the drum to the insulated drum, is turned on, and the paper feed roller and clutch C are turned on to feed one sheet of paper f on the paper feed stand at 241°.
I and 3 are turned on, and the screen drum enters the second rotation cycle after starting modulation, and the paper feed roller clutch CL3 is turned off at the home position, and the paper is fed from this nK. ;r: In order to match the tip of iA and the developed stone statue on the insulated drum, the timing roller
Clutch CL4 is at stage 40' of current fault motor operation, 16
Turns on at 0°. If the number of copies is 1, 228° is 11'! At #', the adjustment iron 511 turns off, but in this case it does not turn off because it is 2 +. Go further, 2
At 4F, the roller clutch CR, 5 is turned on, and the 2
Feed the first sheet of paper. At 36o0, turn off the first timing roller and clutch DL4. Entering the third rotation cycle, Bohm position 1. ;Y is the paper feed roller clutch,
Turn off the first timing roller/clutch and turn 1 n
Set the timing roller f25 with o o.

2nd timing roller/clutch CL4 at 160o
Turn on. , at 228°.

Turn off the modulation charger. If it is one copy, 50
0 turns off the developing motor M2 and the toner bridge prevention motor.

Offload the timing roller and clutch at 560°. 2
In sheet copying, at the fourth rotation cycle 50', the motor M2 and the toner bridge prevention motor are turned off, and at 53Q', the insulated drum motor IJ1r and the conveyance roller clutch are turned off, and the two-sheet tenon is turned off. End the cycle.

The separation pawl solenoid SL1, which separates the paper from the insulating drum, operates between 276° and 316° during the second and subsequent cycles.

Figure 3 shows the circuit configuration for controlling the operation of each device in the copying machine that executes the copying process as described above. ROM
3-1 is a reading console memory which is capable of storing sequence contents of a copying machine in advance in order and storing them at each address, and from which the contents can be retrieved each time an address is set. That is, n itself is a well-known matrix number μg, which is set in advance with a code from address 0 to the required final address of 11.
4. The control contents (Yic 8 dit binary code)
(Including not only the operating output of the device but also the control details of other circuits)
f memorize. ■1 to 2i are input devices that memorize copy headers, details) [n 3 and 01 to 4 shown in Figure 3-4 are devices that output signals that control the operation of copying equipment, and details are shown in Section 5-5. As shown in the figure.

RAM is a read/write memory that stores temporary signals aυ during copy number and process control. A set of 7 rip-flops and flops constitutes an inverse number of sets, and an arbitrary set is selected by an address designation signal, and data can be written to or read from multiple 7-rip-flops among them. do. CPU and above memory,
One or more registers pB for addressing input/output devices
, PC, and one or more registers A for primary storage,
B, O, D data (control unit C that has an addition arithmetic logic operation function that decodes and processes data input from line i)
T, and is imaged by a line of multiple θ with respect to the external circuit.

To briefly explain, the CPU executes the program L * ROM] address f designation (7, the content of the specified address is the entire data signal line 86, and the OPU [Read], the CPU decodes this and confirms it. According to the read contents, *When it is in chronological order from power supply input, data is processed using the contents of the CjPU itself, and when it is, data in the CPU is stored in RAM.
Store data at a specified address in RAM, input data at a specified address into the CPU, and sometimes output data in the CPU to the output signal line 88 of the input/output section. Input signal of section 1y a Contents on 9 p
The sequence system 1 is performed by inputting the data into the aptr.

The control procedure according to the present invention will be explained in detail below.

The basic timing for the undisturbed sequence φ program It 3IIj will be explained with reference to the clock time chart of FIG. Individual program instructions are stored in ROM
It is pre-coded and stored in 8 main lines,
To designate each code, 0 codes from the address code bus are decoded by an address decoder, and one of the 20 codes is selected and output. This ROM and RO
The address where the instruction in M is stored is designated by the ROM address designation register (pc). This register (R
e) has a function of incrementing by +1 using the control signal α1, whereby programmed commands are output one after another. This register PC is input to the ROM by multiplexers A and O at predetermined times. The ROM outputs the instruction code on 8 lines, but since the data code bus has 86 lines and 4 lines, it is time-divided and output to the data code bus in two parts. BH9, BH according to the signal α of 2 and 3 clocks of instruction codes output in 2 times of 4 each
3. The contents are latched in registers C and D by opening and closing of BH7, and the contents are decoded by an instruction decoder, which generates a control signal α for processing according to the contents of this instruction. In short, it takes four basic clock cycles to complete the designation of the address where the program is stored and the decoding of the instruction code stored at that address. Execute. Then, the programmed command following the address is executed again at concave time intervals.

Therefore, one of the programmed sequences
It takes time equivalent to 101 clocks to execute an execution instruction (one step). It's 2 words, but it takes 20 pieces of glue.

Note that registers A and B are for calculation, and each switch SW is a gate circuit controlled by control tflll IM number α.
OVF is a circuit known per se for detecting overflow of register A.

Control (+41 part OT register O, Df decoded register A
, B, and outputs a control signal α.The functions of the circuit are shown schematically as shown in FIG.

Each latch of the output device of the copying machine ff (e.g. flip 7)
The correspondence between the output device and the output device is as follows.

First surface force 5θ2 Developing motor 4ε The correspondence between the status signal of this copying machine and each latch input line of the input device is as follows.

A specific example of these input/output circuits is shown in FIG. 5.6. Fifth
The figure shows a case where each T10 corresponds to a 4-bit output line, and FIG. 6 shows a case in which a converter is provided in the case of 4 or more.

Table 2 First speed If of the drum motor of the copying machine shown in Figure 1
h 120g++x/8eC1 second speed IW is 56
0mrtt/θec. Two internal generators (this can be an astable multi-vibrator or an example) are built in to generate one pulse per screen and drum rotation angle +ij-1°eC. Since the diameter of the screen drum is 110 mψ, the clock period of clock pulse 1 is approximately 8 ro/8 ec, and similarly the clock period of VC clock pulse 2 is 2.66 m/aec.

These clock pulses are several times faster than the insulated drum.
This can be generated by optically detecting the hole 60 in the rotary plate 56 that rotates.

When the above-mentioned signal is at the ``1'' level, it is ``No or NG''.
”, and “0” level means “6” or “GOOD”f
means.

Note that the control σ in Figure 3-2 (one circuit is 4 with readout control signal 2)
It consists of a known gate circuit to which a bit signal is output, and a known gate circuit to which 4 bits are inputted by the divisor/write control signal 2.

The control circuits in Fig. 3-3 for the father and Fig. 5-4 for the nest are for each.

It consists of a known gate circuit that outputs a data code based on the output control signal 2 and the selection signal of the output device 0, and a known gate circuit that takes in the data code based on the input control signal 2 and the selection signal of the input device uT.

Next, referring to FIG. 7, a schematic flow of copy control using a program method will be explained.

After the power is turned on, a key entry cycle is first executed to set the number of copies and start copying, and if the machine is in a standstill state in which nothing is done, the cycle is looped and a key entry waiting state is entered.

When the operator enters the desired number of copies and presses the copy start key, execution of the copy cycle begins. End mode (i.e., place (
7 (This refers to when the number of copies is completed, when a stop command is received, when the toner runs out, when the paper runs out, etc.)
If it is not in end mode, the copy cycle is looped. If you are in exit mode,
Stop the copying operation, return to the initial cycle of setting the desired number of copies and entering the copy start key, and wait.Since the copying operation is processed sequentially as in the first trial, the number of copies during the copying cycle is The keys entry for setting and copy start is set to M+, and the copy cycle does not start during key entry.

(Key entry cycle) Key entries are numeric keys from 0 to 9 to set the desired number of copies, "Multi" key to start copying, 1 "Single" key to start copying one copy, 6 to issue a stop command. This is done using the "Stop" key and the "Request" key for correcting the settings.

The process will be explained below with reference to the entire flow shown in FIG.

The number of copies per copy can be set up to 2 digits (that is, 99 copies), and the 1st digit is addressed to the RAM address 1, and the 2VT is addressed to the RAM memory 2. After turning on the power, press R on the display with BT+IPO-1.
Display the AM1 and 2nd J loop data and wait for the key to be pressed at 5TKPO~2. Therefore, the numeric display indicates that the power is on. You can check l. 8 when a key is pressed
1PO-3 determines whether it is a numeric key or any other key, executes 5TFtPO-4, 0-5f to release the numeric key, stores the numeric value pressed at 4r in RAM address 1, and 5IPO-
Go back to 1 and display this.

Therefore, numerical settings can be displayed starting from the lower digits, which is convenient.

5TWPO-5f, number 614 #-I key stroke 8Tl! ;Proceed to PO-6 and beyond. If it is the ""rear" key, 5TKPO-7T RAM? Clear, 5TE
PO-1 [Return, display “oo”. If it is multi-key, proceed to the copy cycle, and "single" 1-key rubber 5T
KPO-9TE enters 1'' in RAM address 5 and proceeds to the copy cycle.RAM address 5 is used to determine whether the final mode is on or not; if it is 0'', the next copy cycle 4A/
Proceed to 1, and when it is 1, the end mode is set. This ROM address 5 is used to execute one copy cycle and then determine whether or not it is in the end mode. (See Figure 8) (Ne-M photo cycle) Following the key entry cycle mentioned above.

A copy cycle is then entered to execute the steps shown in the flowchart of FIG.

First, at 5TlltP1, it is checked whether there is copy paper or present agent and whether the stationary heater is at a predetermined level. If No, it waits until OK is reached. If the above state is OK, proceed to s'rgp 2 and start the drum motor (Vl) rotating in the first series. This 5TEP1
, 2 will be explained in detail later.

Next, use +3TKP 3 to check whether the optical system is at the home position, and if it is not at the home position, turn on the compensating clutch so that the optical system moves to the right when looking from the east front, and - Mechanically connect the motor and move it to the home position. When the home position is reached, the clutch is turned off at 5TP2P5 to stop the optical system. Therefore, scanning can always be started from a fixed position.

Next, the entire home position of the screen drum, which is mechanically connected to the drum motor and is already rotating synchronously, is confirmed using the 5TFiP6, and the home position is confirmed! # If there is no VC, wait until the rotating screen drum is at its home position. The details are described below (Figure 11). When the camera reaches the home position 1A, the optical system for the 11th lens is already on standby at the home position 1Q, so the copy creation cycle starts from 5TEP7 onwards.

First, the pre-irradiation lamp, primary charger, and exposure rung are all turned on. The drum motor is already rotating at this time, but STF! Since the second speed drum motor is turned off at P72 and returned to 5TIDP7 after fc, it is necessary to switch to the -th speed LW at this time, so the first speed drum motor is turned off again at 5TBiP7. Start it. Assuming that one latent image formed on the screen drum makes 10 copies, for a total of 55 copies, 6
Since the latent image must be generated twice, the number of repetitions must be stored in a part of the memory in advance. Therefore, when STFiP7 enters the copy cycle, it is stored at address 4 (in this case 10?) in the RAM as described above.

Next, enter VC8TKP8 and count the number of clock pulses generated per degree of rotation of the screen drum rotating in the first gear, and if this reaches 60 (i.e., when the screen drum has rotated 60'' from its home position) 5TKP
At 9, 1 wide belt device (rear) is applied to the woman. Thereafter, in the same way, when apl reaches 105, the secondary static eliminator is turned on at 5TEP11, and then, when OPl is 12, the forward clutch is turned on to move the optical system from the front of the main body to the right (STEP12). , 15).

Thereafter, it waits for the screen/drum home position to be read again (sT+rp14). That is, 5TBP7~1
4, if the frequency of clock pulse 1 deviates from synchronizing with the rotation of the screen drum, or if there is a mistake in counting, the sequence will be controlled depending only on the counting of clock pulses. STI! iP7~14
During one rotation of the screen drum up to this point, the VC occurrence time is accumulated, so this can be prevented by resetting the total U of 5TEP14. Similarly, 5TIi: P35, S T
EiP57 and 5TKP61 are also provided for the same reason.

The steps after 5TKP15 are based on the same idea as above, so the details will be omitted.

That is, in this device, the rotation angle of the screen drum (that is, the number of pulses) from one change point to the other in the sequence is stored in advance in the memory, and when the number of pulses is reached, the control II equipment fIt is turned on. , turn it off. In other words, when 48 pulses are counted from the drum home position, the front 1 wide band charger is turned off (step 16), when 55 pulses are counted, the rear primary charger is turned off (step 18), and when 47 pulses are counted from the drum home position, the forward clutch is turned off. , the exposure lamp is turned off I~ to end the document scanning (step 20). Therefore, there is no need to provide an optical system detection switch on the moving path for terminating scanning.

Next, do 20 pulses and count 10 pulses, 5TKP2
4, the creation of the Seiden image on the screen drum is completed,
Since the transfer cycle to the insulated drum immediately begins, the drum motor is switched from the first speed IW to the second speed IW. Therefore, the clock to be counted thereafter is the clock pulse 2 (described above) generated by the rotation angle +f 1° VC of the screen drum rotating at the second speed IW.

4 system as below? All is performed to turn on the paper feed roller (step 30), and when 39 pulses are counted, the optical system's reverse ω clutch is turned on to move the optical system backward. Therefore, there is a delay until the first movement stops and the second movement starts, so there is less shock when switching to g movement.

Since the entire movement of T is started repeatedly without waiting for the start and completion of K movement, the copying time can be shortened. One copy C with 5TLP43
11IL, 5TKP44 Determine whether a 5TOP instruction has been issued, and if a 5TOP instruction has been issued, enter all 1 to RAM address 3 and end the r mode.'lr: Memory. In addition, STE'P45 judges whether the desired number of copies set in the key entry cycle matches the number of copies.
Enter 1 in the RAM 1 register to indicate the end mode.

If they do not match, proceed to p[5TEP47, 5TE
1f from the number of repetitions set in RAM address 4 in P7
Pull, 5T) CP48 determines whether the RAM4 address is 0, jumps to 5TKP46, and enters the same (' 1 to RAM3 address.And if it is the end mode, 5TF
Turn off the screen bias latent image transfer charger on the iP49. 5TKP51.5TKP60,5
TKP f, 6. l-j i-1zua mo+winter r
-E= -)'-4-to') Distinguish color. When the end mode is entered, 5TKP51 is set and the paper feed port is set to OFF (1+t). However, in step 54, the molecule f
Turn on the P claw and continue the entire sequence under L. , 5 TEP 66 has the Bohm position 1j of the next screen drum, and if the step is not in the end mode, it returns to 5 IT FiP 40 and repeats copying from the primary latent image. 1. 8 T E P 68 It is determined whether the end r mode has reached the number of repetitions, or whether it is due to another 5TOP command or the number of copies being made matches the set number of copies, and if it is the former, the screen drum rotates one more time at 5TEP71. Screen drum home (
Wait for M rE't, and if it's in the middle, it's 2nd gear! ! Turn off the drum motor of f: and return to ETFiP7, ? Switch to the drum motor of y, 1 degree, and repeat step f from electrostatic m image formation again. In the latter case, use BTFP and P67 to find the screen/drum home position, and when cp2 is 330 (day IP69) (/C Nara 7'n), turn off the drum motor (V2) and restart the copy cycle. Completely complete and return to the first key entry cycle, again with operator command 'f#'.

Ending the copy cycle at 330 (i.e., 500 before the screen drum reaches its home position) causes the drum to reach t=dry home position I
Prevents stopping F after passing W.

Therefore, next, the operator issues a copy command, 5TEP, 5
This eliminates the extra 114 turns required for the first copy VC to reach the screen drum's home device.

The program instructions for executing each step of 1'J-h will be explained using the case of μC0M4 manufactured by 8 Densha.

1, 0100 X+X2XxX4 Address specification command Y
IY2Y5Y4 ZIZ2Z3Z4X 1~4
iPB! ! F, Yl~4fPB2 F, z1~4
Transfer to FB+.

While the program is being executed, a certain address in the ROM is designated by the PC, and at time 3 and 0 T1, code 0100 is output to the data code bus.

At T2, it is latched into the resistor C by opening and closing SW 14. Same (T2 decodes this and recognizes that it is a tf pond specification command 1~Same ('T2 follows XI~4 is output to the bus line and is latched into register PB3 by opening/closing of T5 SW9, 5WI5.Continued) , add 1 to pc, and RO
Code Yl-4, Z+ ~ 4 of address following +ifl notation of M
f PB2. (Each is stored in PB+, so store the new address f;rPBK that you want to use later in 10 grams.The timing of this execution is slightly different from that in Figure 4.

2, il 101 X I X 2 X 5 X
4 Jump command Y+Y2Y5Y4 Z+
When the jump conditions of Z2Z3Z4X are met, the jump destination addresses Y+-4 and Z+-4 are transferred to each PB2. Transfer to FBI, transfer to 4i/CPB2f PC2, FBI f PC+ and complete, but do not jump if not established.

X+-4 is 0010f over 7 o -0VFi 1
jump instruction when detected, 0100 is when register A is 0, 1000 is unconditional, 1010 fii
This is a jump instruction when OVF register A is not 0.

First, at time TI+T2, an address in the ROM is designated by the PC, and at time T1, code 0101 is output to the data code bus, and at time T2, it is latched into register C by opening/closing SW6 and SW9. Same (at T2, continuation (XI~4) is output to the bus bar, and at T3, register D[
Being latte. Now, if x1~4=0100, in time T4, the code of 0101.0100 will be
, L. Is it a jump instruction and determines the contents of register A? d W&, continued (at time Ts to T+o, first determine whether the contents of register A are zero or not, and if not zero, PCjf → -2 and exit the jump instruction. If it is zero, set PC to +1 Then, by opening and closing the following codes Y1a, Z+ to a fBWq, BWx, and BW+s in the ROM, each is stored in PB2.FBI.Fourth, it is transferred to PB2→PO2, FBI→PO+.This causes the jump destination address to be set. PC- is 311 and I am the first-order T.
In the cycle 1 to Too, a new address to jump to is specified in the ROM and the jump is completed.

3, 0110 1000 Transfer command (1) This 1j
Store the data at the address set in PB in register A (hereinafter referred to as load). ft of TI+T2, output 1, J in pc
An address in tOM is specified, and at time T1, code 01
10 is output to the data code bus rtc, and SW6 is output at T2.
, 9 is latched by the register C. same(
Continuation at T2 (1000 is output to the bus bar, SW is output at T5
It is latched into register D by opening and closing of 7 and 9. At T4, the codes in registers O and D are decoded, and then from T5 to To.

At the time of , the code of PB is output to the address code mother #+;+, and is specified by this station? 'LRAM, output device, key display input/output The contents of one of the scattered key registers are output to the data code bus, and SW? , SW2
By opening and closing, register A [opens].

The following will be a brief description of the same movement.

In the following procedure for controlling copying by making full use of the instruction codes listed in Table 5 and above, it is necessary to easily set up the input/output device i and the memory itself.
The code to do this is as follows. This means that the X-code is not limited.

In other words, the top four of the 12 address code bus lines are the lines for selecting memory, etc., and each memory and input/output device has 1r'! 4 has a circuit known per se. The other eight lines are lines for specifying the partial address of the further tic memory, and are for each memo. It has a circuit known per se for decoding. Since each input/output section in the input/output device corresponds to each digit of the data 41) it in this example, no special designation circuit is required.

Next, representative steps of the copying cycle shown in FIG. 9 will be specifically explained. Without stirring, repeat step 1 and step 2 first.
This will be explained using the instruction flow and code shown in Figure 0. In the instruction flow, after step 0 of the key entry mentioned above,
In step 1-1, address (1) of the r input device (0
110) to register PB5? Next step 1
-2, the input device (1
) is transferred to register A, and in step 1-3 it is determined whether the contents of register A are 0 or not, and if not, the address (0110) of input device d(1) is set to PB5 again.
The content is transferred and determined repeatedly. However, when the contents of the register A are O, that is, the paper, toner, etc. conditions of the input device fα(1) are satisfied, the process moves to step 2. In step 2-1, register P for address (0010) of output device (1)
R5, and in step 2-2, 0001 is placed in register A in order from the lower digit of the code, and in step 2-3, the contents of register A are transferred to the output device (1) specified by register PB3. 00 of r output device (1)
01 K The corresponding 1θ4 drum motor v15r is driven.

This procedure will be explained in detail with reference to the circuit example shown in FIG. The execution procedure of steps 1 and 2 is recorded in advance from address 1 to number 8 l1l1 in the ROM based on the above-mentioned table 3.

5TIP ROM number 11j (ROM code)”1-
1 [10000000000001000110 human power + i#f1) address code 11000 0000
0001 0000 00001-2 1
# 0010 0110 10001-3 1
1 0011 0101 1100 Jump condition register A, ='0 1 1 0100 00000000 Jump destination ROM address 2-1 # I 010
1 0100 0010 Output device #(1) address code # I 0110 0000 00 mouth 0
2-2 # # 0111 0111
1000 Code to be transferred to register A 2-3 # I 1000110 100
0 After the contents of the above ROM address 00 are read, the motor v
Until 1 is activated, the time chart in Figure 4, No. 3 and 1.
This circuit will be explained below.

Without calling, the power is turned on and the register is cleared by the company cow, so as mentioned above, the time r of T I + T 2 in Figure 4.
i place code ff1-&! 1112 KPC contents non
o.

The codes noon and oooo are output and address 0 of the ROM can be specified. As a result, at time T1, the upper code 0100 of address 0 is output to the four data code bus lines, and by opening/closing SW9 and BW6, u? of T2 is output. f
When it becomes in, it is launched into register C. Immediately, this is decoded by the instruction 1 Zen reader OT, and then the data code busbars (PBs, FBs, FBs, etc.)
? , generates a control signal α such that 5 is sent to the FBI. Therefore, at time T2, the lower code 0110 of the ROM address 0 is output to the bus line, and immediately the above α
By opening and closing SW9, 5WI5, it is latched to PB5. Next, set the register PC'ji-+1 to the next R
Output the code of address OM 1 to the front Re bus in the order of upper 0000 and lower 0000, and similarly output it to SW using α above.
9. FB2. by opening and closing the SW eye. Execution f is completed by the time of Too by PB+heratsu.

(When TI is 1111, add +1 to PC and ROM
Specify address 2, and at T1, the output T2 of the upper A1 gamma code 0110 latches this into the register CVC, and the output of the lower code 1000, and at T3, it is latched into the register D. It is decoded at T4, and from T5 to T100, the code of FB, that is, 011000000000 is output to the f address code bus line, and the input device (1) is all specified, and the data, including the signals input to its 4 lines, are sent in parallel.・It is output to the code bus and latched by register A by opening and closing SW9 and SW2. (Refer to Figure 14) This input device (1) has four input lines.As shown in Table 3, the remaining paper signal (1-absent, Signal (1-absent, 〇-present), fusing heater] Dead IE
Temperature detection signal (1=NG, O=OK) and stop command (1-present, 0=absent) are included, so all inputs are 0.
It means that it is okay to enter the level copy cycle. However, if you specify the ROM5 address by DOf+1 at T11, the upper 0101 will be the lower 110 of register C1.
A zero is latched into register D and decoded as described above. It is determined that this is a conditional jump instruction, and the register A is set to 0, and then PC'li-+1 is added to the code at ROM address 4, upper 0000, lower nooo.
'(i-sequentially, output to the data code bus as described above, and transfer the upper 0000 to FB2 and the lower 0000 to PBl. Therefore, FB: +-)"1XXXX 0
It becomes 000 0000. And then PB2 minute PC! 2
．． Transfer FBI to PCI and complete execution, so PC
The code is 0000 00000000K. Therefore, at time T1, the ROM and Otf address codes appear again on the address code bus line, and the contents of the ROM addresses O to 6 are repeated.

However, if register A=[], that is, if all the state detection signals are OK, then pc is increased by +2. Therefore, the jump command is exited, and the address code bus KR at the next time T1.
Address OM5 is designated.

Similarly to the above, the address code of the output device jl) is set in the FB using the code at address 5.6 in the ROM. So(7,
When PC is further increased by 1, the ROM7 address is specified at the next time T1, and at T2, the upper code 0111 is latched into register C, decoded, and the lower 1060 is sent to SW9.
, 8W2 opens and closes to latch the register A and finish.

Furthermore, PO is incremented by 1, the next T I [ROMf1 address is specified, and 72f the upper 1 d'OO of the contents of this address is latched to the lower 1ooMr-register D using registers O and T3 and decoded.

Then, the content 1000 of register A is output to the data code bus by opening/closing sw+ and swa, and at the same time, the FB
Code 0010oooo ooo
o is output to the address code bus line, the output device (1) is specified, and the code of the data code bus line is launched to the 44: output line of the output device operator (1). Therefore, the outputs are 1θ1=0, 1θ2=0, 1θ5=0, 1θ4=1
become. l 1θ4 is toram.

Since the motor Vl (first speed If) is fully connected to the interface circuit shown in FIGS. 3-4, the drum motor starts at the first speed.

Next, the drum home position confirmation procedure in step 6 in FIG. 9 will be explained in detail with reference to the command flow in FIG. 11. After completing the double-acting clutch off in step 5, the address (0111) of the input device (2) is set in register PB3 in step 6-1, and the address (0111) of the input device (2) is set in register PB5 in step 6-2. The contents of the input device (1) are transferred to the l/ register, and in step 6-5, the contents of the register are rotated clockwise, and as a result of the clockwise rotation in step 6-4, register A; - It is determined whether or not f has been performed. If not, step 6-1.6-2 of reading all input again and overflow determination step 6-3f are repeated.

When an overflow of register A is detected in step 6-4, that is, when Baum level fif is detected, the process proceeds to step 7. -F Step 6-1~
Continuing the code in Table 1 that executes steps up to 6-4 from step 5 (
l(For example, write 1~ to the number 1 of OM.

5TKP ROM address ROM':y-doOOO 6-+ 10000100 [11100001011
10011101111000000 6-201201101000 6-301311110111 01500010000 That is, 10 of 1'10M specified following step 5
The upper code 0000 from the address is output to the data code bus line and latched into register C as described above. Immediately, the contents of register C are decoded by the CPU p, which generates a control signal α which causes the next code appearing on the data code bus to be stored in FB. Therefore, when the lower code 0111 at address 10 is output to the data bus at the next clock, SW9 and 15 will close 11th block with the α signal.
RB5 will be crushed.

Below; until the end of execution at address 10M12, the same process as the execution up to address 02 in the previous example is carried out, that is, code 011 of FB
1 0000 Output 0000 to the address code bus, specify the input device (2), and output the signals input to the four wires of the input device (2), for example, 0000 in parallel to the data code bus, SW9.2 Opening/closing register A [this is latched. This input device (2) [is the screen home position detection signal shown in Table 2 (1: present, 0: absent),
The optical system home position detection signal (1: present, 0: absent) and the first and second clock pulse detection signals (1: present, 0: absent) are input (the above example indicates that neither example is detected). show).

Next, when the ROM15i location is specified, the top 11 contents of the ROM15i location are specified.
10 is latched from the lower 0111 of register C1 to register D like a turning water and is decoded by the CPU. This is determined to be a clockwise rotation command, and the series 4-digit contents of register A are shifted to the right. Furthermore, register A 4' (haoo
Since no is stored, even if shifted, register A
There will be no overflow.

After executing the next VC shift, when address pc all + 1 C T7 ROM 14 is specified, upper 0101 is assigned to register C1 lower jr' (
, 0010 is stored and decoded in register D.

This is judged to be a conditional jump instruction, and the previous register A is
Since the overflow detector OVF due to the right shift is not 1 and the original screen home position is detected, the PC is further increased by 1 and the ROM address 15 is designated. The contents of address 110M15, oooi oooo, are sequentially output to the data code bus line, transferred to the above 0001 all PB2 and lower 0000 all PB1, and finally the PB is transferred to the PC to complete this step, and the ROM10 a location designation code is output again. is stored. At the next clock (T1), the contents of this PC are output and the ROM address 13 is repeated from ROM 10$.

However, an overflow was detected in step 6-4, that is, in step 6-2, register A was set to 01101 (homey) 11.
When 1 is passed to ◯VF' from the right 7th foot VC in step 6-3, the signal α is decoded and the signal α is generated to set the PC to +2. Therefore, ROM for Jean 1 @
Pass through the pond and go to step 7 ROM address code fp
Store in a.

Next, the procedure for counting the copy clock and turning on the primary charger in step 8 of FIG. 49 will be explained in detail using the instruction flow shown in FIG. Each Stella2 in the instruction flow corresponds to each ROM part as in the previous example. First step 8-1
In step 7, the time from driving the drum motor to turning on the primary charger in step 7, that is, the predetermined count value 60 of the copy clock is stored in the ROM No. N 11ii (for example, 12020 address code ?PB).

The code written in ROM K (addresses 20 to 49) will be explained below. When address 20 is specified, 0100,0000 is sequentially output to the data bus line, and the upper 010
0 is stored in register C and read by the CPU, lower 00
00 is stored in FB5. Next is PO? +1 and ROλ
When address 21 is specified, its contents are (1100ooo
o) The data is output to the bus line and sent to FB2 in the same way as the previous station.
, stored in PBl.

Designation code of the ROM and number 120 I in the ROM
A tl designation code is stored. Step 8-2: When the 22nd address of the ROM is specified by adding 1 to all DCs, its contents are output to the data mother@, the upper 1101 is stored in the register C1, the lower 000o is stored in the register D, and the solution α is calculated by the CPU. The above code of FB is address code mother 4i! Output to. Therefore, specify the ROM corresponding to h2 and its 120# address, and output the code of the content 6° (the above count (corresponding to +#) at address 120 to the data code H[. Then, the 8-bit count code 174 Transfer the bits to register A and the lower 4 bits to register B and store them.

After storing, the ROM25 address is designated by CP2+1 and the process proceeds to step 8-3. That is, the contents of this address are sequentially output to the data code bus line, stored in the register, decoded, generates the control 41 signal α, and transferred to the register A (4fpa2).Then, proceed to step 8-4.Specify the ROM 24 address. Then, the contents of this address are sequentially output to the data code bus line and resolved, and as a result, the contents written in register B are transferred to register A, and in the next step 8-5, the specified contents are stored in the fcROM.
This is PB by ty4Mf at the instruction address of pond 25.
Transfer to l. In step 8-6, the instruction code at address 26 in the 77 ROM is decoded, and the inner world of the upper IGs P+33, 2, and 1 is stored in RAM K via the data motherboard a, and 1tIl is temporarily stored when the charger starts operating. When the PC is +1 and the process proceeds to the next step 8-7, the ROM27 address is specified, and the contents are output to the data code bus line as in the previous example.By decoding the upper 0100, the lower Q1?1 (
The code corresponding to the input wave fill(2)) is stored in FB3.

In step 8-8, the input contents of the input device (2) are transferred to register A, and in the next step, the contents in the register are rotated counterclockwise. That is, the contents of the input device (2) are shifted to the left digit, different from the previous example. This is because the copy clock detection signal that rotates counterclockwise in step 8-10 is located at the second left digit, so the presence or absence of 1 at this position is detected. Proceed to step 8-11 and RO[2脣111! is specified, and the presence or absence of overflow is determined as in the previous example.

When the OVF detects 1f by two left shifts, it jumps to step 7, which is specified by the ROM memory No. 33, and repeats the same steps.

ty'+I [In order to detect the copy clock pulse hh at the rising edge of the copy clock signal, first detect the level 0 of the copy clock pulse 1b-f. It is. Therefore step 8-
Numerals 12 to 8-16 are processors for detecting level 1 of the copy clock pulse. This process is carried out with the same 70- and Ro)t codes as in the previous example. Step-8
When the OVF detects 1 at -16, the process advances to step 8-17, and the contents stored in the RAM at step 8-6 are transferred again to the FBs 3 and 2.1. Then, in step 8-18, FB is decremented by 1, and in step 8-19, PB is subtracted again.
is stored in RAM. FB2 in step 8-20? (The contents of FB are not erased by executing step 8-19.) The contents of register A are transferred to register A, and in step 8-21, the contents of register A are checked to see if the upper part of the numerical code that was not subtracted is 0 or not. Since it is not register A11O, it is RO.
The program moves to i'17jROM27 specified by address M45, that is, steps 6-7, and executes the steps up to now again. Therefore, each time the copy clock rises, the RAIi K stores 11fc-FZ value ff-1, which is VC.
Eventually, the steps up to now are repeated a predetermined number of times, and the upper digits of the numerical code up to 0 are counted as tithes. 1- When register A becomes 0, the process proceeds to step 8-22, and the contents of FBI having the lower order of the uncounted number + 1i code are transferred to register A, and in step 8-23, it is determined whether register A is 0 or not. Determine everything. When register A is 0, it is specified at ROM address 49.
The program jumps again to step 8-7 at address OM27 and executes the steps up to now again until the lower digit becomes 0. When the register A reaches 0, the counting step of the copy clock is completed, and the operation sequence of the copying machine advances to the next step 9, and the -VL to the wide charger is turned on.

Furthermore, since the synchronization of the clock pulse dedicated to the CPU is 1μeeQ, the time required to execute the above 14-day cycle of il-1 =
Therefore, it is 300μ at most.

Kone is a friend of Copy Clock Pulse, as mentioned above, about 8
Since it is msθC, it does not affect tta.

FIG. 14 shows a schematic circuit example of the control section t4 which decodes all the instruction codes and data codes of the ROM and outputs the control 1111 signal α in the control procedure as described above. This is the first
Step f in FIG. 0 has been functionally explained, and the other steps can be configured in a similar manner.

[Brief explanation of drawings]

Fig. 1 is a sectional view of a retention copying machine using the control system of the present invention, Fig. 2 is a sequence time chart of the retention copying machine, Fig. 3, and Figs. The control circuit example according to the invention, Figure @4, is the ROM number tlh? 5 is an example of the circuit of the input/output section, FIG. 6 is another example, FIG. 7 is a schematic flowchart of the copying cycle according to FIG. 5, and FIG.
The key entry flowchart in FIG. 9 is shown in FIG. Flowchart of sequence control in Fig. 7, 1st
Figure 0 is an example of the instruction flow to lr at input judgment drive start in Figure 9, Figure @11 is an example of the instruction flow in home position detection, and Figure 12 is the instruction flow in copy clock counting. example. FIG. 13 is an example of writing the ROM code required in FIG. 12, and FIG. 14 is a schematic circuit diagram of the control section.
ROM is a read-only memory that stores the copy sequence as an instruction code, RAM i is a write/read memory that stores the set number of copies, etc., 1 is a device for inputting data such as the copy status, an output device compatible with oFi copy processing equipment, cp
This is a central processing unit that reads and discriminates U light data and commands and outputs required signal data. Applicant Canon Co., Ltd. Figure 10 Procedural Amendment (Method) September 27, 1980 Commissioner of the Patent Office Kazuo Wakasugi 1 Indication of the Case 1981 Patent Application No. 56204 2 Name of the Invention Image Forming Device 3, Amendment Relationship with the case of a person who does
August 60, 2015 (shipping date) 6. Engraving of the specification to be amended and the specification of the contents of the amendment (no change in content) Procedures Written amendment (voluntary) R/Z, 1982? Meto + MLi"k Official Sai1 Kazuo Sugi Tono 1, 11 I'l's Expression J < 11t (W58 41Fa1 Application No. 56204
No. 2, Name of the invention Image forming device 3, Relationship with the amended person case 41f Applicant Address 3-30-2 Shimomaruko, Ota-ku, Tokyo Name (+00) Canon Co., Ltd. Representative Ryu Kaku 3rd Department 4th Agent Place of residence: 3-30-25 Domaruko, Ota-ku, Tokyo 146, Japan Description subject to amendment 6 Contents of amendment (1) The scope of claims column of the specification will be corrected as shown in the attached sheet. (2) Correct "several copies J" in line 18 of page tJ'fJ1 to "seven copies". (3) Add the following after the 20th line of the first page. [That is, the first processing means for forming a latent image on the rotating body (
A second processing means (a second processing means (second processing means) for repeatedly forming a plurality of clear images from the same latent image of the quadrupling body shown in FIG. The first processing means has a reciprocating means (52 to 54 in FIG. 1) for exposure scanning, and before the operation of the reciprocating means is completed, 2.
Claims: A first processing means for forming a latent image on a rotating body; and a second processing means for repeatedly forming a plurality of visible images on a transfer material from the same latent image on the rotary body 1. The first processing means has a reciprocating means for exposure scanning, and the first processing means has a reciprocating means for exposure scanning.
and a control means for starting at least one operation of the Jr2 processing means. 596-

Claims (1)

[Claims] comprising a first processing means for forming a latent image on the rotating body, and a second processing means for repeatedly forming a plurality of visible images on the transfer material from the same latent image on the rotating body, wc1 above
An image forming apparatus (f) having a reciprocating means for optical scanning of the processing means (Fia) and a stopper (11) means for starting at least one operation of the second processing means (1) before the operation is completed.