JPS5940658A - Controlling method of copying machine or the like - Google Patents

Abstract

PURPOSE:To control a copying machine, etc., with simple constitution while changing sequences easily, by discriminating an input signal necessary for copying connected to a generation source with bit position and outputting a control signal based upon a time elapse. CONSTITUTION:Multibit signals connected to various detectors such as an FF stored with data on the depression of a key stop at a bit position, paper remain amount detector, and generation sources for such as a home position detection part, etc., for a screen drum and an optical system are inputted from each input device consisting of a latch circuit, control circuit (f), etc. This input is judged by a CPU to read a program out of an ROM, and the incorporated counter in the CPU which counts elapsed time to output a sequence control output is controlled. Therefore, the constitution which eliminates the need for an input means for the number of various condition signals controls the copying machine, etc., with an easy sequence change.

Description

[Detailed description of the invention]

The present invention relates to a method of controlling a copying machine, a recording device, etc. Conventionally, recording control of copying machines and the like has been performed by outputting control signals based on various condition signals necessary for recording. In this case, input means equal to the number of various condition signals are required, and as the number of various condition signals increases, the control device becomes complicated.゛1 The present invention eliminates such drawbacks - ゛'□Furthermore, by using this example, it becomes possible to program the sequence of a copying machine CP recording device in a time-series f program, This has the feature of making changing the sequence much easier. Furthermore, this example has the feature that the high-life integration of the circuit is reduced to 1, and the number of parts can be reduced to a large number of parts. Furthermore, according to this example, by using the same circuit and changing only the program, it is possible to perform sequence control of different copying machines. Furthermore, in this example, since driving a device with a constant PJr cannot be executed unless the process leading to driving the device is completed, there is a feature that no poisonous operation will occur due to an input error signal. Furthermore, this example θ program is executed at the drum home position IM#
Since the actual progress of the recovery process is monitored at a predetermined point in time, it has the feature that no errors occur in sequence control. Hereinafter, a primary latent image is formed from the original, and a secondary latent image is repeatedly formed from this primary image.1. ．． Lithia'/E7 to obtain a number of copies by developing and transferring the secondary latent image.
The present invention will be explained using an example in which a copying machine is sequentially controlled by a 4-bit parallel processing microcomputer. First, we can roughly understand the recovery process using the cross-section of the camera in Figure 1 and the time chart in Figure 2.
ilI! do. 61ilj key operation panel, 51 original document stand, 52 low light lamp, 53, 54, 56, 57゜5
8Vi reflective mirror, 55 it/z system, lii photosensitive drum, 3 digits httpα/f 14 digits primary charger, 6 is secondary remover, 7 Vj full irradiation lamp, 13 digit modulation pre-bander,
11F'i modulation charger, 8 insulated drum, 24Vi developer, 33 paper feed roller, 34 is timing roller, 36
is a transfer charger, 73 separation claws, 70°72 is a paper detector,
45 pieces of fixing roller, 47 pieces of output tray, 31 pieces of transfer paper,
It has a 14Vi blower and an 18-piece heater, and the photosensitive drum L is either transparent from the surface or has 6 net-like yellow-sensitive drums that have wire scraps, a light guide 11L layer, and a conductive layer (example O is the 1930 published patent No. 19).
(described in detail in Japanese Patent No. 455) around the drum, and the next-order electric appliances are temporally and spatially divided into front and rear parts. The driving operation of the photographic device is performed by a command from the Vi operating panel 61. The operation consists of 1161, two displays 62, 63, two pilot lamps 65, 66 and a keyboard 64. The numerical keys "0" to "9-1" on the keypad P64 are used to set the number of copies, and the contents of the keys pressed in sequence are entered on the display 62. The "ω" key means "infinite number of times" and lights up the pilot lamp 65 of "ωJ." Next, the key [R-1 (几ETEN1'ION) is pressed repeatedly by one electrostatic image formed on the screen. This is used when setting the number of copies to be made, and the number of entries is displayed from the following numeric keys or 4 entries of the ``1ω'' key. The contents are displayed on display 63 or Pyrontra/Pro 6
will be displayed. The f-COJ r CRj key is used to correct each set number. "8INGj is used to start copying one page, VC1r MULTJ is used to start multiple copies using the numerical keys, and rsTolJ is used to stop copying before the set number of copies (/'J) is completed. Next, the time chart in Figure 2 is used to First, when the power switch is turned on, the screen heater 18, fixing roller heater, etc. are turned on, and after a waiting time, it enters the preparation state.Then, the number of copies is set on the operation panel 61, and then the rsIN (to start copying) is pressed. jl straddle rl (When the ULTj key is pressed, il rotates to the screen p ram motor. At this time, the reciprocating clutch of the optical system is activated, which allows the document illumination lamp 52 and lamp reflector to be installed integrally. The first reflecting mirror 53//i moves at a speed v1 that is equal to the circumferential speed of the screen drum 1.Therefore, as will be described later, the optical system home position is set and the exposure process begins.Irradiation of the document illumination lamp The motor for the middle screen/drum rotates with
! When the X-edge drum motors M1/ are turned on at the same time, the speed of both drums instantly increases by about twice [V2rr]. While the screen/r ram motor 41 is rotating, the front irradiation lamp ``3'' and the entire surface irradiation lamp 7 are turned on to perform exposure and illuminate the document. The optical cooling fan is driven. Then, along with the operation of the charger 4 and the secondary charge remover 6, the rC on the screen is formed as described above. Also, when the copy start key is activated, powder image transfer charger 36;
The paper separation charger 37, the insulated drum static eliminator 50, and the paper separation suction/fan are turned off and turned off at the end of the copying operation. However, since the rotational speed of the insulating drum is slow at the circumferential speed of the above-mentioned 36°37.50ij Niscreen drum motor, the potential is lowered to prevent excess charge from being charged on the insulating drum. Next, after the next large image is formed, the screen drum motor is turned off and the insulating drum motor is turned on, thereby starting copying operations such as modulation, development, paper transfer, and separation. After modulation, the first copy of f'i is completed when the screen/IS ram rotates three times, but after that, one copy is completed every time the screen/IS ram rotates once. First, the rotation of the drum is switched to the insulated drum motor M1/, and at the same time, the pre-modulation charger 13 and the conveyor belt 3B (first
Figure) The conveyor roller clutch for transmitting the force of the Heckler 2/G motor is turned on. When the rotation is advanced
The paper feed roller clutch CL3 for feeding one sheet of paper on the paper feed table is turned on at 241° when the Mi Teishoki 11 is off L, and the screen drum starts its second rotation cycle after the modulation starts. The paper feed roller/clutch CL3 is turned off at the home position, and the timing roller/clutch CL4, which aligns the leading edge of the fed paper with the leading edge of the developed image on the insulating drum, moves to 4o0. The developing motor is turned on at 160'. If the number of copies is 1, at position 228, change 1111j Teidenki 31
1 is turned off, but in this case there are 2 cards, so it is not turned off. Proceeding further, the paper feed roller/clutch CL3 is turned on at 241° to feed the second sheet of paper. At 36o0, turn off the first timing roller clutch CL4. Enter the third rotation cycle, turn off the paper feed low 2nd clutch and the 1st timing roller clutch at the home position, and turn off the 1st timing roller clutch.
Apply the brake to the timing roller with o. At 16o0, turn on the second timing roller/clutch CL4. At 228°, the modulation band 11 unit 311f is turned off. If,
If one copy is to be made, the developing motor M2 and the toner bridge prevention motor are turned off at 50. At 360, turn off the timing roller clutch. When copying two sheets, turn off the developing motor M2 and the toner bridge prevention motor at 50 of the fourth rotation cycle of Vi, and turn off the motor at 33 o.
At ', the insulated drum motor M1' and the conveyance roller clutch are turned off to complete the two-sheet retention cycle. The separation pawl solenoid SLI, which separates the paper from the insulating drum, operates between 276 and 316 during the second and subsequent cycles. Figure 3 shows the circuit configuration that controls the operation of each device in the copying machine to execute the 7'' process described above.ROM
A read-only memory is shown in detail in FIG. 3-1, from which the sequence contents of the TJ copying machine can be stored in a pre-ordered manner at each address and retrieved each time an address is set. In other words, the control contents (including not only the operating output of the device but also the control contents of other circuits) are written in binary code r of the 8b in order from address 0 to the required final address, which is set in advance in a known matrix circuit with a code. remember. ■1~2
t- is an input device that stores the copy status.For details, refer to fa3.
This is a device for outputting signals for controlling the operation of the 001 to 4Fi copying machines shown in Fig. 4.The details are shown in Fig. 3-3. ItAM is a read/write memory that stores the number of copies and temporary control signals during process control. A known memory for storing information is shown in Figure 3-2 in detail, and consists of a plurality of sets of flip-flops, and any set is selected by an address designation signal. A plurality of 7-lip/70-lip data are written therein and read out. CPUVi top memory,
One or more registers FB for specifying addresses of input/output devices
, PC, and one or more registers A for primary storage,
B, C, D. It has a control unit CT that has addition/subtraction logical operation functions to decode data input from the data signal processor and process the data (7,
The image is formed by a plurality of lines with the external circuit. Roughly at the crotch, there is a ROM in which the sequence is programmed from the CPU.
The contents of the specified address are the data signal &
! 86 [7, CP II VCM including 1, C
P U tri Kot1wojW me, L,, Mvf
. According to the contents of
Sometimes data in the CPU is stored at a specified address in Ij A V, or at a specified address in Ij A M.
Also, input address data into cpv, and sometimes
The data in P II can be output to the output signal line 88 of the input/output section, or the contents on the input/output section's manual signal line 89 can be output to the output signal line 89 of the input/output section.
Input into tJ1. , fc to perform sequence control.
I will clarify. First, please refer to the clock time chart in Figure 4 for the basic timing for sequence program processing (explained in ~). Individual commands of the program are written on 8 main lines in the ROM VC.

[Pre-M) It is encoded and stored, and the n codes from the specified bus address are decoded by an address decoder, and one of the 211 codes is selected. It is designed to be output as follows. The address at which the instruction in the ROM and RCM is stored is designated by the ROM address designating register (PC) K. This register (PC) has a function of incrementing it by +1 using a control signal αl, and in response to this K, zologram-formed instructions are output one after another. This register PC is jJI at a predetermined time.
K multiplexer A to It OM is powered by CVC. It OM outputs the instruction code to 8 lines, but since the data code P bus 86Vi has 4 lines, it is time-divided and output to the data code bus in two parts. The four instruction codes output in two batches are latched into register C1D by the opening and closing of SW9, SW6 and SW7 in response to the 2.3 clock signal α, and the contents are decoded by the instruction decoder. A control signal α is generated for processing according to the instruction contents. In short, the designation of the address where the program is stored in four basic clock cycles and the decoding of the instruction code stored at that address are completed (~, during the following six clock cycles, the contents of the above instruction are Then, execute the programmed command at the same address again at the same time interval. Therefore,
It takes time equivalent to Kidto clocks to execute one execution instruction (one step) in a series of programmed sequences. 20 for a 2 word command
clocks. Note that the registers A and B are used for calculations, and each switch SW is a date circuit controlled by a control signal α, which is a well-known circuit for detecting an overflow of the ovpi register A. The control unit CT decodes registers C and D and reads register A. This is a circuit for calculating B and outputting a control signal α, and its functions are schematically shown in FIG. 14 (described later). Next, input/output signals will be explained. The correspondence between each latch (eg, flip or clock) of the output device of the copying machine and the output device is as shown below. 1st expression 101 Front irradiation lamp power 1θ 21st charger (front) Device ]θ3 Optical system forward clutch (1) lθ4 Drum motor (1st speed #) output 2f
J1 Primary charging "a (performance) Force 202 Harakun Tsuyuki lamp device 2θ3 Secondary static eliminator (2) 204 Optical system sliding clutch output 3θ1 Image-based transfer Teidenki force 3θ2 Current iron motor device 3θ3 Drum motor (second speed) )(3) 3θ
4 Screen bias charge leakage 4 (Pl Supply I-L clutch force 4θ2 Timing roller clutch device g7 4&3 Separation solenoid (4) 4&4 Timing roller -I-L-
Additionally, the correspondence between the status signals of the present copying machine and each latch input line of the input device is as follows. Specific examples of these input/output circuits are shown in FIGS. 5 and 6. Fig. 5 shows the case where each [Δ] corresponds to a 4-bit output line, and Fig. 6
A converter is provided for i4 or higher. Table 2 First speed 1 at which the drum motor of the copying machine shown in Figure 1 rotates
d l 2 (l mtn / sec, the second speed is 360g+x/see.Screen・

[It has two built-in internal generators (this can be anything, including an astable multi-vibrator) that generates one pulse per 1'IC rotation angle of the S ram. Since the diameter of the screen drum is 11 Qmψ, the clock pulse is 1.
The clock period of clock pulse 2 is approximately 8 m/sec, and similarly the clock period of clock pulse 2 is 266 m/sec. These clock pulses can be generated by optically detecting the holes 60 in the rotating plate 56, which rotates at several times the speed of the insulating drum. When the status signal is at the "1" level, it is either "None" or N.
G”, and the 0” level means “Yes” or G O(l D
The control circuit shown in FIG. 3-2 is a known r-t circuit in which a 4-bit signal is output with the bladder release control signal 2, and a known dart circuit in which a 4-bit signal is input in the write control signal 2. The control circuits shown in FIGS. 3-3 and 3-4 each include a known r-) circuit in which a data code is output using the output control signal 2 and the selection signal of the output device 0; It consists of a known gate circuit in which the data code P receives the input control 4F No. 2 and the selection signal of the input device 2.Next, Figure 7 shows the general flow of the program control method. After turning on the power, a key entry cycle is executed to set the number of copies and start copying, and then it goes to standstill 1 where nothing is done, and the previous 0 pi''! Loop the cycle (2 and enter the waiting state YC of Keye/l.Lee. The operator makes the desired number of copies/Torishi,)l! When the copy start key is pressed, the copy cycle begins to run. Determine whether each close-up cycle is in end mode (i.e., when the desired number of close-up shots have been completed, when the stop command has been issued, when the L-day has run out, when the paper has run out, etc.). Then, if it is not the end mode, the copy cycle is looped. It is in the end mode, stops the printing operation, selects the first desired copy, and enters the copy start key cycle yc y! 7. Wait. In addition to the above @, since the copy operation is processed sequentially, setting the number of copies during close-up → Noikle and entering the key to start copying are prohibited, and there are some percentage problems such as the remote cycle not starting during key entry. have (Key Eft Recycle) The key entries are numeric keys from 00 to 9 to set the desired number of copies, the °'Multi" key to start copying, and the 1 Single" key to start copying one copy. This is done by using the 6 stop key to issue a stop command and the "clear" key to stop the set number of sheets. This will be explained below with reference to 70- in FIG. You can set up to 2 digits (i.e. 99 copies) for the number of copies.The first digit is the address J(, A
Store in M2 incense area. After the Xeonzo thrower, display the data of RAMI and 2 Kaji on the display with 5TEPO-1, and S'l'
Wait for a key to be pressed on the EPO-2. Therefore, the power-on state can be confirmed by the numerical display. When a key is pressed, S'l'EPO-3 determines whether it is a numeric key or another key, executes the numeric key sequence S'l"EPO-4, 0-5, and displays the newly pressed numeric value. Store in RAM t address, 5T
Return to EPO-1vc and display this. Therefore, it is convenient to be able to display numerical settings starting from the lower digits. If Si'EPO-3 is used for keys other than numeric keys, proceed to Si'EPO-6 and beyond. If the ``clear'' key is S'l'E]'(,+
Clear the RAM with -7, return to 81'EPC') -1, and display "00". If it is Maruna key, go to 1st column to print, if it is °'shi/group' key, it is 5 TEPL.
) At -9, ``l'' is entered at address ftAM3 and the process proceeds to the nuclear transcription cycle. 14 A M Address 3 is for determining whether it is in the end mode or not, and it is 0゛' and the next 43
Proceed to 1-photo twist and end mode when it is l. , this ROM31? it:j 1? , II! This is to execute the photo cycle and then determine whether or not it is in the end mode. (Refer to FIG. 8) (Copying Cycle) Following the key/process/tree cycle described above, the first copying cycle begins to execute the step shown in the flowchart of FIG. 9 below. First, in 5TEP 1, check whether there is paper or developer and whether rMU of the fixing heater is D[i1. ,
If NO, I will wait with OKK. If the above conditions are OK, proceed to 8'l'EP2 and start the drum motor (■1) that rotates at the first speed.
i'EP 1 and 2 will be explained in detail later. Next, the optical system is at home position @ VC at 8'l'El) 3
Check if it is in the home position [7] If it is not in the home position, turn on the double-acting clutch and mechanically connect the drum motor so that the optical system moves to the left when looking from the front of the main unit.
It is moved to the home position. When the home position is reached, the front six pixels are turned off at S'l'EP5 to stop the optical system.2 Therefore, scanning can be started from the 1C fixed position. Next, the home position of the screen-drum, which is mechanically connected to the drum motor and is already rotating synchronously, is confirmed in S'l'EP6, and if it is not at the home position tti, the rotating screen-drum Wait until the drum reaches its home position. Details Y'i will be described later (
Figure 11). When the home position is reached, the optical system is already waiting at the home position, so 8 TEP
After 7, the copy creation cycle begins. First, turn on/off the pre-irradiation lamp, primary charger, and f@b0 lamp. The drum motor is already rotating at this time, but after turning off the second gear drum motor in S'l''EP 72, it returns to Si'EP 7, so at this time Vi must be switched to the first speed, so at S'I'EP 7 the first 5th medium drum.
Start the motor again. Slurry/11 If we take 10 sheets for one latent image formed on the drum, for a total of 55 sheets, we have to make the latent image 6 times.
The number of repetitions must be stored in a part of the memory in advance. 0 Therefore, the copy cycle starts S'J”h
:P 7 stores [2] (in this case, 10) at address 4 in RAM as described above. Next, enter S'rEP BK and count by 1 the number of clock pulses that occur every 1'M rotation of the screen drum rotating at the first speed, and when this reaches 60 (that is, the screen drum is 60 'When it rotates 7)
Turn on the primary charger (rear) with Sl"El' 9 and set L7. Then, when CPl becomes 105 in the same way, S
Turn on the secondary static eliminator with 'l'EP 11, then C
When Pl is 12, turn on/off the forward clutch to move the optical system in the right direction VC when looking from the front of the main body (5TEP12.1
3). Thereafter, wait for the screen/drum home position to appear again (5TEP 14). That is, 8'l'EP
Between 7 and 14, if the frequency of clock pulse 1 is not synchronized with the rotation of the screen drum, or if there is a mistake in counting, the system continues to operate depending only on the counting of clock pulses. When controlling 5TEP 7~
Since mistakes that occur during one rotation of the screen drum up to 14 are accumulated, this can be prevented by resetting the count of Si'BP 14. Similarly S'l'EP 35, 5TEP 57, 5T
EP 61 is also included for the same reason. 5TEP 15 and subsequent steps are based on the same concept as above, so the details will be omitted. In other words, in this device, the rotation angle of one ram of the screen (i.e., the number of pulses) from one change point to the other in the sequence is stored in advance in the memory, and when the number of pulses is reached, the control device is turned on/off. , turn it off. In other words, if you count 48 pulses from the drum home position, the front 1
The secondary charger is turned off (step 16), and when 55 pulses are counted, the secondary charger is turned off (step 7018), and when 47 pulses are counted, the forward clutch and exposure lamp are turned off to end document scanning (step 7018). 20). Therefore, there is no need to provide an optical system detection switch on the moving path for stopping the scanning. Next, do 20 pulses and add 10 pulses to 8Tli
, P24, the creation of the electrostatic latent image on the screen drum is completed and the transfer cycle to the insulated drum immediately begins, so the drum motor is switched from the first speed to the second speed. Therefore, the counting clock is then clock pulse 2 (described above) which occurs once per 10 degrees of rotation of the screen drum rotating at the second speed. Thereafter, similar control is carried out to turn on the paper feed roller (step 30), and when 39 pulses are counted, the forward clutch of the optical system is turned on and the optical system is moved backward. Therefore, the forward motion stops (
Since there is a delay until the return movement starts after 7 seconds, there is less shock when switching movements. In addition, since the return process is started without waiting for the start and completion of the return movement, copying time can be shortened. S'l'EP
43 increases the number of copies by 1, 5TEP 44 5TO
It is determined whether a P command is issued, and if a 5TOP command is issued, a 1 is written to address It A M 3 to memorize the end mode. In addition, S'l'EP 45 judges whether the desired set number of copies set in the key/manufacturing/tree cycle matches the number of copies, and if they match, S'l'EP 46 also stores the data in the RAM address 3. Enter 1 to remember the end mode. It doesn't match!
-1h, proceed to history 5TEP47, 5TEP 7f
Subtract 1 from the number of repetitions set in RAM address 4,
8'l'EP 48 determines whether RAM address 4 is 0, jumps to 5TEP 46, and performs the same process (writes 1 to RAM address 3. If it is in end mode, S'L'EP
At step 49, the screen/bias and latent image transfer charger are turned off. Subsequent 811'EP 51, 5TEP 60
. 5TEP 66 determines whether any of them are in end mode. When the end mode is entered, the 5TEP 51 keeps the paper feed roller off. Iroshi step 54
Since the separation claw is turned on and the following sequence is continued, it is not necessary to feed new paper, but the copying of the paper that has already been fed can be completed and outputted. Turn off the Vi developer with S'I''EP60, and turn off the next K<ru screen/・ with Si'EP66.
If the drum has a home position and is not in the end mode at this step, it returns to 5TEP 40 and repeats copying from the primary latent image. S'l'EP 6B may have reached the same number of end modes 12 repeatedly, or because the number of copies per copy matched the set number of copies using the 5TUI' command).
1. If it is the former, wait for the screen drum to make one more rotation (-) at 5TEP 71, and when it reaches the home position, turn off the second speed drum motor. 5TEI' Return to 7 and set the first speed t
Switch to the y-chromator and repeat the steps from electrostatic latent image formation again. In the latter case Ht. After searching the screen drum position with 8'l'EP 67, CF2 is 330 (8TEP 69)
K Natsuko came and turned off the drum motor (v2),
Completely complete the copy cycle, return to the first key cycle, and wait for operator commands again. If said CP2 ends the copying cycle at 330 (i.e., 30' before the screen drum reaches its home position Ml), K prevents the drum from stopping some distance past the home position. Next, the operator issues a copy command and at 5 TEP 6, the first
Eliminate extra time required for copying. The zologram instructions for executing each of the above steps will be explained using the case of U COM A manufactured by 8 Densha.
'il instruction YIY2Y3Y4 ZIZ2Z3Z4Xl
~4 to PH3, X1~4 to PH1, X1~4 to FB
Transfer to I. While the program is running, a certain address in the RCM is specified by the PC, and at time T1, the code 0100 is output to the data code bus, and at T2, sw6.9 is opened and closed.
(, i p L/ y sp CK is latched. The same < IlI Q decodes this and recognizes that it is an address designation command, and the same <' is latched to register PB3 by opening/closing T3 SW9°8W15.Next, add +1 to PC,
The code of the address following the above in the ROM is ¥1-4. Output Z1 to 4 and store them in PH1 and PBI (7, so store the new address you want to use in a later program in PBK. This execution timing is slightly different from Figure 4 (5). 2, 0101 XlX2X3X4 Jump instruction YIY2Y3Y4 When the jump condition of Z1z2Z3Z4X is satisfied, the jump destination addresses Y1 to 4.Z1 to 4 are transferred to each PB2.PB1, and further PH1 is transferred to PC2 and PBI to PCI, and the jump is completed, but if it is not satisfied, the jump is not performed.X1 to 4 0010 is over 70-0■F is detected as 1 t, ;#, jump instruction, when register A is O in oloo, unconditionally in 1000, 1010te Vi
OVF' is 0, 110 C) CVi') Star A is 0
This can be done with a jump command when not in use. First, when Tl+T2, 1'lJj T, an address in RcM is specified by PC, and at time TI, code 0101 is output to the data code bus gfl,'[°2, and the register CVC is latched by opening/closing SW6°9. Ru. Same (“l’
At 2, the following signal Xl-4 is output to the bus line and latched into register D by opening/closing SW7.9 at '1°3. Now, X
Assuming that I~4=0100, at time T4, 01
It decodes the code of 01,0100, recognizes that it is a jump instruction, and determines the contents of register A. During the subsequent time T5 to T10, it first determines whether the contents of register A are zero, and then determines whether the contents of register A are zero. If not, add +2 to the PC and exit the jump command. If it is zero, tfPCi+I
ROM (i') above Vc continuation (:I-1-"Yl~,
i and Zt~4 are stored in PH1 and FBI by opening and closing 8W9 and Swl 1.5W13, respectively. Furthermore, P
Transfer from B2 to PC2, PBI to Pct. As a result, the jump destination address appears on the PC, and the next T1-T1
Fi at the end of slack in cycle 0 1. , It's the obi fabric,
Complete the Sane Shamezo specified by OM. 3, 0110 1000 Transfer command (1) This is P
B'''c Store the data at the set address in register A VC (hereinafter referred to as row\). At the time of TI0T2, write R on the PC.
An address in OM is specified, and 1 code 011 is sent at time Tl.
0 is output from the data code bus PC, T 2 Te 8 W
6, 9 (') The register CIK is ratted by opening and closing. 1000 followed by the same <'I' 2 is said every f
! It is output to register D and latched to register D by opening/closing of 8W7°9 at 'j゛3. At T4, the codes in registers C and D are decoded, and at the time from T5 to 'l' IO, the code of P]3 is output to the address code bus tl, and this band 1' is designated R.
The contents of any of the key registers of A M, the output device, and the key display input/output device are output to the data code bus, and SW9. The data is stored in register A by opening and closing SW2. Since it functions in a similar manner, it will be briefly described below. The codes for setting the necessary input/output devices and memory itself in the following manual VC which performs photocopy control by making full use of the command codes r shown in Table 3 and above are as follows. This means that the xVi code is not limited. In Table 4, the top four of the 12 address code bus lines are lines for selecting memories, etc., and each memory and input/output device has a circuit known in itself for decoding this. The other eight lines are furthermore lines for specifying sub-addresses of the memory, each memory having a circuit known per se for decoding them. Each input/output unit in the input/output device has data 4b in this example.
Since it corresponds to each digit of it, no special designation circuit is required. Next, representative steps in the copying cycle shown in FIG. 9 will be specifically described. Step 1 and Stella f2 first
This is illustrated by the instruction flow and code shown in Figure 0. In the instruction flow, after step 0 of the spinning key entry,
In step 1-1, address (1) of the input device ('
Ol10) is set in the register PB3, and in the next step 1-2, the contents of the input device (1) specified in the register PB3 are transferred to the register A, and Stella fl-3 is set.
Then, it is determined whether the contents of the register A are O or not. If not, the address (020) of the input device (1) is set to PH1 again, and the contents are transferred and the determination is repeated. Shi7 Kishishi
. When the content of Sister A is 0, that is, when the paper, toner, etc. conditions of the input device (1) are satisfied, the item is transferred to Stella 7°2. In step 2-1, address (o. 10) of output device (1) is set in register PB3 (7), and in step 2-2, 0001 is entered in register A in order from the lower digit of the code,
In step 2-3, the contents of this register A are transferred to the output device fit (1i) specified by the register PR3, and the 1θ4 drum motor Vl corresponding to 00111 of the output device (1) is driven. (2) will be explained in detail with reference to the circuit example in FIG.
゛Record in advance from address 1 to address 8 of the ROM based on the table.
Keep it at 7. 5TEP l(,11,i, ground 110M
Code 1-1 000000000000 01000
110 Address code of human powered device (1) 0000 0000 0001 0000 0000
1-2 1 # 0010 0
101 1000# # (+100 000
0 QOOO jump destination I [JM address 2-1
1 1 0101 01 (+001110 Output device (11 Vf ground code # # 0110 0000 00
002-2 # # 0111 011
1 1000 Code to be transferred to register A 2-3 # I 1000 1000 1(t
o. After the contents of the above ROM address 00 are read, the motor
The process up to activation will be explained using the time chart in FIG. 4 and the circuit in FIG. 3. First, the resistor PCH is cleared at the same time as the power is turned on, so as mentioned above, the time Tl + T20 in Figure 4 (time zone - mother WIJ 12 KPC) is $0000゜oooo
, oooo codes are output and address 0 of the ROM is specified. As a result, at time T1, the upper code 0100 of the 0 address is outputted to the four data code bus lines r (by opening/closing SW9 and SW6), and at time T2, this is latched into register C. Immediately, this is decoded by the command decoder C'F+, which subsequently converts the code appearing on the data code bus into PB3, PB2, PBI.
A control signal α is generated to be stored in the . Therefore, T2
When the time comes, the lower code 0110 of the ROM address 0 is output to the bus line, and immediately 8W9°5 according to the above α is output.
By opening and closing W15, it is latched to PB3. Next, add 1 to the register PC and write the code of the next ROM address 1 to the bus line with the upper oooo and the lower 0000 Ill.
K is output, and this is similarly converted to SW9゜SW by α above.
11 start ff1K, t:suPB2, PB1 start fgsei' Execution ends by time 10. At the next Tl...When it becomes I, add 1 to the PC to instruct ROMz planning, and at T1 output T2 of upper code 0110,
This is the register CVC latch and the lower code 1000
This is outputted to register D at T3. I
ll Decipher with 4 7. At time T5 to i'IO, output the code of PB, that is, 0110 0noo oooo, to the address code bus 7. Specify input device w (1) and input it to the four legs of the kneading Parallel rc ff
' - output to the data code bus line, and is latched by register A by opening/closing SW9.8W2. (Figure 14 #jlt
i) This input device'(1) has four inputs; V as shown in Table 3 and #1' remaining reserve signal (l-absent, 0-present). Since the toner rAff- signal (1=heat, a=present), fuser heater proper temperature detection error (1=NO, 0=OK), and sono command (1=present, 0=absent) are included, Total 8 inputs
If 1S is '(1'' level), it is possible to enter the copy cycle. However, in Tz, add 1 to C and specify address R, OM 3. First, upper 0101 is register C1 lower 1100 is register D as mentioned above [7
It is latched and then decoded. It is determined that this is a conditional J/f instruction, register A? When it is 0,
Further, the PC is incremented by 1, and the code at address It OM 4, upper oooo, oooo00, is output to the first-order data code bus as described above, and the upper 0000 is transferred to PB2 and the lower 0000 is transferred to PBI. Therefore, the code F of PB
It becomes ixxxx oooo oooo. Then, PB2 is transferred to PC2 and PB1 is transferred to PCI to complete the execution, so the PC's call is ooo. It becomes oooo oooo. Therefore, at time Tl #-
The ROM, O address code appears again in the i address code r, and the contents of the ROM addresses O to 3 are repeated. However, if register A=O and all the blockage state detection signals are OK, then PC is increased by +2. Therefore, the jump instruction is exited, and the address code bus is 1 at the next time Tl.
(, OM 5 address is specified. Same as above, PC seat R
OM5.61i? Output device to PB with the code of
(The address code of ++ is set. Then, when the PC is further +1, the ROM7 address is specified at the next time T1, and at T2, the upper code 0111 is latched into register C, decoded, and the following lower 1000 SW9.f9V
Opening and closing of 1 and 2 causes register A to latch and finish. Furthermore, add 1 to pc, specify address 几(') N18 in the next T1, and in T2 specify the content of this address V) top 1 (+ (l O
into register C, 'I' 3 and lower 1ooo into register D
It is latched and decoded. B, 1 Contents of register A 1
oo. is output to the h data/code bus by opening and closing the SWI and SWs, and at the same time, the PBK latched knee S O
(Outputs +10 0000 0000 to the address-to-Pa line, specifies the output device (1), and latches the code on the data code bus line to the four output lines of the output device # and (1). .Therefore, the output is 1el=0,1θ
2=0, 1 #3=0, 1θ4=1. lθ4
is connected to the drum motor Vl (first speed) through the interface circuit shown in Figures 3-4, so the drum motor starts in first speed. Next, the step 6 of FIG. 9, the drum home steering procedure, will be explained in detail with reference to the command flow of FIG. 11. After completing the operation of the clutch in step 5, in step fi-1 the address (oll 1) of the input device (2) is set in register PB3, and in step 6-2 the address (oll 1) of the input device (2) is set in the upper 8 pin register PB3. The contents of register A are transferred to register A, and in step 6-3, the contents of register A are rotated clockwise.In step 6-4, as a result of clockwise rotation, register A
Determine whether or not overflow has occurred, and determine whether (l−
Stella 7'6-1.6-2 inputs the input again and repeats the overflow determination 6-3. Step 6
When the overflow of register A is detected at -4, the process is skipped, and when the Baum position is detected, the process proceeds to the next step 7. Write the code in Table 1 that executes steps 6-1 to 6-4 in step 5 from 100001 to V(t) as follows. 5TEP ROM address ROM code Ol
l 110000006-2 0
1 2 011010006-3 0
1 3 11110111 That is, following step 5, the upper code 0100 is outputted to the data code bus from the designated address 10 of it OM as described above and latched into register C. Immediately, the contents of register C are decoded by 1jcPU, and a control signal α is generated to store the code appearing next on the data code bus into PB. Therefore, when the lower code 0111 at address 10 is output to the data bus at the next clock, it is latched to PB3 by SW9.15, which is opened and closed by the α signal. From here on, the same process as in the previous example up to address 02 is carried out until the end of the line in ROM12Tf, that is, PR code 011
1 0000 Output 0000 to the address code bus, specify the input device (2), and output the signals input to the four wires of the input device (2), for example, 0000 in parallel to the data code bus, SW9.2 This is latched into register A by opening and closing. This input device* (21K H Slurry/home position detection signal shown in Table 2 (1: present, 0: absent)
, optical system home position detection reliability (1: present, 0: absent), Tsumugi
and a second clock pulse detection signal (l: present, 0: absent) are input (the above example indicates that nothing is detected). Next, when ROM address 13 is specified, the top 11 of its contents are
The lower 0111 of register C2 is latched into register D as described above and decoded by the CPU. This is determined to be a clockwise rotation command, and the series 4-digit contents of register A are shifted one digit to the right. Register A Kkeooo
is stored, so register A will not overflow even if it is shifted. Next, after the shift is executed, the PC is +1 and the ROM 14 address is specified, the upper 0101 is stored in the register C1 and the lower 0010 is stored in the register D and then decoded. This is judged to be a conditional sharp/shut instruction, and the previous register A
Detection of overflow by shifting to the right 50VF is not 1, that is, the slurry/home position is not detected, so
Add 1 to PC and specify ROM address 15. So[7teR, 0M15 contents 0001 0000 to 1
Ranji data code bus line is U”, the above 0001 is PB
2 transfers the lower 000o to PB 1 and further PB to PC
After completing this step, the location designation code R,0Ml0i is stored again. At the next clock (T1), the contents of this PC are output and the ROMI (from address l to ROM13 address is repeated. However, an overflow is detected in step 6-4, that is, in step 6-2, register AK0001 is
(Home position detection) is stored, and by shifting to the right in step 6-3, 1 is added to the OVF. This is decoded and the PC is +
Generate Shinsaki α to make it 2. Therefore, go through the R/OM address for jump and step 7.
Store the code of the ROM address in PCK. Next, the copy clock in step 8 of FIG. 9 is counted 1. The procedure for turning on the -order distortion ta will be explained in detail with reference to the command flow shown in FIG. Each step in the instruction flow corresponds to each address (as in the previous example). In step 7'8-1, a predetermined count value 6o of the copy clock for the time until the drum motor drive in step 7 is turned on is stored.
Set the code of address N (for example, 120 address) of M to PB. 1't OM K written code (from address 20 to 4
9) will be explained below. When address 20 is designated, Iti next 0100, 0000 data gradient line Vc is output, the upper 010o is stored in register C, and the lower oooo, which cannot be read by the CPU, is stored in PB3-1. Next KP
When the ROM21 address is designated by adding 1 to C, its contents (11000000) are outputted to the data bus line and stored in the respective PH2°FBI in the same manner as in the case of t1. Tsukiri RO
Designation code of M and R(') 120 location designation code r in M is stored. Step 8-2. re-switching]-)C
When the ROM22 address is specified by +1, its contents are output to the data bus, and the upper 1101 is the register C1 and the lower 0.
000 is stored in the register DV (and decoded by the CPU, and the above code of PB is output to the address code bus line. Therefore, specify the corresponding ROM and its 120 address, 7 and 12
A code with the content 60 (corresponding to the above count value) of the zero point is output to the data code bus line. Then, of the 8 bits of the count code, the 4 bits of the -F order are transferred to register A and the lower 4 bits are transferred to register B and stored therein. After storing, the ROM 23 address is designated with CP 2 +11 and the process proceeds to step 8-3. That is, the contents of this address are sequentially output to the data code r motherboard and stored in the register.
Transfer to 0 and proceed to step 8-4. ROM24
When an address is specified, the contents of this address are output to the 1111st data code bus line and resolved, and as a result, each of the upper registers of register B is transferred to register A, and in the next step 8-5, the specified ROM 25 address is This is transferred to the FBI by solving the instruction code M. In step 8-6, the instruction code at address 26 in the ROM is decoded [7, the contents of the above PB3, 2.1 are stored in the RAMK via the data bus (7), and the start time of the charger is temporarily stored. Next step 8
-7, the ROM27 address is specified and the contents are outputted to the data code bus through the same process as in the previous example.By decoding the upper 0100, the lower 0111 (input device!
(code corresponding to 2+) is stored in PB3. In step 8-8, the input contents of the input device @(2) are transferred to register A (7, in the next step, the contents of register A are rotated counterclockwise. That is, the contents of the human-powered device (2) are changed from the previous example,
Shift to left digit. Step 8-] Since the t-dimension copy clock detection signal of the counterclockwise rotation at O is located at the second left digit, the presence or absence of 1 at this position is detected. Proceeding to step 8-11, if address Ft OM 32 is not specified, it is determined whether or not there is an overflow in the VC as in the previous example. When OVF detects 1 after two left shifts, It OM
Repeat the ladle step with step I7 specified at address 33. When 0VFI is not detected (i'+), the process proceeds to the next step 8-12. In this example, the steps described above are executed to first detect the level 0 of the copy clock pulse so that the rising edge of the copy clock signal is detected from 1 to m for the number of copy clocks. Therefore Stella 7'8-12 to 8-
16 is a process of detecting level 1 of the copy clock pulse. This process has a similar flow to the previous example and
When the OVF detects 1 in step 8-16, step 8-! Proceed to step 7, and in the previous step 8-6, the contents stored in 1 (,
Transfer to B3,2゜1. Then, in step 8-18, PB is -1, and in step 8-19, the subtracted PB is calculated.
is stored in RAM. In step 8-20, PB2 is transferred to register A (the contents of PB are not erased by executing step 8-19), and in step 8-21, the contents of register A, that is, the high-order of the subtracted numerical code, is 0. Determine whether or not. RO because it is not register At1O
It jumps to the It 011.127 address specified by address M46, ie, step 8-7, and executes the steps up to now again. Therefore, by incrementing the numerical values stored in R and AM by -1 each time the copy clock rises, the previous steps are repeated a predetermined number of times, and the upper digits of the numerical code are zeroed.
up to that point is counted. Then, when register A becomes OVC, the process advances to step f8-22, and the contents of FBI having the lower order of the subtracted numerical code are transferred to register A, and step 8-23
It is determined whether register A is 0 or not. When register A is not O, it was not specified in ROM49i [10 N127
Go to step 8-7 at address r (J/7'' again) and execute the steps up to now until the lower digit becomes 0.Then register A becomes OVC, and the copy clock counting step is completed. The operating resistance of the copying machine advances to the next 9th step, and VC is turned on to the -order distortion electric current. 1i, the synchronization of the clock pulse dedicated to CPIJ is 11C5.
Since it is eC, it takes about 30 seconds to execute one cycle of the above counting steps (7
Since one step is at most 10 clocks x 1 μsec, it is at most 300 μ. This means that the synchronization of the copy clock pulse is approximately 13
Since it is m5ec, it does not affect the number of digits. In the controller IvA as described above, the instruction code of the ROM,
There is one control unit V (one circuit) that clears the data code and outputs the control signal α, and a schematic circuit example thereof is shown in FIG. The steps can also be configured in a similar manner.

[Brief explanation of the drawing]

Figure 1 i+, ft1ll side 1 system of the present invention, all 1 side 1 use (
Also, a sectional view of a retention copying machine. 26, a sequence time chart of a retention copying machine, FIG. 3, and FIGS. 3-1 to 3-4 are
Fig. 4 is a clock time chart for advancing the address of tOM, Fig. 5 is an example of a circuit of an input/output section, Fig. 6 is an example of a control circuit, and Fig. 7 is an example of a control circuit. Figure 3 is a schematic flowchart of the copy-i cycle, Figure 8 is a key/key flowchart in Figure 7, and Figure 9 is a sequence control ill//no flowchart in Figure 7. , 101CH, an example of the instruction flow for starting the input judgment drive in Fig. 9, gttt\1-, home position t
17 is an example of the instruction flow in detection, Figure 12 is an example of the instruction flow at t-7 in the number of copy clock sets, and Figure 13 is an example of writing the ROM code required in Figure 12. Fig. 71 is a schematic circuit diagram of part 1 of the 11th control;
RO~I iJ copy sequence is memorized as an instruction code 7
RAM is a write/read memory that stores copy settings, etc., ■ is a device for inputting data such as subject status, 0 is a copy processing device corresponding to 17 output devices, CI ) [1 is a central processing unit that reads and discriminates data and instructions and outputs required signal data. Figure 10 Procedural amendment (method) September 2q, 1980 Director-General of the Patent Office Kazuo Wakasugi 1 Indication of the case 1988 Patent Application No. 56207 2,
Name of the invention Control method for copying machines etc. 3 Relationship with the person making the amendment 41 Patent applicant Address 3-30-2 Shimomaruko, Ota-ku, Tokyo Name (+00) Canon Co., Ltd. 6, Amendment order attached [1] August 30, 1982 (Delivery date) 6. Specification to be amended, contents of amendment * (no barbaric content) Hand k no ° 5 Sleeve original writing (spontaneous) + 1/I sum July 1958 eP (Co-Special, :Relationship with the layered small town I Patent applicant address 3-30-2 Shimomaruko, Ota-ku, Tokyo Name (+00
) Canon Co., Ltd. Representative Kaku 11-3 Department 4, Agent Notification Office 3-30-2 Shimomaruko, January-ku, Tokyo 146
Detail 6, Contents of amendment (1) The third line of page 1-2 of the description is corrected as follows. 1) To which the present invention is applied (explaining an example of a copying machine in terms of a copying process, the surface of a photosensitive drum having a photosensitive member consisting of a conductive layer, a photoconductive layer, and an insulating layer is uniformly charged by a primary charger as the drum rotates). M7 is charged (for example, positively charged), and then an optical image is scanned and projected as the document table or optical system moves. At the same time, a nail charger is used to charge the
The static electricity is removed by a direct current having a polarity opposite to that of the weight, and an electrostatic latent image corresponding to the brightness 11Δ of the optical image is formed. Furthermore, the entire surface of the latent image is exposed to light to form a high-contrast electrostatic latent image, which is then made visible by a developer mainly containing toner in a developing device. Thereafter, due to a corona discharge of the same polarity as the above current (for example, negative if the current is positive), the visual image is easily transferred and transferred to plain paper. Turn around! J゛material-ni 111. The developer such as 71 color particles remaining on the surface of the photosensitive drum after one rotation is removed by a cleaning roller, and the remaining weight is removed by a lamp and a corona release device, making it possible to repeat the photosensitive drum. By repeating the multiplexing process as described above, 9! Recording control of such copying machines was performed by outputting control signals under the best conditions for safe recording. It has also been considered to use a digital data processor for this purpose. However, this has the disadvantage that the number of condition signals requires manual labor and is complicated. The present invention eliminates these drawbacks and improves the input configuration for the digital data processor. This is convenient for the sequence control of the camera resistor, which has a large number of conditional signals. A human power means for inputting a signal, an output means for outputting an operation timing control signal to the processing equipment, and a data processor (CPU) for parallel processing with a predetermined number of focus points, and -1- from the input input means. By discriminating and processing the signals and sequentially executing the above 7° program, recording control is carried out.

Claims (1)

[Scope of Claims] A read-only memory that records the operation and sequence program of processing equipment for recording process processing, input means for inputting signals necessary for recording, and outputting operation timing control signals to the processing equipment. and a data processor that performs parallel processing using a predetermined number of bits. Each of the sources of the input signal is connected to each bit position of at least one input means in the input means, one of the input means is selected by a selection signal thereto, and a particular bit of the selected input means is selected. A method for controlling a copying machine, etc., which judges the data and performs recording control accordingly.