JPS594028A - Manufacturing device of semiconductor - Google Patents
Manufacturing device of semiconductorInfo
- Publication number
- JPS594028A JPS594028A JP11313282A JP11313282A JPS594028A JP S594028 A JPS594028 A JP S594028A JP 11313282 A JP11313282 A JP 11313282A JP 11313282 A JP11313282 A JP 11313282A JP S594028 A JPS594028 A JP S594028A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- plasma
- gas
- upper electrode
- chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は半導体の製造装置にかかり、特にプラズマCV
D若しくはプラズマエツチングのための電極構造を有す
る半導体製造装置に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to semiconductor manufacturing equipment, particularly plasma CV
The present invention relates to a semiconductor manufacturing apparatus having an electrode structure for D or plasma etching.
(2)技術の背景
近年、例えばMO3IC製造工程時に多結晶Si、5t
O2,PSG (ボスフォシリケードガラス)等はCV
D法によって形成されている。しかし、CVD法は耐温
性、フラツグ等の点で問題があるため、最近プラズマ反
応を用いたすなわち低温で反応をおこし薄膜を形成させ
るプラズマCVD法が行われるようになってきた。(2) Technology background In recent years, for example, polycrystalline Si, 5T
O2, PSG (bosphosilicate glass), etc. are CV
It is formed by the D method. However, since the CVD method has problems in terms of temperature resistance, flagging, etc., recently, a plasma CVD method that uses a plasma reaction, that is, causes a reaction at a low temperature to form a thin film, has been used.
(3)従来技術と問題点
第1図(δ)乃至(C)は、従来のプラズマCVD装置
であり、第1図(alは全体の構成を示ず路線的断面図
、第1図(blは電極部を下から見た平面図と第1図t
c+は開部断面図をそれぞれ示す。(3) Prior art and problems Figures 1 (δ) to (C) show conventional plasma CVD equipment; is a plan view of the electrode section viewed from below and Figure 1
c+ shows an opening cross-sectional view, respectively.
同図において、上部電極部1は主にガス取入れロタ1幅
広電極部3.ガス吹出し口は透孔4等からなり、また所
定の化学反応を起こして薄膜を形成させるためのウェハ
9を載置させた下部電極5と該下部電極5の外周部の真
空排気口6の下方にはチャンハフを真空状態になすため
の真空ポンプ(図示せず)が設けられている。In the figure, the upper electrode part 1 mainly consists of the gas intake rotor 1 wide electrode part 3. The gas outlet is composed of a through hole 4, etc., and is located below a lower electrode 5 on which a wafer 9 is placed for causing a predetermined chemical reaction to form a thin film, and a vacuum exhaust port 6 on the outer periphery of the lower electrode 5. is equipped with a vacuum pump (not shown) for evacuating the chamber.
真空排気口6の下方に設けられた真空ポンプによってチ
ャンバ7の内部を例えばほぼI Torr程度度の低圧
状態に維持させておき、ガス取入れ口2よりプラズマガ
スとして用いる例えば3iHn。The inside of the chamber 7 is maintained at a low pressure of, for example, approximately I Torr by a vacuum pump provided below the vacuum exhaust port 6, and a plasma gas, such as 3iHn, is used as a plasma gas from the gas intake port 2.
NH3等の気体を取り入れてガス吹出し孔4がら放出さ
せ、さらにまた、高周波発生部8により上部電極部1と
下部電極5とに高周波電圧を印加させて高周波放電をお
こさせることにより、プラズマを形成する。このプラズ
マ中のイオン電子等によりウェハ9上において所定の化
学反応がおこり薄膜がウェハ上に成長して所望の半導体
が形成される。しかしながら、従来は電極部が同図(b
l及び(C)の如く円形のガス吹出し口4のエツジ部1
oが孔開けされたままの鋭利な形状を有するために高電
圧をかけると孔のエツジ部1oに電界の簗中が起こり高
角l放電が不吋−性となりいわゆる異常放電を生じ易く
、かかる異常放電下でプラズマ。Plasma is formed by taking in a gas such as NH3 and releasing it through the gas blowing hole 4, and further applying a high frequency voltage to the upper electrode part 1 and the lower electrode 5 by the high frequency generator 8 to cause a high frequency discharge. do. A predetermined chemical reaction occurs on the wafer 9 by ions and electrons in the plasma, and a thin film grows on the wafer to form a desired semiconductor. However, in the past, the electrode part was
Edge part 1 of circular gas outlet 4 as shown in l and (C)
Since the hole 1o has a sharp shape after being drilled, when a high voltage is applied, an electric field is generated at the edge 1o of the hole, and the high-angle discharge becomes stationary and tends to cause so-called abnormal discharge. Plasma under discharge.
CVDを行うと例えばウェハ9における膜厚成長速度が
不均一となり、膜厚にムラが生じたり、また著しい場合
には気相反応が発生してウェハ9上に白い粉が落下して
所定の薄膜成長がなされず半導体の製造上不都合を生じ
ていた。なお、上述の界雷放電の発生は、例えば電極に
設けられた孔の径を小さくすることによりある程度抑え
ることができるが、電極加工の困難な利質を用いた場合
には小さなアパチャが得られない欠点があった。When CVD is performed, for example, the film thickness growth rate on the wafer 9 becomes non-uniform, resulting in uneven film thickness, or in severe cases, a gas phase reaction occurs, causing white powder to fall onto the wafer 9 and making it impossible to maintain a predetermined thin film. Growth was not possible, causing problems in semiconductor manufacturing. Note that the occurrence of the field lightning discharge described above can be suppressed to some extent by, for example, reducing the diameter of the hole provided in the electrode, but if the electrode is difficult to machine, a small aperture cannot be obtained. There were no drawbacks.
(4)発明の目的
本発明は、上記従来の欠点に鑑み、プラズマCVD装置
或いはプラズマエツチング装置の幅広電極部のガス吹出
し孔をスリット状に形成することによって、均一なプラ
ズマを生成し、さらにまた電極部内のスリットの直前部
に多孔板を設けることによってさらに均一なプラズマを
生成し、良好な半導体の膜厚成長を提供することを目的
とするものである。(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention generates uniform plasma by forming a gas blowing hole in a wide electrode part of a plasma CVD device or a plasma etching device into a slit shape. By providing a porous plate immediately in front of the slit in the electrode section, the purpose is to generate more uniform plasma and provide a better semiconductor film thickness.
(5)発明の構、成
本発明の特徴は、チャンバ内にガス吹出し口を有する上
部電極と下部電極を備え、下部電極にウェハを載置し該
チャンバ内にガスを充填してプラズマ放電させてなる半
導体製造装置において、上記上部電極のガス吹出し口の
面積に対し周長の割合の大きい適宜形状の開口部を設け
てなることを特徴とする半導体製造装置を提供すること
にある。(5) Structure of the Invention The feature of the present invention is that a chamber is provided with an upper electrode and a lower electrode each having a gas outlet, a wafer is placed on the lower electrode, and the chamber is filled with gas to cause plasma discharge. An object of the present invention is to provide a semiconductor manufacturing apparatus characterized in that the upper electrode is provided with an opening having an appropriately shaped opening having a large ratio of circumference to area of the gas outlet of the upper electrode.
(6)発明の実施例 以下、本発明の実施例について図面を用いて説明する。(6) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第2図+a+、 (blは本発明半導体製造装置の構成
を示す断面図と本発明の上部電極の構造を示す斜視断面
図である。FIG. 2+a+, (bl is a cross-sectional view showing the configuration of the semiconductor manufacturing apparatus of the present invention and a perspective cross-sectional view showing the structure of the upper electrode of the present invention.
第2図(at、 fblにおいて第1図(a)と同一部
分には同一符号を付して重複説明を省略する。上部電極
1′は幅広電極部3の下面のガス吹出し口をスリット4
′となし、該ガス吹出し口をスリット4′を覆うように
多孔板11を該ガス吹出し口の上に配設する。In FIG. 2 (at, fbl), the same parts as in FIG.
', and a porous plate 11 is disposed above the gas outlet so as to cover the slit 4'.
これら上部電極1′と下部電極5間にウェハ9を配設し
排気口6の下方延長上に設けられる真空ポンプによって
チャンバ7の気密状態を例えばほぼl Torr程度の
低圧状態に保たせる一方、高周波発生部8により上部電
極1と対向する下部電極5との間に高周波電圧印加させ
て高周波放電を発生させ、さらにガス取入れ口2よりプ
ラズマを発生させるための例えば5iHn、NH3等の
気体を取入れて多孔版11を通過させ−ζ幅広電極部3
′に設けたガス吹出し日用のスリット4′から放出させ
る。かかる上下電極板間の放電により、取入れられた例
えば5iHa、NH3等のガスはプラズマ状態になり、
従ってラジカルやイオンが生成されウェハ9にて気相化
学反応をおこして薄膜が形成される。なお、ここでガス
吹出し口として第2図(blの如き細長い形状を有する
スリット4′を形成させている理由について説明する。A wafer 9 is disposed between the upper electrode 1' and the lower electrode 5, and a vacuum pump provided on the downward extension of the exhaust port 6 maintains the airtightness of the chamber 7 at a low pressure of, for example, about 1 Torr. A high frequency voltage is applied between the upper electrode 1 and the opposing lower electrode 5 by the generating section 8 to generate a high frequency discharge, and a gas such as 5iHn, NH3, etc. is introduced from the gas intake port 2 to generate plasma. Pass through the perforated plate 11 -ζ wide electrode part 3
The gas is discharged from the gas blowout slit 4' provided at 4'. Due to this discharge between the upper and lower electrode plates, the introduced gas, such as 5iHa or NH3, becomes a plasma state,
Therefore, radicals and ions are generated, causing a gas phase chemical reaction on the wafer 9, and forming a thin film. Here, the reason why a slit 4' having an elongated shape as shown in FIG. 2 (bl) is formed as a gas outlet will be explained.
一般的に円の面積に対する円周の割合αば、半径をrと
すると
α −2πr/πr2 父 1 / rすなわち円の径
が小さいほど円周の割合は大きくなり、従って、換言す
れば、円の径が小さいほど電界密度が低く、故に電界の
集中を抑えることが容易になる。従ってかかる異常放電
の原因となる電界集中を防止するためには上述の如く開
孔部の径の大きさを小さくする程良いわけであるが、実
際上電極部の材質等により孔の径のスケーリングには一
定の限度を有している。このためこれに代る方法として
、ガス吹出し口の形状を細長い楕円若しくは本発明の実
施例の如きスリット状開孔部を形成することによって電
界集中が抑えられるため上記の異常放電は阻止可能とな
る。また、本発明の上部電極に設けたスリット4′上に
設けた多孔板11ばガスを振分ける機能を有しており、
さらにガス吹出し口のスリット4′の直前に配した多孔
板には円形の孔を多数穿設してやることでスリット4′
からのガスの吹出しを均一にして下部電極5上に載置さ
れたウェハ9の薄膜の成長も均一化が可能となった。In general, the ratio of the circumference to the area of a circle is α, and if the radius is r, then α −2πr/πr2 1 / r In other words, the smaller the diameter of the circle, the larger the ratio of the circumference. The smaller the diameter, the lower the electric field density, and therefore it becomes easier to suppress the concentration of the electric field. Therefore, in order to prevent the electric field concentration that causes such abnormal discharge, it is better to reduce the diameter of the hole as described above, but in reality, scaling of the hole diameter is necessary depending on the material of the electrode section, etc. has certain limits. Therefore, as an alternative method, the electric field concentration can be suppressed by forming the gas outlet into an elongated elliptical shape or a slit-like opening as in the embodiment of the present invention, thereby making it possible to prevent the above-mentioned abnormal discharge. . In addition, the perforated plate 11 provided on the slit 4' provided in the upper electrode of the present invention has a function of distributing gas.
Furthermore, by drilling a large number of circular holes in the perforated plate placed just before the slit 4' of the gas outlet, the slit 4'
By uniformly blowing out the gas from the wafer 9, it became possible to uniformly grow the thin film on the wafer 9 placed on the lower electrode 5.
以上のようにスリット状ガス吹出し口を用いると、真円
の孔よりも開口面積に比してエツジの長さを長くするこ
とが可能であり電界集中を避けることができ、従って界
雷放電は起りにくくなる。As described above, when a slit-shaped gas outlet is used, the length of the edge can be made longer than that of a perfectly circular hole compared to the opening area, and electric field concentration can be avoided, so field lightning discharge can be prevented. It becomes difficult to wake up.
またさらに必要に応じてスリット間隔を狭めることは小
さな孔を開けるよりはるかに容易に形成できる。Furthermore, it is much easier to narrow the slit spacing as needed than to make small holes.
(7)発明の効果
本発明の半導体製造装置を用いると、上部電極部におけ
るガス吹出し口の開孔部の面積に比して外縁周長の割合
が大きいため、異常放電を起す原因となる電界の集中が
阻止可能となり、均一な膜厚を有する半導体の製造が可
能となる。(7) Effects of the Invention When the semiconductor manufacturing apparatus of the present invention is used, the ratio of the outer edge circumference to the area of the opening of the gas outlet in the upper electrode part is large, so the electric field that causes abnormal discharge This makes it possible to prevent the concentration of oxides and to manufacture a semiconductor having a uniform film thickness.
また、上部電極の製造の際に、例えば幅広電極部のスリ
ットの形成加工が容易となり、より精度の高い製造装置
が得られる。Furthermore, when manufacturing the upper electrode, it becomes easier to form slits in the wide electrode portion, for example, and a manufacturing apparatus with higher precision can be obtained.
第1図(a)乃至(C)は従来のプラズマCVD装置に
おける全体の構成を示す断面図と電極部の下から見た平
面図及び開部断面図をそれぞれ示す。第2(al、 (
blは本発明半導体製造装置の構成を示す断面図と本発
明の特徴とする電極部の構造を示す斜視断面図である。
1.1゛・・・上部電極部、 2・・・ガス取入れ口、
3,3′・・・幅広電極部、 4′・・・スリ7+・
、 5・・・下部電極部、 7・・・チャンバ部、 8
・・・高周波発生部、 9・・・ウェハ、 10・・
・エツジ部、 11・・・多孔板。
特許出願人 富士通株式会社
135FIGS. 1(a) to 1(C) show a cross-sectional view showing the overall structure of a conventional plasma CVD apparatus, a plan view seen from below an electrode part, and an open cross-sectional view, respectively. Second (al, (
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor manufacturing apparatus of the present invention and a perspective cross-sectional view showing the structure of the electrode portion, which is a feature of the present invention. 1.1゛...upper electrode part, 2...gas intake port,
3, 3'... wide electrode section, 4'... pickpocket 7+.
, 5... Lower electrode part, 7... Chamber part, 8
...High frequency generation section, 9...Wafer, 10...
- Edge portion, 11... perforated plate. Patent applicant: Fujitsu Limited 135
Claims (4)
部電極を備え、下部電極にウェハを載置し該チャンバ内
にガスを充填してプラズマ放電させてなる半導体製造装
置において、上記上部電極のガス吹出し口の面積に対し
周長の割合の大きい適宜形状の開口部を設けてなること
を特徴とする半導体製造装置。(1) In a semiconductor manufacturing apparatus comprising an upper electrode and a lower electrode each having a gas outlet in a chamber, a wafer is placed on the lower electrode, and the chamber is filled with gas to cause plasma discharge. 1. A semiconductor manufacturing device comprising an opening having an appropriately shaped opening having a large ratio of circumference to area of a gas outlet.
を設けてなることを特徴とする特許請求の範囲第1項記
載の半導体製造装置。(2) The semiconductor manufacturing apparatus according to claim 1, further comprising a porous plate provided in the upper electrode to cover the gas outlet opening.
を特徴とする特許請求の範囲第1項記載の半導体製造装
置。(3) The semiconductor manufacturing apparatus according to claim 1, wherein the gas outlet of the upper electrode part has an elliptical shape.
とを特徴とする特許請求の範囲第1項記載の半導体製造
装置。(4) The semiconductor manufacturing apparatus according to claim 1, wherein the gas outlet of the upper electrode part has a slotted shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11313282A JPS594028A (en) | 1982-06-30 | 1982-06-30 | Manufacturing device of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11313282A JPS594028A (en) | 1982-06-30 | 1982-06-30 | Manufacturing device of semiconductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS594028A true JPS594028A (en) | 1984-01-10 |
JPH0437578B2 JPH0437578B2 (en) | 1992-06-19 |
Family
ID=14604351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11313282A Granted JPS594028A (en) | 1982-06-30 | 1982-06-30 | Manufacturing device of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS594028A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6046029A (en) * | 1983-08-24 | 1985-03-12 | Hitachi Ltd | Equipment for manufacturing semiconductor |
JPS6164128A (en) * | 1984-09-05 | 1986-04-02 | Toshiba Corp | Treating device for sample |
US4590042A (en) * | 1984-12-24 | 1986-05-20 | Tegal Corporation | Plasma reactor having slotted manifold |
JPS61174721A (en) * | 1985-01-30 | 1986-08-06 | Toshiba Corp | Parallel and flat type dry etching apparatus |
JPS62109317A (en) * | 1985-11-08 | 1987-05-20 | Anelva Corp | Plasma etching apparatus |
US5006220A (en) * | 1987-10-26 | 1991-04-09 | Tokyo Ohka Kogyo Co., Ltd. | Electrode for use in the treatment of an object in a plasma |
US5010842A (en) * | 1988-10-25 | 1991-04-30 | Mitsubishi Denki Kabushiki Kaisha | Apparatus for forming thin film |
US5091217A (en) * | 1989-05-22 | 1992-02-25 | Advanced Semiconductor Materials, Inc. | Method for processing wafers in a multi station common chamber reactor |
JPH07278851A (en) * | 1994-09-19 | 1995-10-24 | Tokai Carbon Co Ltd | Electrode plate for plasma etching and its production |
USRE36623E (en) * | 1986-12-19 | 2000-03-21 | Applied Materials, Inc. | Process for PECVD of silicon oxide using TEOS decomposition |
US6167834B1 (en) | 1986-12-19 | 2001-01-02 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
KR100489156B1 (en) * | 1994-01-13 | 2005-05-17 | 세이코 엡슨 가부시키가이샤 | Apparatus for manufacturing semiconductor apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5468169A (en) * | 1977-11-11 | 1979-06-01 | Hitachi Ltd | Plasma processor of capacitor type |
-
1982
- 1982-06-30 JP JP11313282A patent/JPS594028A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5468169A (en) * | 1977-11-11 | 1979-06-01 | Hitachi Ltd | Plasma processor of capacitor type |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6046029A (en) * | 1983-08-24 | 1985-03-12 | Hitachi Ltd | Equipment for manufacturing semiconductor |
JPH0473289B2 (en) * | 1983-08-24 | 1992-11-20 | Hitachi Ltd | |
JPS6164128A (en) * | 1984-09-05 | 1986-04-02 | Toshiba Corp | Treating device for sample |
US4590042A (en) * | 1984-12-24 | 1986-05-20 | Tegal Corporation | Plasma reactor having slotted manifold |
JPH0455326B2 (en) * | 1985-01-30 | 1992-09-03 | Tokyo Shibaura Electric Co | |
JPS61174721A (en) * | 1985-01-30 | 1986-08-06 | Toshiba Corp | Parallel and flat type dry etching apparatus |
JPS62109317A (en) * | 1985-11-08 | 1987-05-20 | Anelva Corp | Plasma etching apparatus |
JPH0560650B2 (en) * | 1985-11-08 | 1993-09-02 | Anelva Corp | |
USRE36623E (en) * | 1986-12-19 | 2000-03-21 | Applied Materials, Inc. | Process for PECVD of silicon oxide using TEOS decomposition |
US6167834B1 (en) | 1986-12-19 | 2001-01-02 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
US5006220A (en) * | 1987-10-26 | 1991-04-09 | Tokyo Ohka Kogyo Co., Ltd. | Electrode for use in the treatment of an object in a plasma |
US5022979A (en) * | 1987-10-26 | 1991-06-11 | Tokyo Ohka Kogyo Co., Ltd. | Electrode for use in the treatment of an object in a plasma |
US5010842A (en) * | 1988-10-25 | 1991-04-30 | Mitsubishi Denki Kabushiki Kaisha | Apparatus for forming thin film |
US5091217A (en) * | 1989-05-22 | 1992-02-25 | Advanced Semiconductor Materials, Inc. | Method for processing wafers in a multi station common chamber reactor |
KR100489156B1 (en) * | 1994-01-13 | 2005-05-17 | 세이코 엡슨 가부시키가이샤 | Apparatus for manufacturing semiconductor apparatus |
JPH07278851A (en) * | 1994-09-19 | 1995-10-24 | Tokai Carbon Co Ltd | Electrode plate for plasma etching and its production |
Also Published As
Publication number | Publication date |
---|---|
JPH0437578B2 (en) | 1992-06-19 |
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