JPS5939924B2 - oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that generates triangular waves (including sawtooth waves) used in dither signals and the like.

A conventional triangular wave oscillator uses a circuit that uses two comparators with different set values and outputs a waveform signal that goes back and forth between the respective set values.

However, the above circuit has the disadvantage that two comparators are required, making the circuit complex and expensive.

The present invention eliminates the above-mentioned drawbacks, and provides an oscillator that generates a triangular wave with a simple circuit and can easily and accurately set the upper and lower limit voltages of the output waveform to desired values. With the goal.

In order to achieve the above object, the present invention uses a variable set value comparison circuit that can change the set value, and by switching the set value according to the output voltage, a triangular wave can be generated with a simple circuit. It consists of

The present invention will be described in detail below based on the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is an output waveform diagram of the circuit of FIG.

In FIG. 1, 1 is a variable set value comparison circuit, 5 is an input terminal for inputting the terminal voltage of the capacitor C1, and 6 is a comparison input terminal for inputting the comparison set value.

Further, 2 is a discharging circuit, 3 is a charging circuit, and 4 is an output terminal.

The operation of the circuit shown in FIG. 1 will be explained below with reference to FIG.

First, assuming that the capacitor C1 is completely discharged, the output voltage VOUT at the output terminal 4 (the terminal voltage of the capacitor C1) is equal to the power supply voltage vcc.

Therefore, since the base potential (voltage at input terminal 5) of transistor Q1 of variable set value comparison circuit 1 is high, transistor Q
1 is turned off, and therefore transistor Q2 is also turned off.

When the transistor Q2 is turned off, the base of the transistor Q3 of the discharge circuit 2 and the base of the transistor Q4 of the charging circuit 3 are both at a high level, so that the transistor Q
3 (PNP type) is off, transistor Q4 (NPN type)
turns on.

When transistor Q4 is turned on, resistor R3 is grounded via diode D1 and transistor Q4.

Therefore, the emitter terminal voltage of the transistor Q1 (voltage at the comparison input terminal 6) is the power supply voltage VOO, and the resistor R2 and R3
The voltage is divided by the parallel circuit with the resistor R1 and the resistor R1.

The output voltage VOUT at which the transistor Q1 is turned on at this emitter voltage becomes the lower limit setting value v1 (lower comparison setting value).

In other words, the lower limit setting value v1 is V1 cc - R2Rs
/ (RI R2+R2Rs 10Rs R1).

Also, from the power supply, capacitor C1, resistor R, diode D
Since the charging circuit through transistor Q2 and transistor Q4 is conductive, capacitor C1 is charged.

At this time, the transistor Q3 is off, so the discharge circuit 2 is cut off.

As the capacitor C□ is charged, the output voltage voUT decreases, and at the same time, the base potential of the transistor Q1 also decreases.

Then, when the output voltage VOUT falls to the lower limit set value V1, the transistor Q1 is turned on.

When transistor Q□ turns on, transistor Q2 also turns on, so transistor Q3 turns on and transistor Q4 turns off.

When transistor Q4 is turned off, the emitter terminal voltage of transistor Q1 changes from the power supply voltage VOO to resistors R1 and R2.
It becomes the value obtained by dividing the pressure by , which is higher than the above case.

The output voltage VOUT at which the transistor Q1 is turned off at this emitter voltage becomes the upper limit setting value v2 (the higher comparison setting value).

In other words, the upper limit setting value v2 is V2-vcc-R2/(R
1+R2).

Also, since the transistor Q4 is turned off, the charging circuit 3 is cut off, and the transistor Q3 is turned on, so the discharging circuit 2
becomes conductive, and the charge in capacitor C1 is discharged via resistor R4 and transistor Q3.

As the charge of the capacitor C1 is discharged, the output voltage vo
ty'r rises, and the base potential of transistor Q1 also rises accordingly.

Then, the transistor Q1 whose output voltage voUT reaches the upper limit set value v2 is turned off, and the above operation is repeated thereafter.

Therefore, the output voltage VoUT of the output terminal 4 has a waveform that goes back and forth between Vl and V2, as shown in FIG.

Note that by appropriately setting the values of the resistor R4 of the discharging circuit 2 and the resistor R5 of the charging circuit 3, the output waveform can be made into an accurate triangular wave or a sawtooth wave.

Further, the values of the upper limit v2 and lower limit v1 of the output waveform can be freely set by the values of the resistors R1 to R3.

come.

That is, as mentioned above, R3 is included in the formula for determining the lower limit set value V1, and R3 is included in the formula for determining the upper limit set value v2.
is not included, the upper limit and lower limit can be set to arbitrary values completely independently.

Next, FIG. 3 shows another embodiment of the present invention.

In FIG. 3, when the capacitor C2 is discharged, the output voltage VOUT is high, and therefore the base potential of the transistor Q of the variable set value comparison circuit 1 is also high.
Transistor Q5 is off.

When the transistor Q5 is turned off, the transistor Q6 is turned on, so that the emitter terminal voltage of the transistor Q becomes a value obtained by dividing the power supply voltage VOO by the parallel circuit of the resistors R7 and R8 and the resistor R6.

The set value at this time is the lower limit set value v1.

In other words, the lower limit setting value v1 is Vl-VCo''R7R
8/(R6R7+R7Rs+R3Ra).

Also, when transistor Q6 is turned on, transistor Q
7 is turned on and transistor Q8 is turned off, so that transistor Q9 of discharge circuit 2 is turned off and transistor QIO of charging circuit 3 is turned on.

When the transistor Q1o is turned on, the capacitor C2 is charged, and the output voltage VOUT decreases accordingly.

When the output voltage VOUT falls to the lower limit set value v1, transistor Q is turned on, so that transistor Q6
is turned off.

When transistor Q6 is turned off, the emitter terminal voltage of transistor Q is equal to the power supply voltage vcc and resistors R6 and R.
7 and becomes the value obtained by dividing the pressure, which is higher than in the previous case.

The set value at this time is the upper limit set value v2.

In other words, the upper limit setting value V2 is: ■2″-.vcc-R7/
(R6+R7).

Also, when transistor Q6 is turned off, transistor Q
7 is off and transistor Q8 is on, so transistor Q9 is on and transistor Q1o is off.

When the transistor QIO turns off, the charging circuit 3 is cut off, and since the transistor Q is turned on again, the discharging circuit 2
becomes conductive, and the charge in the capacitor C2 is discharged.

The charge of capacitor C2 is discharged and the output voltage VOTJT
increases and when the value reaches the upper limit set value V2, the transistor Q5 is turned off, and the above operation is repeated thereafter.

Other operations are similar to those in the example shown in FIG.

As explained above, according to the present invention, a triangular wave can be generated with a simple circuit using one comparison circuit, and the triangular waveform, upper and lower limit values, etc. can be freely set.
That is, there is an effect that a desired value can be easily and accurately set.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram of output waveforms, and FIG. 3 is a diagram of another embodiment of the present invention. Explanation of symbols, 1...Variable set value comparison circuit, 2.
...Discharge circuit, 3...Charging circuit, 4...
...Output terminal, C1...Capacitor.

Claims (1)

[Claims] °1 A capacitor with one end connected to a power supply and the other end connected to an output terminal, a first transistor switching circuit that short-circuits the capacitor through a first resistor during operation, and a second transistor switching circuit that connects the output terminal to a second resistor during operation. a second transistor switching circuit which is grounded via the first transistor switching circuit;
and when the third transistor switching circuit is in the first state, the voltage at the comparison input terminal is changed to the power supply voltage to the third resistor. When the first set voltage is divided by the fourth resistor and the first transistor switching circuit is operated, and when the third transistor switching circuit is in the second state, the fourth resistor is set to the fifth set voltage. and a fourth transistor switching circuit that connects the resistors in parallel to set the first set voltage as a second set voltage and operates the second transistor switching circuit,
An oscillator configured to output from the output terminal a signal having a waveform that reciprocates between the first set voltage and the second set voltage.