JPS5939919B2 - multilayer wiring board - Google Patents

multilayer wiring board

Info

Publication number
JPS5939919B2
JPS5939919B2 JP56130673A JP13067381A JPS5939919B2 JP S5939919 B2 JPS5939919 B2 JP S5939919B2 JP 56130673 A JP56130673 A JP 56130673A JP 13067381 A JP13067381 A JP 13067381A JP S5939919 B2 JPS5939919 B2 JP S5939919B2
Authority
JP
Japan
Prior art keywords
pattern
wiring
surface layer
layers
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56130673A
Other languages
Japanese (ja)
Other versions
JPS5832498A (en
Inventor
克己 矢部
貢 枝川
重久 宇野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Computer Engineering Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Computer Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Computer Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP56130673A priority Critical patent/JPS5939919B2/en
Publication of JPS5832498A publication Critical patent/JPS5832498A/en
Publication of JPS5939919B2 publication Critical patent/JPS5939919B2/en
Expired legal-status Critical Current

Links

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  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 本発明は、電子計算機などに用いられる多層配線基板の
改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in multilayer wiring boards used in electronic computers and the like.

電子計算機をはじめとする電子装置では、集積回路など
の論理素子の相互配線や、回路基板の相互配線などを多
層配線基板を用いて行なう傾向にある。
In electronic devices such as electronic computers, there is a tendency to use multilayer wiring boards for mutual wiring of logic elements such as integrated circuits and mutual wiring of circuit boards.

特に、信号配線層が4層以上の基板を利用する機会が増
えつゝある。第1図は、信号配線層が4層の従来の基板
の概略構成である。
In particular, there are increasing opportunities to use substrates with four or more signal wiring layers. FIG. 1 is a schematic diagram of a conventional board having four signal wiring layers.

1a、Ic、Ie、Igが信号配線層であり、クロスト
ークの軽減や特性インピーダンスの制御などのために、
各信号配線層の間に電源層lb、ld、Ifが介挿され
ている。
1a, Ic, Ie, and Ig are signal wiring layers, and in order to reduce crosstalk and control characteristic impedance,
Power supply layers lb, ld, and If are interposed between each signal wiring layer.

信号配線層1a、lc、le、lgのパターン2の走る
方向は、図示のように、X方向、Y方向、X方向、Y方
向と交互に変化させてある。そして、信号配線層1a(
上側の表面層)と信号配線層lc(表面層1aに対応の
内層)のパターン間を必要に応じて経由孔(スルーホー
ル)で相互接続し、下側の表面層lgとそれに対応の内
層Ieのパターン間を必要に応じて経由孔を通じて接続
する方法により、必要な配線を達成する。さて、このよ
うな多層配線基板に搭載する主要な部品、例えば、コネ
クタ類や集積回路、集積回路のソケットなどは、一般に
細長い形をしており、その端子ピンは長手方向に一列な
いし2列に配列されている。
The running directions of the patterns 2 of the signal wiring layers 1a, lc, le, and lg are alternately changed to the X direction, the Y direction, the X direction, and the Y direction, as shown in the figure. Then, the signal wiring layer 1a (
The patterns of the upper surface layer) and the signal wiring layer lc (the inner layer corresponding to the surface layer 1a) are interconnected by via holes as necessary, and the patterns of the lower surface layer lg and the corresponding inner layer Ie are interconnected as necessary. The necessary wiring is achieved by connecting the patterns through via holes as necessary. Now, the main components mounted on such multilayer wiring boards, such as connectors, integrated circuits, and sockets for integrated circuits, are generally long and thin, and their terminal pins are arranged in one or two rows in the longitudinal direction. Arranged.

このような搭載部品は、実装スペース等の面から、向き
を揃えて、幅方向に並べて配置するのが普通である。つ
まり、第2図に示すように、多層配線基板3のX方向に
部品4が多数個配列し、Y方向には限られた個数の部品
4が並ぶ。ところで、多層配線基板のパターン設計に際
しては、信号経路をできるだけ短縮することは勿論であ
るが、さらに次のような点に留意しなければならない。
まず、部品の端子ピンが挿入されるピン孔に接続する配
線パターンは、少なくとも一部を表面層に出す必要があ
る。これは、表面層のパターンを必要に応じて切断する
ことにより、パターン設計後の配線変更を容易に行ない
得るようにするためである。実際、電子計算機などは、
設計後に部分的な論理変更を要することが多く、パター
ン切断による配線変更の必要が生じるケースが少なくな
い。また、配線パターンの表面層への露出位置は、それ
が接続するピン孔の近傍に選ぶことが望ましい。
In view of mounting space and the like, such mounted components are generally arranged in the same direction and lined up in the width direction. That is, as shown in FIG. 2, a large number of components 4 are arranged in the X direction of the multilayer wiring board 3, and a limited number of components 4 are arranged in the Y direction. By the way, when designing a pattern for a multilayer wiring board, it goes without saying that the signal path should be shortened as much as possible, but the following points must also be kept in mind.
First, at least a portion of the wiring pattern connected to the pin hole into which the terminal pin of the component is inserted needs to be exposed on the surface layer. This is to facilitate wiring changes after pattern design by cutting the surface layer pattern as necessary. In fact, electronic computers, etc.
It is often necessary to partially change the logic after designing, and there are many cases where it is necessary to change the wiring by cutting the pattern. Further, it is desirable that the exposed position of the wiring pattern on the surface layer be selected near the pin hole to which it is connected.

これは、配線パターンの切断位置をピン孔に近づけ、そ
の切断位置からピン孔までの間に残るパターン(残余パ
ターン)の長さをできるだけ短くするためである。配線
パターンをピン孔から遠い位置で表面層に出すと、その
位置で配線パターンを切断した場合、必然的に長い残余
パターンが生じる。この残余パターンは表面層でなく内
層にあるため、除去が不可能である。そして、長い残余
パターンが存在すると、それに接続した配線パターン上
のパルスの波形を歪ませたり、伝播遅延時間を増加させ
るなどの悪影響を及ぼすことがあるOさて、第1図に示
した従来の基板に第2図のように部品を配置して搭載す
る場合、以上に述べた諸点を考慮してパターン設計しよ
うとすると、次のような問題が生じる。
This is to bring the cutting position of the wiring pattern closer to the pin hole and to shorten the length of the pattern (residual pattern) remaining between the cutting position and the pin hole as much as possible. If the wiring pattern is exposed on the surface layer at a position far from the pin hole, a long residual pattern will inevitably be produced when the wiring pattern is cut at that position. This residual pattern is not on the surface layer but on the inner layer and cannot be removed. If a long residual pattern exists, it can have negative effects such as distorting the waveform of the pulse on the wiring pattern connected to it and increasing propagation delay time. Now, the conventional board shown in Figure 1 When components are arranged and mounted as shown in FIG. 2, if a pattern is designed taking the above-mentioned points into consideration, the following problems arise.

第2図のような部品配置の場合、X方向への信号の流れ
が、Y方向への信号の流れより圧倒的に多くなるのが普
通である。
In the case of a component arrangement as shown in FIG. 2, the signal flow in the X direction is normally overwhelmingly larger than the signal flow in the Y direction.

したがつて、上側の表面層1aとそれに対応する内層1
cのパターンの様子は例えば第3図のようになる。第3
図において、白丸5はピン孔、太い実線6は表面層1a
上のパターン、破線7は内層1c上のパターンである。
Therefore, the upper surface layer 1a and the corresponding inner layer 1
The appearance of the pattern c is, for example, as shown in FIG. Third
In the figure, white circles 5 indicate pin holes, and thick solid lines 6 indicate surface layer 1a.
The upper pattern, broken line 7, is the pattern on the inner layer 1c.

また、表面層パターンと内層パターンとの接続は経由孔
(スルーホール)にスルーホールピンを打つて行なうが
、スルーホールピンを黒丸8で示す。前述のように、信
号の流れはY方向よりX方向が圧倒的に多いから、ピン
孔間の相互接続のための配線パターンの大部分はX方向
に走る。
Further, the surface layer pattern and the inner layer pattern are connected by inserting a through hole pin into a via hole (through hole), and the through hole pin is indicated by a black circle 8. As mentioned above, since the signal flow is overwhelmingly greater in the X direction than in the Y direction, most of the wiring patterns for interconnecting pin holes run in the X direction.

また、上側の表面層のパターン方向はx方向である。し
たがつて、図からも容易に理解できるように、大部分の
配線パターンを表面層に形成することができ、前述のパ
ターン設計上の諸条件を容易に満すことができる。しか
し、下側の表面層1gとその内層1eについては、上記
の諸条件を満足したパターン設計を行なうのは容易でな
い。
Further, the pattern direction of the upper surface layer is the x direction. Therefore, as can be easily understood from the figure, most of the wiring patterns can be formed on the surface layer, and the conditions for pattern design described above can be easily satisfied. However, it is not easy to design a pattern that satisfies the above conditions for the lower surface layer 1g and its inner layer 1e.

これについて、第4図により説明する。なお、符号は第
3図と同様であり、5はピン孔、6は表面層パターン、
7は内層パターン、8はスルーホールピンを示す。下側
の表面層1gのパターン方向はY方向である。
This will be explained with reference to FIG. Note that the symbols are the same as in FIG. 3, 5 is a pin hole, 6 is a surface layer pattern,
7 indicates an inner layer pattern, and 8 indicates a through-hole pin. The pattern direction of the lower surface layer 1g is the Y direction.

したがつて、配線パターンをピン孔の近傍で表面層に出
そうとすると、圧倒的に本数の多いX方向への信号流れ
用の配線パターンは、図示のように、Y方向の表面層パ
ターンとX方向の内層パターンとを組合せて形成しなけ
ればならず、迂回による配線パターン長の増加を伴ない
、また、信号の伝播遅延時間の増加の原因になる。この
迂回が多いこと\、表面層と内層間のパターン接続のた
めの経由孔を多数必要とすることから、パターン化率の
低下を余儀なくなれることが多い。さらに、全ての配線
パターンを接続ピン孔の近傍で表面層に出すことは、実
際上不可能になることが多く、配線変更が困難になつた
り、パターン切断時に長い残余パターンが生じ易くなる
。したがつて本発明の目的は、上に述べたような従来の
多層配線基板の欠点を解決した多層配線基板を提供する
ことにある。
Therefore, when attempting to expose the wiring pattern to the surface layer near the pin hole, the wiring pattern for signal flow in the X direction, which has an overwhelmingly large number of wires, is different from the surface layer pattern in the Y direction, as shown in the figure. It must be formed in combination with the inner layer pattern in the X direction, which causes an increase in the wiring pattern length due to the detour, and also causes an increase in signal propagation delay time. Since there are many detours and a large number of via holes are required for pattern connection between the surface layer and the inner layer, the patterning rate is often unavoidable. Furthermore, it is often practically impossible to expose all the wiring patterns to the surface layer in the vicinity of the connection pin holes, making it difficult to change the wiring and easily leaving long residual patterns when cutting the patterns. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multilayer wiring board that solves the drawbacks of the conventional multilayer wiring board as described above.

この目的を達成するために、本発明の主たる特徴は、多
層配線基板の上下いずれの表面層についても、主要な搭
載部品のピン配列方向と直交する方向にパターンを走ら
せる点にある。
In order to achieve this object, the main feature of the present invention is that patterns are run in the direction perpendicular to the pin arrangement direction of the main mounted components on both the upper and lower surface layers of the multilayer wiring board.

第5図に、本発明による多層配線基板の一例を示す。FIG. 5 shows an example of a multilayer wiring board according to the present invention.

同図において、主要な搭載部品のピン配列方向をY方向
として、上側の表面層である信号配線層10a1および
下側の表面層である信号配線層10gでは、パターン2
はX方向に走らせる。
In the figure, the pin arrangement direction of the main mounted components is the Y direction, and in the signal wiring layer 10a1 which is the upper surface layer and the signal wiring layer 10g which is the lower surface layer, the pattern 2 is
runs in the X direction.

表面層10a,10gのそれぞれに対する内層である信
号配線層10c,10eのパターン2はY方向に走らせ
る。10b,10d,10fはいずれも電源層である。
Pattern 2 of signal wiring layers 10c and 10e, which are inner layers for surface layers 10a and 10g, respectively, runs in the Y direction. 10b, 10d, and 10f are all power supply layers.

尚、上記の各層の間は図示してない絶縁物の層によつて
絶縁されることは勿論である。しかして、当該本発明の
基板に第2図に示すような配置で部品を搭載した場合、
上側の表面層10aとその対応内層10cの組、および
下側の表面層10gとその対応内層10eの組は、いず
れも、第1図の従来基板の上側表面層と対応内層の組に
おけるパターン設計上は同条件とみなし得る。
It goes without saying that the above-mentioned layers are insulated by an insulating layer (not shown). However, when components are mounted on the board of the present invention in the arrangement shown in FIG.
The set of the upper surface layer 10a and its corresponding inner layer 10c and the set of the lower surface layer 10g and its corresponding inner layer 10e are both pattern designs in the set of the upper surface layer and its corresponding inner layer of the conventional substrate in FIG. The above can be considered to be the same condition.

したがつて、第4図に示したような不利な配線パターン
を避け、第3図に示したような好ましい配線パターンの
設計が可能となる。故に、従来の基板における諸問題を
容易に解決できる。なお、上記の実施例は信号配線層が
4層であつたが、3層または5層以上の基板についても
、同様に本発明を適用して効果を挙げ得ることは勿論で
ある。また、上記実施例に示した本発明の特徴点以外の
構成は、従来と同様でよい。以上に述べたように、本発
明によれば、信号の伝播特性等に関する要求は勿論のこ
と、配線変更に関する要求も満した配線パターンを持ち
、かつパターン化率を向上した多層配線基板を容易に実
現でき、その効果は顕著である。
Therefore, it is possible to avoid an unfavorable wiring pattern as shown in FIG. 4 and to design a preferable wiring pattern as shown in FIG. 3. Therefore, various problems with conventional substrates can be easily solved. Although the above embodiment has four signal wiring layers, it goes without saying that the present invention can be similarly applied to a substrate with three or five or more layers and produce the same effect. Further, the configuration other than the feature points of the present invention shown in the above embodiments may be the same as the conventional one. As described above, according to the present invention, it is possible to easily create a multilayer wiring board that has a wiring pattern that satisfies not only the requirements regarding signal propagation characteristics but also the requirements regarding wiring changes and has an improved patterning rate. It can be achieved and the effect is remarkable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の多層配線基板の一例の概略構成を示す図
、第2図は多層配線基板上の一般的な部品配置を示す図
、第3図は第1図の従来基板の上側の表面層とその対応
内層における配線パターンの一例を示す図、第4図は第
1図の従来基板の下側の表面層と対応内層における配線
パターンの一例を示す図、第5図は本発明による多層配
線基板の一例の概略構成を示す図である。 2・・・・・・パターン、4・・・・・・搭載部品、5
・・・・・・ピン孔、6・・・・・・表面層パターン、
7・・・・・・内層パターン、8・・・・・・スルーホ
ールピン、10a,10c,10e,10g・・・・・
・信号配線層、10b,10d,10f・・・・・・電
源層。
Figure 1 is a diagram showing a schematic configuration of an example of a conventional multilayer wiring board, Figure 2 is a diagram showing a general arrangement of components on a multilayer wiring board, and Figure 3 is the upper surface of the conventional board in Figure 1. FIG. 4 is a diagram showing an example of the wiring pattern in the lower surface layer and the corresponding inner layer of the conventional board of FIG. 1. FIG. 5 is a diagram showing an example of the wiring pattern in the layer and its corresponding inner layer. FIG. FIG. 1 is a diagram showing a schematic configuration of an example of a wiring board. 2...Pattern, 4...Mounted parts, 5
...Pin hole, 6...Surface layer pattern,
7...Inner layer pattern, 8...Through hole pin, 10a, 10c, 10e, 10g...
- Signal wiring layer, 10b, 10d, 10f... power supply layer.

Claims (1)

【特許請求の範囲】[Claims] 1 配線層を複数層積層した多層配線板において、最上
層と最下層に位置し、外部に露出する2つの配線層(外
部配線層)のパターンを同一方向に、しかも、該多層配
線基板に搭載される主要部品のピン配列方向と直交する
方向に走らせるとともに、前記2つの外部配線層と各々
相対する内部配線層のパターンを、前記主要搭載部品の
ピン配列方向と平行に走らせたことを特徴とする多層配
線基板。
1 In a multilayer wiring board in which multiple wiring layers are laminated, the patterns of two wiring layers (external wiring layers) located at the top and bottom layers and exposed to the outside are mounted in the same direction and on the multilayer wiring board. The pattern of the internal wiring layer facing each of the two external wiring layers runs parallel to the pin arrangement direction of the main mounted components. Multilayer wiring board.
JP56130673A 1981-08-20 1981-08-20 multilayer wiring board Expired JPS5939919B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56130673A JPS5939919B2 (en) 1981-08-20 1981-08-20 multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56130673A JPS5939919B2 (en) 1981-08-20 1981-08-20 multilayer wiring board

Publications (2)

Publication Number Publication Date
JPS5832498A JPS5832498A (en) 1983-02-25
JPS5939919B2 true JPS5939919B2 (en) 1984-09-27

Family

ID=15039873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56130673A Expired JPS5939919B2 (en) 1981-08-20 1981-08-20 multilayer wiring board

Country Status (1)

Country Link
JP (1) JPS5939919B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017199879A (en) * 2016-04-28 2017-11-02 富士通株式会社 Wiring board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS563972U (en) * 1979-06-21 1981-01-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS563972U (en) * 1979-06-21 1981-01-14

Also Published As

Publication number Publication date
JPS5832498A (en) 1983-02-25

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