JPS593869B2 - Method for manufacturing silicon gate field effect semiconductor device - Google Patents

Method for manufacturing silicon gate field effect semiconductor device

Info

Publication number
JPS593869B2
JPS593869B2 JP13587275A JP13587275A JPS593869B2 JP S593869 B2 JPS593869 B2 JP S593869B2 JP 13587275 A JP13587275 A JP 13587275A JP 13587275 A JP13587275 A JP 13587275A JP S593869 B2 JPS593869 B2 JP S593869B2
Authority
JP
Japan
Prior art keywords
silicon gate
silicon
field effect
boron
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13587275A
Other languages
Japanese (ja)
Other versions
JPS5260080A (en
Inventor
泰一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13587275A priority Critical patent/JPS593869B2/en
Publication of JPS5260080A publication Critical patent/JPS5260080A/en
Publication of JPS593869B2 publication Critical patent/JPS593869B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はシリコンゲート型電界効果半導体装置の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a silicon gate field effect semiconductor device.

多結晶シリコンを用いる電界効果トランジスタ(以下M
OSと称す)は通称シリコンゲートMOSとして知られ
ており、この多結晶シリコンは特別な場合を除き不純物
を含まない絶縁体であり、必要に応じて不純物としてリ
ン、ボロンさらにはヒ素、ガリウムなどが拡散もしくは
ドーピングなどの技術により、又はイオン注入技術等に
より多結晶シリコン中に添加され導電体として使用され
る。
Field effect transistor using polycrystalline silicon (hereinafter referred to as M
OS) is commonly known as silicon gate MOS, and this polycrystalline silicon is an insulator that does not contain impurities except in special cases, and if necessary, phosphorus, boron, arsenic, gallium, etc. are added as impurities. It is added to polycrystalline silicon by techniques such as diffusion or doping, or by ion implantation techniques, and is used as a conductor.

一般にこの不純物の撰択としてNチヤンネルシリ5 コ
ンゲートM05にはリンが、そしてPチャンネルシリコ
ンゲートにはボロンが常識であり、ほとんどの場合がシ
リコン基板への不純物拡散の時に同時に多結晶シリコン
中へ拡散される。特別な場合として基板に拡散する不純
物と異なるものが多10結晶シリコン中へ拡散される事
もあるがいずれの場合も多結晶シリコン中には単一の不
純物しか含まれない。この様に、多結晶シリコン中に単
一の不純物特にボロンが含まれている場合は、後述する
如く、そのMOSの特性を劣化させる原因とな15つて
いる。本発明の目的は特性の安定なシリコンゲートMO
Sの製造方法を提供することである。
Generally, the selection of impurities is phosphorus for the N-channel silicon gate M05 and boron for the P-channel silicon gate, and in most cases, when the impurity is diffused into the silicon substrate, it is simultaneously diffused into the polycrystalline silicon. be done. In special cases, an impurity different from that diffused into the substrate may be diffused into the polycrystalline silicon, but in either case, only a single impurity is contained in the polycrystalline silicon. In this way, when a single impurity, particularly boron, is contained in polycrystalline silicon, it becomes a cause of deterioration of the characteristics of the MOS, as will be described later. The purpose of the present invention is to provide a silicon gate MO with stable characteristics.
An object of the present invention is to provide a method for manufacturing S.

本発明は多結晶シリコン中に含まれた二種類の不純物、
特にボロン及びリンが同時に含まれた時20の各不純物
の挙動についてゲート絶縁膜としてシリコン酸化膜を用
いた場合の新たな実験結果にもとずくものである。
The present invention deals with two types of impurities contained in polycrystalline silicon,
In particular, the behavior of each of the 20 impurities when boron and phosphorus are contained at the same time is based on new experimental results when a silicon oxide film is used as a gate insulating film.

PチャンネルシリコンゲートMOSを例にとると水素を
含む雰囲気、スチームを含む雰囲気でそ25れぞれ熱処
理するとMOSトランジスターのスレツシユホールド電
圧VTが第1図a、bに示す如く、負に大きくなる現象
が知られている。
Taking a P-channel silicon gate MOS as an example, when it is heat-treated in an atmosphere containing hydrogen and an atmosphere containing steam, the threshold voltage VT of the MOS transistor becomes negative as shown in Figure 1a and b. The phenomenon is known.

第1図においてVToはVTの初期値、をは熱処理時間
を示す。この現象は多結晶シリコン中に添加され30て
いる不純物のボロンがシリコン酸化膜中に熱的に拡散し
これが水素により加速されるためである。一方Nチャン
ネルシリコンゲートMOSを例にとるとPチャンネルシ
リコンゲートMOSに比べてはるかに安定であり熱処理
中のMOSトランジス35ターのスレツシユホールド電
圧の変化は見られない。これを第2図に示す。この事は
リンがシリコン酸化膜中にきわめて拡散されにくい事を
示している。一般にシリコン酸化膜にボロンが入るとガ
ラス層をつくるがボロンの存在によりシリコン酸化膜は
結晶化し易くなり膜密度が疎になり、一方リンを含んだ
シリコン酸化膜はより無定形になり膜密度が密になる事
が知られており上記現象もその効果として理解できる。
そこでボロンが拡散されたシリコン酸化膜にリンを拡散
したらどうなるかを第3図に示す。
In FIG. 1, VTo indicates the initial value of VT, and indicates the heat treatment time. This phenomenon occurs because boron, an impurity added to polycrystalline silicon, thermally diffuses into the silicon oxide film and is accelerated by hydrogen. On the other hand, taking an N-channel silicon gate MOS as an example, it is much more stable than a P-channel silicon gate MOS, and no change in the threshold voltage of the MOS transistor 35 is observed during heat treatment. This is shown in FIG. This shows that phosphorus is extremely difficult to diffuse into the silicon oxide film. Generally, when boron enters a silicon oxide film, it forms a glass layer, but the presence of boron makes the silicon oxide film easier to crystallize and the film density becomes sparse.On the other hand, a silicon oxide film containing phosphorus becomes more amorphous and has a lower film density. It is known that the density increases, and the above phenomenon can be understood as an effect of this.
FIG. 3 shows what happens when phosphorus is diffused into a silicon oxide film in which boron has been diffused.

図においてt′,T.″t′2はリン拡散時間を示し、
a′,a!a′〃はそれに対応したVTをそれぞれ示す
。即らリン拡散時を境として、その前でPチヤンネルシ
リコンゲートMOSの不安定さそしてその後でNチヤン
ネルシリコンゲートMOSの安定さが備つている。これ
は前記した様に一度ボロンにより疎になつたシリコン酸
化膜がリンにより再び密に変つたと考えて理解される。
本発明は第3図に示したこの新たな現象を半導体装置に
適用したものである。たとえばPチヤンネルシリコンゲ
ートMOSを例にとると多結晶シリコンゲートにはソー
ス及びトレインへの拡散と同時にボロンが添加される。
In the figure, t', T. "t'2 indicates phosphorus diffusion time,
a', a! a' indicates the corresponding VT. That is, with the phosphorus diffusion as a boundary, the P channel silicon gate MOS becomes unstable before that, and the N channel silicon gate MOS becomes stable after that. This can be understood by considering that the silicon oxide film, which had once become sparse due to boron, becomes dense again due to phosphorus, as described above.
The present invention applies this new phenomenon shown in FIG. 3 to a semiconductor device. For example, taking a P channel silicon gate MOS as an example, boron is doped into the polycrystalline silicon gate at the same time as it is diffused into the source and train.

その後シリコンゲートMOSの特徴である多層配線技術
を生かすために多結晶シリコンと他の配線電極との分離
のため多結晶シリコン上に絶縁被膜を形成しなければな
らない。このために熱酸化を行うとボロンが多結晶シリ
コンよりシリコン酸化膜へ侵入し酸化膜質を劣化せしめ
電荷トラツプをつくり高温バイアス処理での不安定さを
助長し、ついにはMOSトランジスターのスレツシユホ
ールド電圧の値を変化させてしまう事が知られている。
この効果は水素を含む雰囲気で行うとより顕著にあられ
れる。そこで現実には多結晶シリコンとシリコン酸化膜
との間にシリコン窒化膜などのボロンの不透過な膜をは
さみ込んだり低温で気相成長法での絶縁被膜の成長を行
うなどしている。本発明による.と、ゲート絶縁膜とし
てシリコン酸化膜を用いその上に多結晶シリコンゲート
を設けたシリコンゲート型電界効果半導体装置の製造方
法において、チヤンネルとなるべき基板表面にシリコン
酸化膜を通してボロンもしくはガリウムが導入される第
1の工程と、しかる後に多結晶シリコンゲートにリンを
導入する第2の工程とを有し、これにより所定の一定の
スレツシユホールド電圧を得ることを特徴とするシリコ
ンゲート型電界効果半導体装置の製造方法が得られる。
ボロンが熱処理でシリコン酸化膜を突き抜けるとMOS
トランジスターのスレツシユホールド電圧が変化する。
After that, in order to take advantage of the multilayer wiring technology that is a feature of silicon gate MOS, an insulating film must be formed on the polycrystalline silicon to separate the polycrystalline silicon from other wiring electrodes. For this reason, when thermal oxidation is performed, boron invades the silicon oxide film from polycrystalline silicon, deteriorates the oxide film quality, creates charge traps, promotes instability in high temperature bias processing, and finally reduces the threshold voltage of the MOS transistor. It is known that the value of
This effect is more pronounced when the process is carried out in an atmosphere containing hydrogen. In reality, therefore, a boron-impermeable film such as a silicon nitride film is sandwiched between the polycrystalline silicon and the silicon oxide film, or an insulating film is grown by vapor phase growth at low temperatures. According to the present invention. In a method for manufacturing a silicon gate field effect semiconductor device in which a silicon oxide film is used as a gate insulating film and a polycrystalline silicon gate is provided thereon, boron or gallium is introduced through the silicon oxide film onto the surface of the substrate that is to become a channel. A silicon gate field effect semiconductor comprising a first step of introducing phosphorus into a polycrystalline silicon gate, and a second step of introducing phosphorus into a polycrystalline silicon gate, thereby obtaining a predetermined constant threshold voltage. A method for manufacturing the device is obtained.
When boron penetrates the silicon oxide film through heat treatment, MOS
The threshold voltage of the transistor changes.

この現象を利用してMOSトランジスターのスレツシユ
ホールド電圧制御が可能である事が知られている。しか
しボロン添加だけでは前述したMOSトランジスターの
不安定性のため実用化が困難である。従つて本発明の実
施例によれば、多結晶シリコン成長時もしくは成長後に
各々ドーピング拡散で1018〜1019Adの濃度で
ボロンを多結晶シリコン中へ添加し続いて水素を含む雰
囲気で900℃〜1100℃の渦度で熱処理するボロン
はMOSトランジスターのチヤンネルとなるべき基板表
面にシリコン酸化膜を通して拡散される。
It is known that this phenomenon can be used to control the threshold voltage of a MOS transistor. However, the addition of boron alone is difficult to put into practical use due to the instability of the MOS transistor described above. Therefore, according to an embodiment of the present invention, boron is added to polycrystalline silicon at a concentration of 1018 to 1019 Ad during or after the growth of polycrystalline silicon, respectively, by doping diffusion, and then heated at 900°C to 1100°C in an atmosphere containing hydrogen. Boron, which is heat-treated at a vorticity of , is diffused through a silicon oxide film onto the surface of the substrate that is to become a channel of a MOS transistor.

適当な時間の後に1020/Cd程度の濃度で多結晶シ
リコンにリン拡散を行うとMOSトランジスターのスレ
ツシユホールド電圧は熱処理時間の平方根に比例して変
化してリン拡散以後の熱処理では変化しない。この様に
安定性のよい任意のMOSトランジスターが得られる。
この方法はPチヤンネルシリコンゲートMOSでも可能
であるがNチャンネルシリコンゲートMOSに適用する
と効果的である。以上実施例をリン−ボロン系について
記述したが本発明はリン−ガリウムなど適用しても有効
である。
When phosphorus is diffused into polycrystalline silicon at a concentration of about 1020/Cd after an appropriate period of time, the threshold voltage of the MOS transistor changes in proportion to the square root of the heat treatment time, and does not change during heat treatment after phosphorus diffusion. In this way, any MOS transistor with good stability can be obtained.
Although this method is possible with a P-channel silicon gate MOS, it is effective when applied to an N-channel silicon gate MOS. Although the above embodiments have been described for phosphorus-boron systems, the present invention is also effective when applied to phosphorus-gallium, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はPチャンネルシリコンゲートMOSの、そして
第2図はNチヤンネルシリコンゲートMOSの熱処理時
間の平方根とスレツシユホールド電圧の関係を示したも
ので、A,b,そしてCは各図において各々水素雰囲気
、スチーム雰囲気、そして不活性ガス雰囲気を示す。
Figure 1 shows the relationship between the square root of the heat treatment time and the threshold voltage for a P-channel silicon gate MOS and Figure 2 for an N-channel silicon gate MOS, where A, b, and C are respectively shown in each figure. Hydrogen atmosphere, steam atmosphere, and inert gas atmosphere are shown.

Claims (1)

【特許請求の範囲】[Claims] 1 ゲート絶縁膜としてシリコン酸化膜を用いその上に
多結晶シリコンゲートを設けたシリコンゲート型電界効
果半導体装置の製造方法において、チャンネルとなるべ
き基板表面にシリコン酸化膜を通してボロンもしくはガ
リウムが導入される第1の工程と、しかる後に多結晶シ
リコンゲートにリンを導入する第2の工程とを有し、こ
れにより所定の一定のスレツシユホールド電圧を得るこ
とを特徴とするシリコンゲート型電界効果半導体装置の
製造方法。
1. In a method for manufacturing a silicon gate field effect semiconductor device in which a silicon oxide film is used as a gate insulating film and a polycrystalline silicon gate is provided thereon, boron or gallium is introduced through the silicon oxide film into the surface of the substrate that is to become a channel. A silicon gate field effect semiconductor device comprising a first step and a second step of introducing phosphorus into a polycrystalline silicon gate, thereby obtaining a predetermined constant threshold voltage. manufacturing method.
JP13587275A 1975-11-12 1975-11-12 Method for manufacturing silicon gate field effect semiconductor device Expired JPS593869B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13587275A JPS593869B2 (en) 1975-11-12 1975-11-12 Method for manufacturing silicon gate field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13587275A JPS593869B2 (en) 1975-11-12 1975-11-12 Method for manufacturing silicon gate field effect semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP22732084A Division JPS60121770A (en) 1984-10-29 1984-10-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5260080A JPS5260080A (en) 1977-05-18
JPS593869B2 true JPS593869B2 (en) 1984-01-26

Family

ID=15161733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13587275A Expired JPS593869B2 (en) 1975-11-12 1975-11-12 Method for manufacturing silicon gate field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS593869B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07143912A (en) * 1993-11-22 1995-06-06 Yamato Esuron Kk Container for cosmetics

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54159186A (en) * 1978-06-07 1979-12-15 Fujitsu Ltd Semiconductor device
JPS6042865A (en) * 1983-08-18 1985-03-07 Nec Corp Mos type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07143912A (en) * 1993-11-22 1995-06-06 Yamato Esuron Kk Container for cosmetics

Also Published As

Publication number Publication date
JPS5260080A (en) 1977-05-18

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