JPS5937740Y2 - signal integrator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a signal integration device used in, for example, a radar signal processing device.

For example, when a signal with a limited number of hits is obtained superimposed on noise in synchronization with a radar trigger, such as in radar video, signal integration is used as a means for effectively detecting the signal superimposed on noise.

This is a technology that focuses on the characteristic that while noise is random, the signal is synchronized with the trigger, and therefore there is a correlation between the signals obtained for each trigger, and performs cumulative calculations on the signal to enhance only the signal. be.

By the way, a conventional signal integrator was constructed as shown in FIG.

That is, the input signal that is generated continuously for N cycles in synchronization with the trigger becomes one input of the adder 11, and the output signal of this adder 11 is delayed by one cycle by the delay device 12, and this delayed output signal is used for setting the feedback coefficient. After being multiplied by a certain number by the arithmetic circuit 13, it becomes the other input of the adder 11, and is added to the input signal of the next cycle.

Repeating this signal processing process enhances the periodic signal.

Therefore, for an input signal as shown in FIG. 2a, the output signal of the integrator will be as shown in FIG.

By the way, if noise is superimposed on the input signal as shown in FIG. 2A, the noise will also be amplified to some extent by repeating the signal processing process.

In other words, like the DC component (average value) Iri signal of input noise, there is a cumulative effect for each cycle, and the output signal of the integrator has a floating base as shown in Figure 2, and the noise level is lower than the input. This resulted in a raised shape, which caused a major inconvenience in signal processing.

For example, when an image of an integrated signal and an image of a non-integrated signal are switched and displayed on a radar scope, the noise levels of the two images are different and are difficult to see.

Alternatively, when a signal obtained by integration is displayed as an image, it becomes difficult to distinguish it from the image due to the noise level.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a signal integration device that can maintain the same noise level of an input signal and an output signal.

An embodiment of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, the signal integrator shown in FIG. 3 is different from the conventional signal integrator described above in that a subtracter 31, a reference calculation circuit 32, and an arithmetic circuit 33 are added, and the other points are the same. Therefore, the same reference numerals as in FIG. 1 are given in FIG. 3, and the explanation thereof will be omitted.

The reference calculation circuit 32 calculates the reference value of the input signal (see FIG. 4C).

This reference value may be a value that keeps the average value of noise, a value that keeps the false alarm rate Pfa, etc. constant, or a value that keeps the rate of time when noise exceeds a certain level constant, but there are other values that can be used for the calculation circuit 33. There may be various modifications depending on the calculation method.

The subtracter 31 converts the input signal into the reference calculation circuit 32.
Subtract the reference value level obtained in .

A signal that becomes negative as a result of this subtraction is truncated or treated as a negative signal.

The output signal of the subtracter 31 is transmitted to the adder 11 and the delay device 12.
, the arithmetic circuit 131C performs an integral calculation similar to the conventional one.

The output of this integral operation, that is, the output signal of the adder 11 (see FIG. 4) has a noise level lower than that of the input signal, and only the signal is enhanced.

This is because signals below the reference value are discarded before inputting to the adder 11.

Note that when handling negative signals, the negative signals may be discarded at the input of the arithmetic circuit 33 or processed within the arithmetic circuit 33.

By the way, the arithmetic circuit 33 synthesizes a part of the input signal and the output signal of the adder 11 in order to match the output noise level of the adder 11 with the input signal.

For example, among the input signals, a signal level below a reference value is derived from the reference calculation circuit 32, and this output signal and the adder 11
The arithmetic circuit 33 adds the output signals of .

As a result, the output signal from the arithmetic circuit 33 has the same noise level as the noise level of the input signal, although only the input signal that is repeated at a constant period is amplified.

Furthermore, even if the DC component is not completely removed from the input signal by the attenuator 31 and the reference calculation circuit 32, the calculation circuit 3
3 subtracts the DC component from the output of the adder 11 and outputs the result, so the output signal from the arithmetic circuit 33 has the same noise level as the input signal.

Therefore, even when the output signal of the arithmetic circuit 33 is displayed as an image and compared with the input signal, it is extremely easy to see on the screen.

The output of the arithmetic circuit 33 (see FIG. 4C) becomes the output of the signal integrator, but depending on how the reference value is calculated, the output of the adder 11 can also be used as is as the output of the arithmetic circuit 33. It is.

According to the signal integrator as described above, when only an input signal that repeats at a constant period is amplified and derived, the noise level of the output signal is set to be the same as the case where the signal is not amplified, that is, the same as the noise level of the input signal. can.

Therefore, if the signal integration device is applied to radar video signal processing, for example, and the integrated video is displayed on a radar scope, the noise level of the image will be the same as when the above device is not applied, and the display will be easy to see.

In addition, since the integrally processed video only emphasizes the signal and not the noise, the image display is easy to see.

As described above, the present invention can provide a signal integrator that can maintain the same noise level of the two input signals and the output signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional signal integrator, Fig. 2 a and b are signal waveform diagrams shown to explain the operation of Fig. 1, and Fig. 3 is an example of the signal integrator according to the present invention. Block diagram showing weekly example, see Figure 4C, c
2 is a signal waveform diagram shown for explaining the operation of FIG. 2. FIG. 11...Adder, 12...Delay device,
13--Arithmetic circuit, 31--Reference calculation circuit, 32--Subtractor.

Claims (1)

[Scope of utility model registration request] = A reference calculation circuit that calculates the reference value of an input signal that is repeated at regular intervals, a subtracter that subtracts the reference value level calculated by this circuit from the input signal, and an addition whose output signal from this subtracter is one input. a delay device that delays the addition output signal of the adder by one cycle; a first arithmetic circuit that multiplies the output of the delay device by a certain number and supplies the result as the other input of the adder; and an output of the adder. and a second arithmetic circuit that synthesizes the reference value level.