JPS593770A - Memory control circuit - Google Patents

Abstract

PURPOSE:To execute reading/writing operation irrespective of either in bit unit or fixed-length unit and to speed up data transfer, by supplying a mode signal for indicating bit mode or fixed-length mode together with a read/write signal to a memory control circuit. CONSTITUTION:The memory control circuit is equipped with a two-way bus driver 3 connected to a data bus and a two-way bus driver 4 connected to a memory 2, and a write control part 5, read control part 6, and bit address recorder 7 are provided between both drivers 3 and 4. A read/write signal line and a mode signal line are both connected to the circuit 1 and either a bit- mode signal or a fixed-mode signal is supplied to the mode signal line to perform read/write control in bit unit or fixed-length unit. Thus, the data transfer is performed finely and speeded up totally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory control circuit, and more particularly, to a memory control circuit that can arbitrarily perform reading and writing in units of fixed length and reading and writing in units of pits.

[Prior art and problems]

Conventional memory control circuits can only read from and write to memory in fixed length units such as bytes or words, or in bit units. Reading and writing data in fixed length units allows high-speed data reading and writing, but does not allow fine-grained control.

On the other hand, bit-by-bit memory reading and writing allows for fine-grained control, but has the disadvantage that data cannot be sent out at high speed.

[Purpose of the invention]

The present invention solves the above-mentioned problems, and provides a memory control circuit that can read and write to memory in units of fixed length or bits, and can transfer data in detail and at overall high speed. The purpose is to

[Structure of the invention]

To this end, the memory control method of the present invention includes a first bidirectional bus driver, a second bidirectional bus driver, a read control section, a write control section, and a bit address decoder, The second bidirectional bus driver and the second bidirectional bus driver transmit read data from the memory from the second bidirectional bus driver to the first bidirectional bus driver through the read control section in response to a read signal. The write data is output to the data bus side, and in response to a write signal, the write data from the data bus is passed from the first bidirectional bus driver through the entire write control section to the memory side of the second bidirectional bus driver. In the memory control circuit that can now be switched to output, the write control section receives the select signal of the bit address decoder, the mode signal of either bit mode or fixed length mode, and the data in the memory. is given, and the write control unit transfers all bit data inputted from the first bidirectional bus driver to the second bidirectional bus driver on the condition that a fixed length mode mode signal is given. The bit selected by the select signal of the bit address decoder is output to the bus driver, and on the condition that the bit mode mode signal is given, the bit selected by the select signal of the bit address decoder is the data input from the first bidirectional bus driver. , the said
The bits other than the bits transfer the data of the corresponding bits given from the memory to the second bidirectional bus.
The read control unit is configured to output a bit address decoder select signal and a mode signal whose bit mode is a fixed length mode, and the read control unit is configured to output a fixed length mode to the read control unit. On the condition that a long mode mode signal is given, all bit data inputted from the second bidirectional bus driver is output to the first bidirectional bus driver, and the bit mode is set. On the condition that the signal is applied, the bit data selected by the select signal of the bit address decoder among the data input from the second bidirectional bus driver is transferred to the first bidirectional bus driver. It is characterized in that it is configured to output to a driver.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a memory control circuit, FIG. 3 is a block diagram showing an overview of the configuration of a write control section, and FIG. FIG. 5 is a diagram showing an example of a specific configuration of a control section, FIG. 5 is a diagram showing an example of a specific configuration of a gate circuit used in a write control section, and FIG. 6 is an overview of the configuration of a read control section. The block diagram shown in FIG. 7 is a diagram showing one example of a specific configuration of the readout control section. In the figure, 1 is a memory control circuit; 2 is a memory control circuit;
are memories, 3 and 4 are bidirectional bus drivers, 5 is a write control section, 6 is a read control section, 7 is a bit address φ decoder, 8-0 to 8-le are write switching circuits, 9 is a gate circuit, 10-0 to 1°, 11-0 to 1
1-n, 20-0 to 20-n and 25 are or gates, 12-o to 12-n, 13-0 to 13-FL
ll 5-0 to 15-n, 17-0 to 17-n
, 21-0 to 21-n, 22-0 to 22- and 24-〇 to 24- are AND gates, 14-0 to 14-n, 18-0 to 18-n and 23-〇 to 23 -n is an inverter, 16-0 to 16- are tri-state gates, and 19-0 to 19- are read switching circuits.

In the present invention, as shown in FIG. 1, a memory 2 is connected to a data bus through a memory control circuit 1, and a bit mode signal or fixed One of the long mode signals is applied to the memory control circuit 1, and in the bit mode, the bit address is applied to the memory control circuit 1 along with the bit mode signal from the address bus. The memory control circuit 1 controls bit-by-bit reading and writing between the data bus and the memory 2 based on the bit mode signal and the bit address, and controls the bit-by-bit reading and writing between the data bus and the memory 2 based on the fixed length mode signal. Controls reading and writing in fixed length units.

FIG. 2 shows the configuration of the memory control circuit 1. In FIG. 2, the memory control circuit 1 includes a bidirectional bus driver 3 on the data bus side connected to the data bus and a bidirectional bus driver 4 on the memory side connected to the memory 2.
and a write control unit 5 and a read control unit 6 connected between the two bidirectional bus drivers 3 and 4, and a bit address for decoding the bit address sent from the address bus. It is equipped with a decoder 7. In the bidirectional bus drivers 3 and 4, when a read signal is sent, the data bus and the memory 2 are connected through the read control section 6, and when a write signal is sent, the data bus is connected through the write control section 5. Switching is performed so that the bus and the memory 2 are connected.A bit mode signal or a fixed length mode signal is supplied from the mode signal line to the write control unit 5 and read control unit 6, and the bit address - A select signal is also supplied to the decoder 7. Furthermore, the data of each bit in the memory 2 is supplied to the write control unit 5. Then, when the signal on the mode signal line is logic "1", the bit Fixed length mode is entered when the logic ``0'' is selected.In bit mode writing, the select signal of the bit address decoder 7 is a logic ``1'' bit of the data from the data bus. The data is output as is to the memory 2 side, and for other bits other than this bit, the original data in the memory 2 is output as is to the memory 2 side.In bit mode reading, select bit address decoder 7 The signal is logic “1”
bit data is output from memory 2 to the data bus. In addition, in fixed length mode, all bits of data from the data bus are output as is to the memory 2 side for either writing or reading, or all bits of read data from memory 2 are output to the data bus. . In this manner, as is clear from FIG. 1, writing and reading are performed in the memory 2 in units specified by the fixed length address section. Note that in FIG. 2, the fixed length is +1 bit.

FIG. 3 shows an outline of the configuration of the write control section 5. As shown in FIG. The write switching circuits 8-0 to 8- are provided corresponding to bits, and are connected to the data line from the data bus and the memory through the mode signal line, the select signal line of the bit address decoder 7, and the bidirectional bus driver 3, respectively. 2
The data lines of each bit in the data line are connected to each other. In the bit mode, only the write switching circuits 8-0 to 8-n for which the select signal of the bit address decoder 7 is logic "1" transfer data from the data bus to the memory 2.
The write switching circuits 8-0 to 3-n for the other bits output the data in the memory 2 to the memory 2. Therefore, the write data to memory 2 is
Although one bit is supplied at the same time, data from the data bus is actually written only to the bit for which the select signal of the bit address decoder 7 is logic "1".

In addition, in the fixed length mode, regardless of the select signal of the bit address decoder 7, the write switching circuit 8-
All 0 through 8-n output data from the data bus to memory 2. 1. Specific configuration of write control unit
FIG. 4 shows an example. In Figure 4, beep)
0 write switching circuit 8-0 is connected to AND gate 12-0.
13-0 and 15-0, OR gates 10-0 and 11-0, an inverter 14-0, and a part of gate circuit 9.

Looking at the circuit for bit 0, the data line from the data bus is connected to one input terminal of ANDG 15-0 and one input terminal of ANDG 12-0, and the data line from the data bus is connected to one input terminal of ANDG 12-0. The select signal line 7 is connected to the other input terminal of the AND gate 15 and the gate circuit 9, and the mode signal line is connected to the input terminal of the inverter 14-0, one input terminal of the AND gate 13-0, and the gate circuit 9. Connected to 9.

The other input terminal of the AND game) 12-0 is connected to the output terminal of the inverter 14-0, and the AND game) 12-0 is connected to the output terminal of the inverter 14-0.
The output terminal of 0 is connected to one input terminal of OR game 11-0. The other input terminal of AND game) 13-0 is connected to the output terminal of AND game) 15-0,
AND gate 13-00 output terminal is OR gate 11
-0 is connected to the other input terminal. or gate 11
The output terminal of -0 is connected to one input terminal of OR gate 10-0, and the output terminal of the corresponding bit of gate circuit 9 is connected to the other input terminal of OR gate 10-0. With the above connection configuration, in the bit mode, the mode signal line is logic "1", so the select signal of pin 0 of the bit address decoder 7 is logic "1".
1, the data is transferred from OR gate 11-0 to 10-0 through AND gates 15-0 and 13-0.
Data from the bus is output to memory 2, and vice versa.
When the select signal of bit O of address decoder 7 is logic "0", the data of bit O in memory 2 is output to OR gate 10-0 through gate circuit 9. The same original data is written and retained. In the case of fixed length mode, since the mode signal line is logic rOJ, inverter 1 is connected to the mode signal line.
Data from the data bus is output from AND gate 12-0, whose input terminal is connected through 4-O, to OR gate 11-0.10-0. Below, bit 1
The same applies to bits 0 to 0. Therefore, in the bit mode, AND gates 15-0 to 15-r are activated only for bits for which the select signal of bit address decoder 7 is logic "1".
L, 13-0 to 13-fL, or gate 11-0
Data from the data bus is written to the memory 2 through the lines 10-0 to 11- and 10-0 to 10-, and the other bits are written to the memory 2 from the gate circuit 9 to the OR gate lO.
- The original data in the memory 2 is written again through 10-n. The gate circuit 9 has an input terminal to which the data line of each bit in the memory 2 is connected, and an OR gate) 1.
A tristate gate is provided between the output terminal and the output terminal to which the other input terminal of 0-0 to 10-3 is connected.

As shown in FIG. 5 as an example of a specific configuration, tristate gates 16-0 to 16-n are controlled by the outputs of AND gates 17-0 to 17-n.

17-0 to 17-n have one input terminal commonly connected to the mode signal line, and the other input terminal inputs the corresponding bit address and input signal through inverters 18-o to 1s-n, respectively. It is connected to the select signal terminal of the decoder 7. With this connection configuration, when the mode signal line becomes logic "1" to indicate the bit mode, only the tristate gate corresponding to the bit whose select signal from the bit address decoder 7 is logic "1" is activated. When the mode signal line is set to a high impedance state and the mode signal line becomes logic "0" to indicate the fixed length mode, the logic condition is not satisfied for all of the AND gates 17-0 to 17-, and all tri-state lines are Gates 16-0 through 16-n are placed in a high impedance state.

FIG. 6 shows an outline of the configuration of the readout control section 6. In FIG. 6, the readout switching circuit 19
-xi:c to 19- are provided corresponding to bits, and each is connected to a mode signal line, a select signal line of the bit address decoder 7, and a data line from the memory 2 through the bidirectional path driver 4. . When the mode signal line becomes logic "1" and the bit mode is set, the select signal of the bit address decoder 7 is set to logic rlJ, so that only the bit read switching circuits 19-1 to 19-1 select the read data of the memory 2. output to the data bus,
When the mode signal line becomes logic "0" and the fixed length mode is set, all of the read switching circuits 19-1 to 19-n output read data from the memory 2 to the data bus. The seventh example shows an example of a specific configuration of the read control unit.
It is a diagram. In FIG. 7, the read switching circuit 19-o for bit 0 is connected to the AND gate 21-0.22-0.24-
0, an OR gate 20-0, an inverter 23-0, and a part of the OR gate 25. Looking at the circuit related to bit 0, the data line from the memory is connected to one input terminal of the AND game (24-00) and the AND game.
121-0, the select signal line of bit address decoder 7 is connected to the other input terminal of AND gate 24-0, and the mode signal line is connected to AND gate 24-0. One input terminal of 22-0 is connected to the other input terminal of AND/G 21-0 through an inverter 23-o. The output terminal of AND gate 24-0 is connected to the input terminal of OR gate 25.

The other input terminal of AND gate 22-0 is connected to the output terminal of OR gate 25. One input terminal of the OR gate 20-0 is connected to the output terminal of the AND gate 21-0, and the other input terminal is connected to the AND gate 21-0.
Connected to the output terminal of 22-0, or game) 20-0
The output of is sent to the data bus through bidirectional bus driver 3. With the above connection configuration, in the bit mode, the mode signal line is logic "1", so
When the select signal of bit address decoder 7 is logic "1", AND gate 24-0 . Or game) 25. AND GATE 22-0. Then, the read data of bit 0 in the memory 2 is sent to the data bus through the OR gate 20-0, and the select signal of the other bits of the bit address decoder 7 becomes logic "1".
When the read data of the relevant bit in the memory 2 is OR gate 25, AND gate 22-0. It is then sent to the data bus through OR gate 20-0.

Hereinafter, bit 1 to bittle are also the same as bit 0.

[Effects of the Invention] As is clear from the above description, according to the present invention, high-speed reading and writing of data in fixed length units and fine-grained reading and writing of data in bit units can be performed by switching the mode detection power. Therefore, detailed and high-speed data transfer can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a memory control circuit, FIG. 3 is a block diagram showing an overview of the configuration of a write control section, and FIG. FIG. 5 is a diagram showing an example of a specific configuration of a control section, FIG. 5 is a diagram showing an example of a specific configuration of a gate circuit used in a write control section, and FIG. 6 is an overview of the configuration of a read control section. The block diagram shown in FIG. 7 is a diagram showing one example of a specific configuration of the readout control section.

Claims (1)

[Claims] a first bidirectional bus driver, a second bidirectional bus driver, a read control, a write control, and a bit address decoder; The bidirectional bus driver outputs read data from the memory from the second bidirectional bus driver through the read control section to the data bus side of the first bidirectional bus driver in response to a read signal, and outputs read data from the memory to the data bus side of the first bidirectional bus driver in response to a write signal. The memory can be switched to output write data from the data bus from the first bidirectional bus driver to the memory side of the second bidirectional bus driver through the write control section. In the control circuit, the write control unit is supplied with a select signal of the bit address decoder, a mode signal whose bit mode is a fixed length mode, and data in the memory, and the write control unit: On the condition that the fixed length mode mode signal is given, all bit data input from the first bidirectional bus driver is output to the second bidirectional bus driver, and the bit mode signal is applied. On the condition that the mode signal is given, the bit selected by the select signal of the bit address decoder receives the data input from the first bidirectional bus driver, and the other bits are stored in the memory. The data of the corresponding bits given from
The read control unit is supplied with a select signal of the bit address decoder and a mode signal of either bit mode or fixed length mode; The read control unit outputs all bit data input from the second bidirectional bus driver to the first bidirectional bus driver on the condition that a mode signal of the fixed length mode is applied. , the bit data selected by the select signal of the bit address decoder out of the data input from the second bidirectional bus driver on the condition that the bit mode mode signal is applied. 1. A memory control circuit configured to output to one bidirectional bus driver.