JPS5936896A - Transmitter for accumulated data - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated data transmission device that is used as a remote measuring device, a remote monitoring control device, or the like.

FIG. 1 is a block diagram showing a conventional example of such a transmission device. In the figure, "U" and "S" indicate the main parts of the integration device, which consists of an integration counter 1 and an integration output register 2. "T" shows the main parts of the transmission device, and 3A to Nth word It consists of an input gate 3N and a transmitter register 4.

2 and 0 are timing charts of each line signal in FIG. 1.

The operation will be explained with reference to @1FXJ and FIG.

Pulse input that arrives as data at any time is handled by an integration counter l.
It is accumulated each time. Then, the integrated value is read into the integrated value output register 2 at an appropriate timing. Next, a control unit (not shown) controls the first
A word read pulse is input to the first word input gate 3A, opening it. As a result, the integration output register 2
The contents of a predetermined number of digits are transferred to the transmitter register 4-\.

The data transferred to the transmitter register 4 as one batch through the gate 3A is transmitted as a first word from the transmitter (not shown).

Next, the second word read pulse, the third word read pulse...
...The MA-c-reading pulse of the first word reading Hals is given from the control unit, and depending on the circumstances, the corresponding input game)
, 313.3C (not shown)...3N is opened, and the contents of a predetermined number of digits in the integration output register 2 are transferred to the transmitter register 4, and the second word, third word, etc.
. . . It is transmitted as the n-th word from a transmitter (not shown). That is, the contents read into the integration output register 2 are transmitted as 11 words in series.

Now, in the integrating device S shown in FIG.
Regarding the timing of reading into register 2, if this timing of reading occurs during the integration operation in counter l, a completely unrelated and meaningless value that occurs during the integration process will be read into register 2. ,
To prevent this, the integration counter 1 normally sends a READY signal synchronized with the input pulse to the register 2 to regulate the timing of reading by the register 2. This is clearly shown in Figure 2 (a).

In other words, as shown in Figure 2 (a), the counter l
The E and ADY signals supplied from the register 2 to the register 2 are synchronized with the input pulses to the counter 1, and remain at the L (low) level for a certain period of time t1 from the direct input pulse. 1,
0 to take H (high) level and this Jl, 13 A
)) In period 1 when the Y signal takes L level,
Reading by the register 2 is prohibited, and the counter 1 completes the integration operation of input pulses during this period. This solves the problem of register 2 reading completely meaningless contents from counter 1.

On the other hand, the timing for serially transmitting the contents read into register 2 as 11 words is determined by the product node fi? 8 is determined independently of the above-mentioned timing.

The transmission timing will be explained below with reference to FIG. 2 O).

The read passes A and S arriving from a control unit (not shown) arrive at regular intervals from the first word read pulse to the nth word read pulse, and correspondingly (IW, 2W, .
... n W ] is transmitted. Subsequently, a synchronization word for synchronization on the receiving side is inserted, and is further periodically transmitted as (IW, 2W, . . . n W ).

Now, in the conventional m* data transmission device as described above, the operation timing in the integration device MS and the operation timing in the transmission word [T are determined independently. It could happen that the integration output register 2 reads the next integration value from the counter 1 before the contents read from the counter 1 have been completely transmitted as n words.

In this case, a part of the n-sode sent from transmission 'A@1' is due to the content that the integration output register 2 first reads from the counter 1, and the other part is due to the content that the integration output register 2 reads from the counter 1. This is due to the contents that occurred during the process of reading from counter 1 for the second time, and as a set of data consisting of n words,
This results in meaningless data being transmitted, which is extremely inconvenient.

The present invention consists of 1. This invention was made to solve the above-mentioned inconveniences in the prior art, and therefore, an object of the present invention is to prevent meaningless data from being generated as a set of n words due to read timing, etc. An object of the present invention is to provide a transmission device for integrated data that is prevented from being transmitted.

The main point of the configuration of the present invention is that the integration output register uses the T'tEADY signal output from the integration counter as a timing signal to read the integration value in the integration counter, and synchronizes with the synchronization word added to the data consisting of n words. The point is that the AND output with the generated BNAB, T, and E signals is used.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. The circuit configuration shown in the figure is different from the conventional circuit configuration shown in FIG. R output from counter 1
Instead of using the EADY signal, the AND gate 5 creates an output of the READY signal and the ENABLE signal output from the transmission device T, and uses this AND output as the read timing signal. 0 There is nothing else that has changed 0 Figure 4 (a)
4 is a timing diagram of each line signal in FIG. 3. First, refer to FIG. 4 (5). RBADY is generated and outputted by the mW counter in synchronization with the input pulse.
It will be obvious that the AND output of signal 7 and J (NABLE signal) is used as the read pulse of the product output register 2. Also, at the rising edge of the read pulse of the product output register 2, the product output is It will be observed that the data in register 2 has changed (i.e. a read has taken place).
Regarding this point, what is the timing at which the L E signal is generated in the transmission device 1?
This will be explained with reference to FIG. 4(c).

In FIG. 40, the first word read pulse is generated at the end of the synchronization word in the serial transmission signal, so that the number of digits corresponding to the first word in the MW output register 2 is read through the first word input gate 3A. The data is then read into the transmitter register 4. Similarly, the m-th word read pulse is generated at the end of the fil(m-t) word, and the number of digits in the integration output register 2 corresponding to the @In word is read into the transmitter register 4.

The same applies below.

In this case, in the timing of the synchronization word in the serial transmission signal, E is applied during a period that does not overlap with the first word read pulse.
Generates a NABLE signal. Needless to say, no data is transmitted during this period.

Therefore, the AND output of the RE A DY signal and the ENABLF3 signal causes f1! of the integration output register 2! By using a read signal for the integrated value in the calculation counter 1, the inconveniences seen in the prior art can be solved.

According to the present invention, an integrated data transmission device has the advantage of being able to accurately read and transmit integrated data.

The present invention is particularly effective when the cumulative data has a large number of digits and one data spans a plurality of words forming a serial transmission signal.

This invention can be applied not only to the transmission apparatus described above, but also to reading integrated data with a large number of digits into a computer or the like.

[Brief explanation of the drawing]

FIG. 11 is a block diagram showing a conventional example of an integrated data transmission device, FIG. 2 and 0 are timing charts of each line signal in FIG. 4 (5) and 0 are timing charts of each line signal in FIG. 3. Description of symbols 1... Integration counter, 2... Integration output register, 3A... First word input gate, 3
N... Song N word input gate, 4... Song transmitter register, 5... Song & Gate agent, patent attorney Akio Namiki, patent attorney Kiyoshi Matsuzaki.

Claims (1)

[Claims] 1) An integration counter that counts and integrates pulses input as data, an integration output register that reads the integrated value from the counter in parallel, and the contents of the register are divided into a certain number of digits. a transmitter register that sequentially reads data in parallel in parallel and sequentially outputs the data of a certain number of digits read in - times as one word in series; and a series of words corresponding to the contents of the integration output register from the transmitter register. and a transmitting unit that adds a synchronization word to the data and transmits it in series, and a transmission unit for transmitting cumulative data consisting of C, wherein a pulse is sent to the cumulative counter as a timing signal for reading the cumulative value from the cumulative counter into the output jJ register. Every time ``is input'', the first
from the period of the synchronization word, the first signal takes a level of 1 and takes a second level in other periods, and is applied to the transmitter register in order to read the first word from the integration output register to the transmitter register. By using the AND output of Transmission of cumulative data, characterized in that the cumulative value is not read from the cumulative counter to the cumulative output register until after the contents once read into the cumulative output register have been transmitted from the transmitter. Device.