JPS5936287A - Character display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Misfire #! A relates to a character display device that can perform column-by-column window display and column scrolling (horizontal scrolling), and also has a display mode M in which the horizontal width of one character is expanded, although the total number of characters that can be displayed is reduced.

Figure 1 shows an example of a conventional character display device.
1 is a microprocessor (MpU).

2 is a cathode ray tube display controller (hereinafter abbreviated as CRTC), 5 is a multiplexer, and 4 is a display screen regeneration maintainer (refresher 3).
-) memory (hereinafter simply referred to as RAM), 5 is a character generator that inputs a character code and rask designation and outputs display dots on the designated rask for that character in parallel, 6 is a parallel input serial output CP-5) circuit.

7 is an AND gate, 8 is MpUt data bus to RAM
A bidirectional bus buffer coupled to a. C, RT C
2 is in addition to the horizontal synchronization signal (BSYNC) and the display timing signal (DISP/G).

Address of character to be reflexed kl Ao~MA,
.

to the RAM 4 via the multi-bleph generator 3, -f (actual division 2 dots to be displayed).
Send to. Multiplexer 5 CLM p 111 is commanded to input the address of the address bus /< A M
4, and transmits and receives data to and from the data bus via the memory top bus buffer 8 of this selected address.1. The dots in the specified row of the dot matrix display of the characters output in parallel from the character generator 5 are displayed from the p-8u path 6 to the 1st substitution column by the AND gate 7. From there, the video signal (VIDEO
) is sent as When performing a window display that displays only one or more vertical columns of the Zt/'1 or 1 displayable screen on such a conventional character display device, blank columns and display columns are stored in the refresher memory RAM 4. There are problems such as the need for operations, the need for a second memory to store the contents of blank columns, and the difficulty in column scrolling (horizontal scrolling) display.

The purpose of the present invention is to solve the above-mentioned problems of the conventional technology, and to display windows in individual units and horizontally scroll display layers.
To provide a character display device capable of displaying window display contents by enlarging the width of characters in the horizontal direction.

In order to achieve the above object, the present invention provides a display timing signal conversion circuit consisting of a '441 and a second counting circuit that count the character clock signal or dot clock signal, respectively, and receives the display timing signal as input. Then, the first counting circuit starts counting the clocks, and when it reaches the arbitrarily determined first predetermined number, the screen display starts, and from that point on, the second counting circuit starts counting. The display is ended when the second predetermined number is reached, and window display is performed in units of character columns or dot columns. In addition, a delay circuit is provided to delay the horizontal synchronization signal by an integral multiple of the character clock signal period or dot clock signal period, and the delay multiple is sequentially decreased or increased together with the first predetermined number at *appropriate intervals. Enabled horizontal scrolling display to the left. Generally, a character display device is used as an iF1' calculation terminal, and in such a case, a latch circuit that holds the first predetermined number, a latch circuit that holds the second predetermined number, and a horizontal synchronization signal: M extension amount. A latch circuit is provided to hold the character clock signal period or dot clock signal period as a multiple of the period.

If the number of these latch circuits held is arbitrarily controlled by the MPU built into the terminal (in some cases, the CPU of the entire system may also be used), it is possible to create vertical windows in character columns or dots. You can do things as you wish, such as display, horizontal scroll display, and even enlarge the character width of the window display contents.

The present invention will be explained in more detail below using the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention, where 9 is a display timing signal conversion circuit which forms the basis of the present invention, 10 is a horizontal synchronization signal delay circuit, and other symbols are the same as those in FIG. The same is true. The display timing signal conversion circuit 9 converts the original display timing signal DI SpTMG, which attempts to display as much content as possible over the entire display screen, starting from the left side of one screen as much as possible and extending to the right side, to the width of the display screen. is converted into a display timing signal DISPTMG' used for actual display including (vertical) window display that occupies only a portion of the display surface of the cathode ray tube. Horizontal synchronization signal delay time (K) period or dot clock signal (DOTC)
The original horizontal synchronization signal (H5YN
C) is delayed and converted into a horizontal synchronization signal (BSYNC') used for actual display including window display and scroll display.

FIG. 6 is a block diagram showing the display timing signal conversion circuit 9 and horizontal synchronization signal delay circuit 10 shown in FIG. 2, and their vicinity in some detail.

11 is a delay circuit that delays the horizontal synchronizing signal H5YNC by an arbitrary integer multiple of the character clock signal CIIACLK cycle to produce the horizontal synchronizing signal α1lsYNcα; 12 is a delay circuit that starts counting the character clock signal CHACLX in accordance with the input of the display timing signal DISPTMG; When counting until the number is reached, the display timing signal aDIS
The first counting circuit outputting PTM GcL determines the display start column.

13 (DISPTMC; a second counting circuit that starts counting the character clock signal CHACLK in response to the α input and counts until it reaches a second predetermined number, outputs the display timing signal 1) DISpTMGb during the counting period, and Determine the number of columns to display. 14 and 15 are the horizontal synchronization signal ESYNC and the timing signal DI in Table 7, respectively.
SPTMG.

Use for actual display HSY #C', DISP
1 display mode switching with selector α and selector b to convert to T Mσ.
1sYNc as is or horizontal synchronization signal α11SYNC
a as the horizontal synchronizing signal 11sYNC' for actual display.
Display timing signal 1) ISPTMG is output as the display timing signal DI Sp T M G' for actual display.

Figure 4 shows the delay circuit 11 and the first counter (%) shown in Figure 3.
(b) A specific example circuit of path 12 is shown. count (9) road 1
6 uses the horizontal synchronizing signal H5YNC inverted by the inverter 17 as the LOAD signal.

When the character clock signal CHACLK is counted up to a predetermined number, a carried signal (COH) is output. This carrier signal COH and the horizontal synchronization signal M5
YNC is selected by the selector 18 and output as a horizontal synchronizing signal αH5YNCα. That is, if there is no need to delay, H5YNC is output as is, and if it is necessary to delay, a set value is set in the count circuit 16, and it is output after counting the character clock signal CII A CL K. Carried signal C
Use OB as If S YNCα. Inverter 19. Nantes Gate 20. The self-stop counter consisting of the count circuit 21 receives the display timing signal DISPTM.
Character clock @No. C11ACLK from the time of G input
After counting with a predetermined number of 1, carry out 1 Hgc.
Outputs on.

This con and the display timing signal DISPTMG are selected by the selector 18 and the display timing signal a l)
It is output as I S p T M G α. In other words, when displaying from the left end of the display screen (the display start column is column 0), the 1 display timing signal DISPTMG is output as is, and when the display start column is changed, the 1 display timing signal DISPTMG is output as is.
Set the setting value to .

A carried signal COD output when a predetermined number of character clock signals CHACLK is counted is used as a display tie 6fufu 13 txDIsPTMGa. The latch circuit 22 is a latch circuit that holds the count setting values of the count circuits 16 and 21 and the selection conditions of the selector 18.

Here, the same set values are set in the count circuits 16 and 21, and the scroll display is performed by row 7.

FIG. 5 shows a specific example circuit of the second counting 11 path 16 shown in FIG. Inverter 25. Nando game) 24
, a self-stopping counter consisting of a counting circuit 25, displays a display evening/f timing signal 6. It starts counting the character clock signal CHACLX from the time of inputting the D I Sp TMGα, and outputs the number COD' to the carrier signal 1 when it reaches a second predetermined number. The inverted signal of this C01J)' is the display timing signal b D I S P T
It is output as ld Gb. The latch circuit 26 holds the set value set in the count circuit 25, that is, the number of columns displayed to the power of 1 in the window.

Figure m6 is a timing chart showing the signals described above and their generation order, and the signal names are the same as those in Figure 5. The maximum screen that can be displayed is the display timing signal DISP.
This is the section in which TMG (d) is output, and the display timing signal α, which determines the display start column by counting the character clock signal citiCLK (a), ie DIS
pTMGa(f) and a display timing signal that counts CIfACLK (t) to determine the number of display columns in the window, that is, DISPTMGb(!1) *1
The display screen of M is displayed using the display timing signal nlspTMG (
Generally, the output section of DIsprmGbcy> is narrower than that of DIsprmGbcy>.cl). In other words, it becomes as shown in East Map 7. 7th
In the figure, a window B is shown within the maximum displayable screen A. The first predetermined number is arbitrarily preset in the count circuit 21 shown in FIG. 4, and the second predetermined number is preset in the count circuit 25 shown in FIG. Only the window part is displayed. Further, the horizontal synchronization signal H5YNC(α) (Fig. 6) is passed through the delay circuit 11 (Fig. 3) to the character clock signal CHACLK (,
6) (Figure 6) It is converted into a character clock signal αH5YNCα(c) delayed by an arbitrary integer multiple of the period,
This H5YNCcL determines the left and right ends of the actual screen.

In other words, if the amount of delay in the delay circuit 11, that is, the delay multiple, is increased or decreased one by one at appropriate intervals in synchronization with the first predetermined number set in the count circuit 21, horizontal scrolling display to the left or right can be achieved. can.

FIG. 8 shows the refresh memory addresses (for example, MAo~"Alg to RAM4 in the first and second rows) for the display screen when the number of horizontally displayed characters is 120. The part surrounded by the 2l frame is the actual Memory address (abbreviated as MA) on the display screen; other parts correspond to the blanking interval M
It is A. In order to realize this screen display, the cathode ray tube display controller CRTC has a total horizontal character count of 180 characters,
The number of horizontally displayed characters is set to 120 characters. FIG. 9 shows the memory address HA of the display screen in which 121 characters are set as the total number of horizontal characters and 120 characters are set as the number of horizontally displayed characters in the CRTC. In Fig. 9, only 80 characters out of 120 characters are displayed by expanding the character width horizontally, so the period for sending the 1 display timing signal DISPTMG (the period in which this 4W signal is "high") extends to 120 characters. However, the input/output interval of DISPTMG', which determines the actual number of display columns, is 80 characters. If the period of the character clock signal CHACLL or dot clock signal DOTCLK is the same as that in FIG. 8, then in the case of FIG.
0 characters are displayed, and a blank space of 40 characters is created on the right side. However, by extending the cycle of C11AcLK or 1) OTCLK, the character width could be expanded horizontally so that 80 characters would be equivalent to 120 characters in the case of Figure 8 (almost the entire display screen width of the cathode tube screen). It can be displayed and is easy to see. Since the horizontal synchronization frequency, and hence the period of the serrated horizontal deflection curve that swings the electron beam, is almost constant, as described above, if the period of the character clock signal CE A CLX or don't clock signal 0TCLKI/) is 1ψ, This means that it will be displayed in 80 characters.
)"i, horizontal control voltage blC rises and approaches the upper limit, 81
From the 81st character to the 120th character, the V display timing signal l) IS P TM G is about to be sent. During this period and the period after that, the return erasure assumption has the same length as 1h as before, and regardless of the number of addresses on the refresh memory in the corresponding part of this period, the return erasure assumption "1" is the frog. If so, the horizontal deflection current will start to rise and the display will start at the same time as fΦ. The character clock 4@-q
CHA CL fmata t edot clock 1g DOT
In order to extend the period of CLf, the phase of the output pulse is continuous when the period changes, so it is necessary to use a device according to Publication No. 8A (% Yan Show No. 56-178580) of the same applicant by the Ministry of the Invention. The problem with Taisaku Shunsai is 71. Even in the case of this strain's enlarged display, in the case of the previous ml window 9 display, it is the same, Shinsuku A -
It goes without saying that you can't do it at any rate.

In the above embodiment, the character clock < g ciii (N
No. 1) It is natural to use OTCLK as a standard for counting, and it is effective when displaying graphics. In addition, in the embodiment, the horizontal synchronization signal HSYNC is delayed by hardware, but the first page set in the horizontal period register of the CRT C is changed as appropriate. By doing so, it is also possible to delay the horizontal synchronization signal H5YIVC using software.

The present invention can be applied to conventional graph ink display gray systems without causing any nuisance, and is particularly effective for display screens in which graph ink and characters are mixed. In the upper layout example (Eng. 1, we have set up a nitpick section on the left and right sides of the screen that can be displayed, but
Display timing inertia for center division display DI S P l'
, if you invert and use yl G', you will get hFSI for one display.
! Display columns on the left and right of the i11 box.

A blank area may also be provided in the middle. -il According to the present invention, it is possible to display a screen with a large number of horizontal display characters and a display screen with a small number of horizontal display text, which is a partially enlarged horizontal display. can be displayed.

As explained above, according to the present invention, window display and horizontal scrolling display can be easily performed in units of character rows or display dot rows by providing only one set of refresh memory, and the character width can be increased more than ever before. It is also possible to display the image enlarged horizontally.

Note that the present invention is applicable not only to ink-sprayed tubes but also to similar type display devices, such as liquid crystal display devices using a dot matrix (IJ) display type.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional character table 7rX device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a display timing signal conversion circuit and a horizontal synchronization No. 4g delay circuit according to the present invention. Figure 4 shows the horizontal synchronization key signal delay l! 21 is a circuit diagram showing a specific example of the first counting circuit, FIG. 5 is a circuit diagram showing a specific example of the second counting circuit, wc6 is a timing chart showing each signal and the order in which they are generated, The figure is an explanatory diagram of window display. FIG. 8.9 is an explanatory diagram showing the relationship between the display screen and the flexible memory address arrangement. 1...MpU 2...CRTC (Dyodo tube display city 1) 4...
Screen playback maintenance memory (refresh memory) 5...Character generator 9...Display timing signal conversion circuit 10, 11...Delay circuit 12...First counting circuit 16...Second counting circuit 16 , 21, 25... Count 1g circuit 22,
26...Latch circuit 4th port data bus S diagram D-91\S1 white] Figure 7 [)IsPTMAJ (9,1

Claims (1)

[Scope of Claims] (11) A display memory capable of storing characters to be displayed in their arrangement at the time of display, a character generator that outputs a dot matrix display of the character code when inputted, and a fresh memory address ( In a character display device equipped with a cathode ray tube display controller that outputs a raster address signal to a character generator, a horizontal synchronization signal, and a display timing signal, a first clock signal or a dot clock signal is counted. A display timing signal conversion circuit including a second counting circuit is provided, and the display timing signal conversion circuit converts the display timing signal into an arbitrary first signal immediately or by the first counting circuit based on the display timing signal input time point. After counting a predetermined number, the second counting circuit converts the period until it counts an arbitrary second predetermined number into a display timing signal and outputs the display timing signal as the actual display period. (2) A patent claim in which a delay circuit for delaying the horizontal synchronizing signal by an arbitrary integer multiple of the dot clock signal period or the character clock signal period is added to the circuit that sends the horizontal synchronizing signal from the cathode ray tube display controller. The character display device according to item 1. (3) A latch circuit that holds the first predetermined number. A latch circuit that holds the second predetermined number, and a delay component of the horizontal synchronization signal delay circuit. A latch circuit is provided to hold the
2. A character display device according to claim 1, wherein the number of latches held by each of these latch circuits is controlled arbitrarily. (4) The character display device according to claim 1, wherein the dot clock signal period or the character clock signal period is switched according to one display mode while making the phase of the output pulse of each issue continuous. (5) Display content in fewer columns than the maximum number of columns that can be displayed,
dot clock every issue cycle or character clock
An 8G character display device with a display mode that extends the cycle and enlarges the horizontal length of one character by 10 inches.