JPS5935048B2 - Timing information transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing information transmission method in a digital complex system.

Conventionally, various digital complex systems have been used that consist of a main circuit block that generates timing information and one or more subordinate circuit blocks that operate according to the timing information. ,
Timing information sent from the main circuit block to each subordinate circuit block is configured to be transmitted through dedicated lines provided individually.

Therefore, the number of wiring between the main circuit block and the slave circuit blocks increases in proportion to the number of slave circuits, and in a system with a large number of slave circuit blocks, the wiring becomes complicated and reliability decreases. have. An object of the present invention is to transmit timing information between a main circuit block and each subordinate circuit block with high reliability without having to install multiple wires between the main circuit block and each subordinate circuit block. The purpose of the present invention is to provide a timing information transmission method that enables the transmission of timing information.

In the present invention, in a timing information transmission method in which a clock signal and timing information are sent from a main circuit block to a plurality of dependent circuit blocks via a common bus line to selectively operate the dependent circuit blocks, the timing information is This is an address signal in which a flag bit and a plurality of address bits unique to each of the dependent circuit blocks are serially multiplexed and sent out in synchronization with a clock signal, and each of the dependent circuits has a flag bit that detects the input of the flag bit. A detection circuit, a counting circuit that counts clock signals from the time of detecting the flag bit and outputs a count signal corresponding to the count value, and a count circuit that presets the address bits that are sequentially input from the flag bit onwards according to the count signal. a comparator circuit for comparing an address specific to the dependent circuit block, a set-reset type flip-flop that is set by the detection of the flag bit and reset by a mismatch in the comparison, and a predetermined first counting signal of the counting circuit. a delay type flip-flop for latching the output of said set-reset type flip-flop circuit by a predetermined second count signal of said counting circuit; a first gate for inhibiting a clock signal to said counting circuit by said second counting signal; and a second gate for inhibiting the output of the delayed flip-flop, and an accessed circuit in the dependent circuit is operated by the output of the second gate. be done.

The system of the present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows an embodiment of a digital complex system using the timing information transmission method of the present invention.

This digital complex system 1 consists of a main circuit block 3 including an address signal generation circuit 2, and complex subordinate circuit blocks 4a, 4b, . . . ( (Only two are shown in FIG. 1). The address signal generation circuit 2 sends out a clock signal S1 of a predetermined period and an address signal S2 synchronized with this clock signal S to bus lines 5 and 6, respectively. 5, 6 to each dependent circuit block 4a, 4.
b, . . . decoder circuits 7a, 7b, .
...is input. In Fig. 2A and b, the clock signal S1
An example of the address signal S2 is shown.

The address signal S2 is composed of 6 bits per word, and the first bit is specified as a flag bit to always be "1", and the remaining 5 bits (a to e) are used as address bits. , a unique address code given to each required dependent circuit block is inserted. Each word constituting the address signal S2 is serially multiplexed at a predetermined time interval T, and sent to the bus line 6. This serially multiplexed address signal S2 is transmitted to each decoder circuit 7a, 7b...
When each decoder circuit determines that the address code of the address signal S2 specifies the dependent circuit block to which it belongs, the decoder circuit decodes the code 8a.
, 8b . . . to the corresponding accessed circuits indicated by
, ...... is output.

This access signal, for example, S3a shown in FIG. make the action take place. Although the case where the dependent circuit block 4a is addressed has been described above, the same applies even if other dependent circuit blocks are designated. FIG. 3 shows the decoder circuit shown in FIG. 1 in detail. Although the decoder circuit 7a is shown in FIG. 3, the other decoder circuits have similar configurations. In FIG. 3, 10 is a shift register, 1
1 is a 4-bit binary counter, 12 is a 4-bit binary counter 11. It decodes the contents of the 4-bit output from the 4-bit binary counter 11 and sends ``1'' as a count signal to the terminal corresponding to the contents among the terminals of outputs 1 to 16. Decoder for output, 13 is R-S
Flip-flop, 14 is a D-type flip-flop,
15 to 19 are and gates, 20 is or gates,
21 is an exclusive OR gate, and 22 to 24 are gates. In the decoder circuit 7a, an address signal S2 from the bus line 6 is input to a terminal 25, a clock signal S from the bus line 5 is input to a terminal 26, and this clock signal S1 is applied to the shift register 10 as a shift pulse. has been done. Therefore, the address signal S2 input from the terminal 25 is sequentially written into the shift register 10 at each rising edge of the clock signal S1. On the other hand, terminals 27 to 31 are each applied with a signal of a logic level corresponding to a 5-bit address code attached in advance to the dependent circuit block 4a to which this decoder circuit 7a belongs. Therefore, for convenience of explanation, it is assumed that the address code pre-assigned to this block 4a is (00101), and the contents of a to e shown in FIG. 2b designate the block 4a.
That is, it is assumed that it is (00101). Now, assuming that the period t1 is longer than the time length T4 of the word, when the flag bit F in the word is input to bit position 10a of the shift register 10, the contents of the shift register 10 will be at bit position 1.
Since only 0a is "1" and the contents of the other bit positions are "O", the output of the gate 22 changes from "0" to "1", and therefore the output of the binary counter 11 is set at terminals R and R. -S
The set terminal S of the flip-flop 13 becomes "1", the binary counter 11 is reset, and at the same time the R-S flip-flop 13 is set and its Q output becomes "1".
become. That is, a predetermined set or reset operation is performed by inputting "0" to the shift register 10 for a predetermined period and then inputting a flag bit "1". At this time, the output of the 4-bit binary counter 11 is (00
00), and only one terminal of the decoder 12 becomes "1". Therefore, in this case, terminals 27 to 31 have (00101
) is applied, the outputs of the AND gates 15 to 19 all become "old", and the output of the OR gate 20 also becomes "0". At this time, since the signal "0" corresponding to address bit a is applied to the terminal 25, the output of the gate 21 also becomes "0", and therefore the RS flip-flop is not reset. Next, when the next clock signal is input, since terminal 16 of the decoder 12 is "O", the gate 23 is in the open state, so this clock signal is
It is input to clock terminal c of bit binary counter 11, only two terminals of decoder 12 become "1", and terminal 28
A signal of the same logic state as that of the signal applied to the OR gate 20, i.e., "0" in this example, is applied to the OR gate 20.
appears in the output of At this time, address bit b (="O") is applied to the terminal 25, so the R-S flip-flop 13 is not reset in this case as well. As can be seen from the above explanation, each time the clock signal S1 is input, the signals applied to the terminals 27 to 31 are taken out from the OR gate 20 and sequentially compared with the address bits a to e, so that each bit is compared with the other. When they are equal, the R-S flip-flop 13 is not reset. The address bits specified in this way (
00101) and the unique address bits (00101) applied to terminals 27 to 31 are detected, and when the clock signal S1 is further input and the 9th terminal of the decoder 12 becomes "1". , the state "1" of the Q output of the R-S flip-flop 13 is a D-type flip-flop.
is latched to the flop 14 and therefore its Q output value ``1''.
" is outputted to the output terminal 32 via the gate 24 which is kept open by the signal from the terminal 16, and is applied to the accessed circuit 8a in FIG. 1 as the access signal S, a. When the clock signal S1 continues to be input, the 16 terminal of the decoder 12 becomes "1", the gate 24 is closed and the sending of the access signal S3a is stopped, the gate 23 is also closed, and the clock signal S1 is output to the binary counter. 1
It is prohibited to supply it to the clock terminal c of 1. In the above, we have explained the case where the contents of the address bits are the same as the codes given to the terminals 27 to 31. However, if they are not the same, the output of the gate 21 will be "month" and R- Since the S flip-flop 13 is reset, the access signal S3a is not output from the terminal 32.

Further, as can be seen from the above explanation, the time point at which the access signal S3a is generated and the length of the period are different from each other in the D-type flip.
The signals to be supplied to the clock terminal c of the flop 14 and the inhibit terminals of the gates 23 and 24 can be arbitrarily selected depending on which terminal of the decoder 12 they are supplied from.

According to the present invention, since the address signal is serially multiplexed and supplied to each slave circuit block, the number of connection lines between the main circuit block and the slave circuit block can be significantly reduced, resulting in a more compact system. , high reliability can be achieved.

In addition, when adding a slave circuit block, it is extremely easy to do so as all you have to do is extend the bus line.Furthermore, by changing the order in which the address signals are generated in the main circuit block, the slave circuit block can be expanded very easily. Since the access order of the blocks can be changed, programmability can be easily added to the main circuit blocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an actual example of the present invention, FIGS. 2a to 2c are waveform diagrams of various parts in FIG. 1, and FIG. 3 is a circuit diagram of the decoder circuit shown in FIG. 1. 1...Digital complex system, 2...
・Address signal generation circuit, 3...Main circuit block, 4a, 4b...Subordinate circuit block, 5, 6
... Bus line, 7a, 7b ... Decoder circuit, 8a, 8b ... Accessed circuit.

Claims (1)

[Claims] 1 In a timing information transmission method in which a main circuit block sends a clock signal and timing information to a plurality of dependent circuit blocks via a common bus line to selectively operate the dependent circuit blocks, the timing information is divided into flag bits and The address signal is serially multiplexed with a plurality of address bits specific to each dependent circuit block and sent out in synchronization with a clock signal, and each of the dependent circuits has a flag bit detection function that detects the input of the flag bit. a counting circuit that counts clock signals from the time when the flag bit is detected and outputs a counting signal corresponding to the counted value;
A comparison circuit that compares the address bits sequentially input after the flag bit with an address specific to the dependent circuit block set in advance according to the count signal, and a comparison circuit that is set by the detection of the flag bit and compares the address bits that are input sequentially after the flag bit. a set-reset type flip-flop reset by;
a delay type flip-flop that latches the output of the set/reset type flip-flop circuit in response to a predetermined first counting signal of the counting circuit, and a clock signal to the counting circuit in accordance with a predetermined second counting signal of the counting circuit; a first gate that inhibits the output of the delayed flip-flop according to the second counting signal, and a second gate that inhibits the output of the delayed flip-flop according to the second count signal, and the output of the second gate inhibits the accessed circuit in the dependent circuit. A timing information transmission method characterized by operating.