JPS5935031B2 - EL display device drive device - Google Patents

Description

Detailed Description of the Invention (Summary) In a thin film EL having a hysteresis memory, writing or erasing is performed by instantaneously applying a voltage equal to or less than the maintenance AC amplitude under maintenance AC drive, and subsequent The present applicant has already filed an application as a prior invention for a technique for maintaining the light-emitting state or light-off state using a maintenance AC voltage.

The present invention relates to a writing circuit for a thin film EL matrix panel having an AC hysteresis phenomenon, that is, a memory function.

□EL Display Device) First, the EL display device used in the present invention will be briefly explained.

First, the configuration of the EL display device will be explained.

As shown in FIG. 1, transparent electrodes 2 are arranged in stripes on a glass substrate 1. On top of this is a dielectric material 3 such as Y2O3, further on this is a fluorescent layer 4 such as ZnS doped with Mn, and further on top of this is a dielectric material 3 such as Y203.
500 to 1000 layers each by vapor deposition, sputtering, etc.
0λ is deposited to form a double-insulated three-layer structure, and electrodes 5 perpendicular to the transparent electrodes 2 are arranged in stripes on top of the three-layer structure. With such a structure, one of the first electrode group 2 and the second
When a suitable alternating current voltage is applied to one of the electrode groups 5, only a small area sandwiched between the two electrodes will emit light, and this corresponds to one pixel on the screen. JEL
An EL display device can be constructed by sandwiching the emitting phosphor layer 4 between dielectrics 3 and 3 and further forming electrodes 2 and 5 thereon. By making it into a shape, a matrix display panel can be formed.

EL with this structure has superior characteristics in terms of brightness, lifespan, and stability compared to conventional distributed EL elements, but each pixel has a new characteristic between brightness and applied voltage. second to
A historical phenomenon as shown in Figure b is shown.

To explain this special music according to Fig. 2, when a pulse of voltage amplitude V1 is first applied as shown in Fig. 2 a, the brightness will change to B and c in the same figure.
As shown in , it is at level B. Here, the maintenance voltage V1
When the light emission threshold voltage is Vth, V1≧Vth.
When a write voltage V2 is applied to this, the brightness changes to B3 at once.
Even if the voltage value is returned to the maintenance voltage V1 again, the brightness settles to B2, which is higher than B1.
When V3 is applied, the brightness level decreases rapidly, and when it is returned to the sustaining voltage V1 again, the brightness settles to B1. These temporal relationships are indicated by the symbols Tl, t3, etc. attached to Figure 2 a.
I2, are shown by corresponding to the positions of the same symbols in FIG. This hysteresis phenomenon is caused by the amplitude and pulse width of the write voltage (not shown), as shown by the thin line in Figure 2b.
Any small loop can be taken depending on. That is, it is also possible to display halftones. A major feature of the ELP, which is not found in other display elements, is that once a write voltage is applied, each picture element continues to emit light without losing the gradation given to it by the sustain pulse. The above voltages vary greatly depending on the composition, film thickness, and applied waveform, but in a prototype example, Vth = 200V.
, V1=210V, V2=210~280V, V3=1
It is 90V. The present invention is based on the "EL" which was previously invented by the inventors.
This invention relates to an improvement in a display device drive device (filed on August 8, 1975, see Japanese Patent Laid-Open No. 52-20786), and its purpose is to simplify the write circuit.

The prior art will be described below, and then the structure of the present invention will be explained using preferred embodiments. <Prior Art> Figure 3 shows a drive circuit according to the prior art.

This diagram consists of five major blocks. The first block is a sustain drive circuit 10.

Although FIG. 3 shows a three-phase resonance maintenance drive circuit, a four-phase or more multi-phase circuit may also be used. The second block is a write switch circuit 20, which is a switch circuit for applying a write voltage Vw to the X line to be written in the write phase. In the circuit description to be described later, the X line will be treated as a scanning line. The third block is a data switch circuit 30.

All switches are shorted (grounded) during maintenance operation. In the write phase, only the Y line to be written is kept short-circuited, and the non-write Y line is opened. The fourth block is a write line isolation and sustain amplitude hold circuit 40. This is a diode circuit for separating the scanning write preparation lines in the X direction. The fifth block is a matrix panel 50 as shown in FIG. Further, FIG. 4 shows the on/off timing of each switch and the driving voltage waveforms E and f applied to the X and Y lines.

The specifications of the 8-inch EL panel prototyped by the inventors are as follows:
2/M7IL. 320 X lines (transparent electrode side), Y
240 lines (back aluminum electrode side) Display characters: 64 types of Roman letters with 5 x 7 dots, γ
Rabbit gamma Number of numbers and symbols displayed: 52 characters in the X direction (scanning side) 24 lines in the Y direction (data side) Maximum number of displayed characters: 1248 characters Number of effective display lines: 260 lines in the X direction (character spacing of 1 line) in the Y direction
There were 168 lines (line spacing of 2 lines).

In order to maintain and drive the above EL panel, the circuit shown in FIG. 5 was prototyped. In this figure, U: Open collector TTL Tr: Switching transistor T1: Inter-stage coupling transformer D1: Protection diode D: Holding diode Other symbols are used with the same meaning as in the previously explained drawings. There is.

In this circuit, circuit constants, inductance of resonant transformer: L = 29mH Panel capacitance when connecting effective display line number: CT = 0.377μFφ, φ2, φ3, pulse width: 200Itsec Repetition of each pulse: 330Hz As a result of resonant driving, the natural frequency was 4 to 5 KHz.

Based on the above circuit constants and driving results, the transparent electrode resistance RTl switching transistor -T of the thin film EL panel
The on-resistance of r, non-linear loss in large amplitude drive of thin film EL, forward resistance of diode, loss of coil, etc. are all calculated as constant resistance Rp loss, Rp = 115Ω ~ 1
It was about 25Ω.

From this, the damping constant: 1RZ Vibration condition 1〉- RAT2 Decay condition However, C is the capacitance value of capacitance component C. L is the inductance of coil L R is the total resistance value of the electrodes and each part of the circuit 1R2 Vibration condition 1 〉 - NAT2 natural frequency of It is calculated as follows.

Returning to FIG. 4, three-phase resonance maintaining drive will be explained. In this figure,

To simplify the explanation, let us consider the coefficient η as a coefficient that indicates the ``extra'' increment of the potential applied to the capacitive element C after a half cycle of LC resonance with respect to the potential difference applied to the LC circuit. good. The exact formulation of the coefficient η was given in the explanation of the invention of the prior application. Now, in FIGS. 4 and 5, when the first maintenance switch SWl is closed at the first timing φ1,
The difference between the third holding potential VH and the first power supply potential E1 is applied to the capacitive element CT (in this figure, the entire EL display panel is considered to be a capacitive element CT with approximately constant capacitance), and this potential difference is multiplied by η. Then, run the first holding potential V1-E1.
+η(B1-VH) ・・・・・・・・・・・・・・・
- Retained in (7).

Similarly, when the second holding switch SW2 is closed at the second timing φ2, the second holding potential -V2=-E2-η(V1
+E2) (8), and then, when the third holding switch SW is closed at the third timing φ, the third holding potential VH=ηV2...・・・・・・
・・・・・・・・・・・・・・・・・・・・・(9)

In this way, three-phase drive was realized. In this way, multi-phase sustaining drive with three or more phases is performed at an intermediate holding potential (
In this embodiment, data switch elements DSl, DS2, . . .
This is to reduce the pressure resistance requirements of... As shown in FIG. 4, writing is performed by selecting the X and Y sides of the write picture element M (J, i) by the write switch circuit 20 and data switch circuit 30, respectively, during the intermediate holding period (VH period). Let's do it.

FIG. 6 shows the write switch circuit 20.

In this figure, D1 is a protection diode. In this diagram,
To select 260 output lines, 10 lines are needed on the a side and 26 lines on the β side.
This is done using the 36 input lines of the book. In the circuit shown in FIG. 6, transistors WSAl, WSA2, . . . are attached to the switches WS1, WS2, . . . , respectively. This is because the switches WS1 and WS2 have a high write voltage Vw (according to the inventors' prototype, 270 to 2
80 volts), and the total number of transistors is reduced. On the other hand, the data switch circuit 30
As shown in FIG. 7, it is constituted by a transistor switch, and a data signal is applied to the base of the transistor in accordance with the displayed character, symbol or pattern to control the on/off of this transistor.

As shown in Figures 5 to 7 above, when writing
The transistors that make up the switch circuit on the line side are PN.
The transistors are P-type transistors, and the transistors forming the switch circuit on the Y-line side are NPN-type.

In this way, P-type and N-type switching elements are required,
In particular, since thin-film EL devices are high-voltage driven devices, high-voltage switching devices are required. However, when considering the integration of the drive circuits mentioned above, it is possible to integrate P-type and N-type high-voltage switching devices into monolithic ICs. This is extremely difficult with the current level of technology.

In view of the above points, the present invention improves the circuit configuration and
This realizes a circuit that can be driven only by channel switching elements, and is composed of a MOST with a common source or emitter and a bipolar NPN transistor.

<<Preferred Embodiment>> FIG. 8 shows a circuit diagram of an embodiment of a driving device for an EL display device of the present invention.

In this circuit, the same parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted. However, the write switch circuit 20' is a circuit for charging the external series capacitor of the X line to which writing is not desired during the write preparation phase. Further, the data switch circuit 30 continues to short-circuit only the Y line to be written during the write preparation phase and the write phase, and opens the non-write Y line. Since the first block 1' supplies not only the sustain voltage but also the write preparation voltage E6 and the write voltage E4, this block is called a sustain and write drive circuit. The sixth block 60 is a write preparation circuit consisting of external capacitors connected in series to each of the X lines.

During the write preparation phase, capacitor C of the line to be written
The charging voltage of i is lowered, and the capacitor Ck of the non-write line is
Charge \i with a high charging voltage. Next, the operation of the apparatus of the present invention will be explained with reference to the time chart shown in FIG. In FIG. 9, a indicates the sustain pulse, b the write pulse, c the drive pulse for the data switch circuit, d the drive pulse for the write switch circuit, e the waveform applied to the X electrode, and f the waveform applied to the Y electrode. show.

Since the sustain drive is the same as described above, the explanation will be omitted. However, when the third holding switch SW3 is closed at the third timing φ3, the power source -E3 (70 volts) is connected, so the third holding potential is VH=-E3-η(Vs-E3)=0. become.

Next, the write operation will be explained.

As shown in FIG. 9, the X and Y lines of the picture element M(1,j) to be written are selected by the write switch circuit 2' and the data switch circuit 30 during the O potential holding period of the sustain drive.
First, at write preparation timing φ6, turn on the write preparation switch SW.
6 is closed, and the charging power source E6 is connected to the X line side. At the same time in this phase, in the write switch circuit 20', only the switch Si for the X line Xi to be written is turned off, and the switches SkSi for the other non-write lines are turned on.
Also, in the data switch circuit 30, the Y line Y to be written is
Turn on the switch SDj of j, and turn off the switch of the non-write line. Therefore, the capacitor Ci on the write line has a capacitance (Ct is the equivalent capacitance of the light-emitting pixel M on the write line, C is the external capacitor C, = C2 =...
... = capacitance of Cm) is charged, and the capacitor Ck\i of the non-write line is charged with 0PH.

The potential of the X line Xi of the write picture element M is 0H, and the non-write line XkSi is O potential. Write timing φ
4, the write switch SW4 is closed and the write power source E4 is connected to the X line.

At write timing φ4, write switch circuit 2'
Then, all the switches s1 to Sm are turned off, and in the data switch circuit 30, only the switch SDj of the Y line Yj to be written is turned on, and the others are turned off. In this way, when the write preparation timing φ6 changes to the write timing φ4, the non-write line switch SkX of the write switch circuit 20' changes from on to off. Therefore, the potential of the write line Xi further continues charging at the previous write preparation timing to reach the write potential (0m>0s).
At this time, the potential of the write line Yj on the Y side is set by the switch S.
Since Dj is on, it is at O potential, and the writing picture element M(1,
A write voltage is applied to J), and it emits light. On the other hand, on the non-write line XkXi, this potential is 0PW-0PH<0s because of the charging voltage of the external capacitor Ck\i. At this time, the non-write line Yt\j on the Y side is switched to the switch SDkSj.
is off, the non-write line XL'S. on the X side is off. It changes according to the change in the potential of i. In other words, write voltage 'C)
From the 77-width mark W, the capacitor Ci of the writing line Xi has the same voltage as above, where Vt is the voltage across the light-emitting picture element M (capacitance Ct), and therefore Vt is expressed by the following formula. It is expressed as

C vt=? 0w ct+c Now, if C>>Ct, then Vt is 0w, and almost the entire write voltage 'C5w is applied to the light emitting picture element M.

On the other hand, in the non-write line XkXi, the external capacitor C
If the voltage across the line k is Vk, and the voltage across the picture element (capacitance Ct) connected to the non-writing line XkXi is Vl, then Qk
=CkOpH+diIdt=CkVk・・・・・・・・・
(1) Qt'=B1di=CtVt'
(2) Vk+Vl=0w・・・・・・・・・・・・
......(3) Note that when 0w is applied, Ck
, Ct are different from each other, and even if they are connected in series, Qk=Qt' will not hold.

In this case, there is no change other than the current 1 flowing into both capacitors from the write power source E4 according to Urchoff's law.
By the way, in the write line Xi mentioned above, Qi-Q
Since t=0=CVi-CtVtl, that is, the initial state is the same, Qi=Qk also at the time of 0w.

Also, with this Cvi-Ctvt=0 Vi+Vt=0w death From the relationship, Vt=? 0w derives Ct+c It goes without saying that it will happen.

Non-write line Xk'S. For i, from equations (1) and (2), CkOPH = CkVk - CtVt' If Vk is deleted from equation (3), CkOPH = Ck (0w - Vt') - CtVt' Therefore, if Ck >> Ct, then Vt ' 0W-0PH,
Substantially, the amount charged in the preliminary charge is subtracted, and the light emission threshold voltage is not reached.

Writing is performed in this manner.

After writing is completed, switch S is turned on at return timing φ5.
W5 closes, bringing the X line to ground potential.

At this return timing φ5, the write switch s1~
Sm is off, and data switches SDl-SDn are on. Therefore, both the X line and the Y line are at O potential, and all external capacitors C1 to Cm, . The EL panel is in the same state as before the write preparation timing. Then, maintenance drive is performed next.

During sustain driving, the writing picture element emits light due to the memory function of the EL display device, and the other points do not emit light. Figure 10 shows a writing picture element M(1,j) and a half-selected non-writing picture element N(
1, t), 0(K, j), and the unselected picture element p(K, t)
The applied waveform of is shown.

Since the driving device of the present invention is configured and operates as described above, the specific circuit of the driving device of the switching element connected to the matrix electrode according to the present invention is a write switch circuit as shown in FIG. Since all the MOSTrs constituting the data switch circuit 20' and the data switch circuit 30 are used with their sources connected to ground, they can be constructed using N-channel type MOSTrs with a common source. In addition to the circuit shown in Figure 11, there is a common emitter '\ipolar NPNT.
It is also possible to configure it with r. In the circuit of FIG. 11, the withstand voltage required of the switching transistor of the write switch circuit 20' is a write voltage of 0 W or more,
The switching transistor of the data switch circuit 30 is required to have a breakdown voltage of (0 pw - 0 pH) or more.

[Brief explanation of drawings]

Figure 1 is a partially cutaway perspective view of a thin film EL display element;
The figure is a characteristic curve diagram of applied voltage and luminance to explain the operation of a thin film EL display element, Figure 3 is a block circuit diagram of the prior art, and Figure 4 is a time chart of the circuit of Figure 3. , FIG. 5 is a circuit diagram of the sustain drive block in the circuit of FIG. 3, FIG. 6 is a circuit diagram of the write switch circuit in the circuit of FIG. 3, and FIG. 7 is a circuit diagram of the data switch circuit in the circuit of FIG. 3. FIG. 8 is a block circuit diagram of an embodiment of the driving device of the present invention, FIG. 9 is a time chart of the circuit of the present invention, and FIG. 10 is a block diagram of each picture element of a thin film EL display device. A time chart showing waveforms and FIG. 11 is a circuit diagram of a portion of this embodiment. 10' is a sustain and write drive circuit, 20' is a write switch circuit, 30 is a data switch circuit, 40 is a write line separation and sustain amplitude holding circuit, and 50 is a matrix panel 60 made of thin film EL elements, a write preparation circuit. .

Claims (1)

[Claims] 1. In a drive device for an EL display device that is equipped with matrix electrodes in the X direction and the Y direction and has an AC hysteresis phenomenon, a capacitor connected in series to one of the electrodes, and a write preparation voltage and a voltage connected to the other end of the capacitor are connected. A power supply circuit that supplies a write voltage is connected to the connection point between the one electrode and the capacitor and the other electrode, and the write line of the other electrode is turned on and the other non-write line is turned off. When supplying the write preparation voltage before applying the write voltage to the write picture element, the write line of one of the electrodes is turned off, the other non-write line is turned on, and when the next write voltage is applied, one of the above electrodes is turned off. An EL display characterized by comprising a switch circuit consisting of an N-channel MOS transistor or a high-polar NPN transistor, in which the source or emitter of both electrodes is commonly connected to ground, and which turns off all lines of electrodes. Device drive.