JPS5934696A - Many circuit boardsand method of producing same - Google Patents

Many circuit boardsand method of producing same

Info

Publication number
JPS5934696A
JPS5934696A JP14416182A JP14416182A JPS5934696A JP S5934696 A JPS5934696 A JP S5934696A JP 14416182 A JP14416182 A JP 14416182A JP 14416182 A JP14416182 A JP 14416182A JP S5934696 A JPS5934696 A JP S5934696A
Authority
JP
Japan
Prior art keywords
circuit
resin
layer
wiring board
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14416182A
Other languages
Japanese (ja)
Inventor
英夫 町田
川上 伸
柳田 具美
安喰 満範
節夫 鈴木
松井 泰雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP14416182A priority Critical patent/JPS5934696A/en
Publication of JPS5934696A publication Critical patent/JPS5934696A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はスルーホールめっき工程を経ることなく作られ
る多層配線基板及びその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board that can be made without a through-hole plating process, and a method for manufacturing the same.

従来、両面銅張板又は多層回路用銅張板を用いて層状に
回路を形成、させる際に、各々の層間の接続にはドリル
、又はパンチング等の穿孔加工を施し、これに力jT%
解めっきもしくは無電解めっきと電解めっきとを付設す
るいわゆるスルーホールめっきによる回路の払・続が行
われていた。
Conventionally, when forming a circuit in layers using a double-sided copper clad board or a copper clad board for multilayer circuits, the connection between each layer was perforated by drilling or punching, and then a force jT% was applied to the connection between each layer.
Circuits were removed and continued by so-called through-hole plating, which is a combination of deplating or electroless plating and electrolytic plating.

しかるに、スルーホールめっき加工とは例えば基板の材
質の品位が低いとき、吸湿による孔壁の絶縁劣化、g&
湿、乾燥、加熱冷却による厚み方向の伸縮に伴うめっき
の劣化、またいわゆるスメア、ネイルヘッド等の穿孔条
件の不適合に伴う付設めっきの品質低下等、回路の信頼
性を低下させる因子が数多くありこれらの因子を高度に
排除せんがため、そのシステムから生産される多層配g
IJ1基板はきわめて高価なものになっているのが現状
である。
However, when through-hole plating is used, for example, when the quality of the substrate material is low, insulation deterioration of the hole wall due to moisture absorption,
There are many factors that reduce circuit reliability, such as deterioration of plating due to expansion and contraction in the thickness direction due to humidity, drying, heating and cooling, and deterioration of the quality of attached plating due to unsuitable drilling conditions such as so-called smear and nail head. In order to highly eliminate the factors of
Currently, IJ1 boards are extremely expensive.

一方、スルーホールめっきのな、い多M板として、あら
かじめ形成された回路層の上に絶縁層を介して導電性ペ
ーストを印刷することにより、また、この工程を絆り返
すことにより2層目、3層目等々の回路を形成して多層
配線板とする方法が知られている。
On the other hand, as a multi-M board without through-hole plating, a conductive paste can be printed on a pre-formed circuit layer through an insulating layer, and by repeating this process, a second layer can be created. , a third layer, etc., to form a multilayer wiring board is known.

しかるに、導電性ペーストだけでは回路の導電性が銅、
ニッケル等の金属回路より劣る。
However, with conductive paste alone, the conductivity of the circuit is lower than that of copper.
Inferior to metal circuits such as nickel.

この点を改魯するため、導電性ペーストとして銅粉を添
加した樹脂を用いて回路印刷し、無電解めっき浴中で露
出した銅粉を触媒として金属めっきを析出させる方法も
案出されている。しかし、この方法を用いても、析出す
るめつきが不均一で密着性の弱いものであり、断線し易
い傾向にあるためやはり十分な信頼性のある導電回路に
はなっていない。
In order to improve this point, a method has been devised in which circuits are printed using resin to which copper powder is added as a conductive paste, and metal plating is deposited using the copper powder exposed in an electroless plating bath as a catalyst. . However, even if this method is used, the deposited plating is non-uniform, has weak adhesion, and tends to be easily disconnected, so that a conductive circuit with sufficient reliability still cannot be obtained.

また、片面板で回路が立体的に交叉する部分をジャンパ
ー線と称する金属線で接続する方法が常用されるが、こ
の方法は基板に密着固定された配線でないため、浮遊容
量等が変動し易く信号回路ではノイズを拾う原因になり
やすかった。
In addition, a method is commonly used in which the parts of a single-sided board where the circuits intersect three-dimensionally are connected using metal wires called jumper wires, but since this method is not a wiring that is tightly fixed to the board, stray capacitance etc. are likely to fluctuate. Signal circuits tend to pick up noise.

本発明は、これらの事例のような欠点を持たない多層配
線基板とその製造方法を提供すの穿設の煩雑さがなく 
各層の回路と層間の接続は信頼性の高い金属めっきで絶
縁層と回路層とが空隙なく一体化[i’il定され、加
工法が容易であると同時に形成された回路の信!lす性
が高い多層配線基板とそのPJ造方法に関する。
The present invention provides a multilayer wiring board that does not have these drawbacks and a method for manufacturing the same, which eliminates the hassle of drilling.
The circuits in each layer and the connections between the layers are made using highly reliable metal plating, so that the insulating layer and the circuit layer are integrated without any gaps. The present invention relates to a multilayer wiring board with high lubricating properties and a PJ manufacturing method thereof.

以下、本発明の多層“j配線基板とその製造方法の具体
的な実施例について詳細に説明する。
EMBODIMENT OF THE INVENTION Hereinafter, specific embodiments of a multilayer "J" wiring board and a method of manufacturing the same according to the present invention will be described in detail.

まず、本発明において基底層の金、匡導体回路と第2の
金属導体回路を述べたものは、基板の片面に枯成された
WR・jの回r!ンのうち、内層側の回路を基底層、外
層側の回に、1を第2の金属導体回路とした。金Fη)
(体重計の材質としては特に限定はしないが、銅を使用
することは回路の導通がすぐれ加工もし易いので望まし
い。回路をパターン状に形成する技術は従来から行われ
ている、いわゆるフォイルエッチ法又はアディティブめ
っき法を応用すれば良い。即ち、基底層の回路の例では
、片面銅張板上にスクリーン印刷によってエツチングレ
ジストインクを印刷し、硬化せしめ、エツチングにより
所望のパターンの金属導体回路を得ることができる。ま
た、基底層の回路自体がすてに複層化されたものであっ
ても良い。
First, in the present invention, the base layer of gold, the solid conductor circuit, and the second metal conductor circuit are composed of WR*j circuits formed on one side of the substrate. Among the circuits, the circuit on the inner layer side was used as the base layer, the circuit on the outer layer side was used as the second metal conductor circuit. Gold Fη)
(There are no particular restrictions on the material for the scale, but it is preferable to use copper because it has excellent circuit conductivity and is easy to process.The technology for forming the circuit into a pattern is the conventional foil etching method. Alternatively, an additive plating method may be applied. In other words, in the case of a base layer circuit, etching resist ink is printed on a single-sided copper clad plate by screen printing, hardened, and etched to obtain a metal conductor circuit in the desired pattern. Furthermore, the base layer circuit itself may be multi-layered.

更に、本発明では電気絶縁性を有する樹脂層とそこに形
成された金属導体回路とが浮上することなく”Jf:着
していることが特徴である。
Furthermore, the present invention is characterized in that the electrically insulating resin layer and the metal conductor circuit formed thereon are attached to each other without floating.

回路の引きはがし強さは特に限定しないが、望ましくは
0」〜ら以上、さらに望ましくは1.0k19/crr
L以上である方がよい。該樹脂層の所要箇所で慧明きさ
れた部分において、該樹脂層をはさむ内外の回路が金属
同志のめっきで一体化接続されているため、電気的には
接触抵抗が小さく、機械的にも強い接続がされている。
The peeling strength of the circuit is not particularly limited, but it is preferably 0'' to more than 1.0k19/crr, more preferably 1.0k19/crr.
It is better to be L or higher. The internal and external circuits sandwiching the resin layer are integrally connected using metal-to-metal plating in the required areas of the resin layer, so electrical contact resistance is low and mechanically strong. Connection is made.

そのため、基板の材質は通常はスルーホールめっきに用
いるには信頼性に多くの不安を与える比較的汎用級のも
のであってもガラス布エポキシ樹脂銅張板を使用したス
ル−ホールめっきに劣らない導通ト;・続の信頼性が得
られる。
Therefore, even though the substrate material is usually a relatively general-purpose material that causes many concerns about reliability when used for through-hole plating, it is still as good as through-hole plating using glass cloth epoxy resin copper clad board. Continuity and continuity can be achieved.

該樹脂層としては、熱硬化性樹脂、熱可塑性樹脂、ゴム
もしくは合成ゴム、及びこれらの混合物、即ちフェノー
ルト“J脂、工目rキシ樹用イ、メラミン41W脂、ポ
リビニルブチラール樹脂、ポリブタジェンゴム、アクリ
ロニトリルゴム、等々を単独又は混合、変性して使用す
ればよい。
The resin layer may include thermosetting resin, thermoplastic resin, rubber or synthetic rubber, and mixtures thereof, such as phenol resin, phenol resin, melamine 41W resin, polyvinyl butyral resin, and polybutylene resin. Gen rubber, acrylonitrile rubber, etc. may be used alone or in combination or modified.

該樹脂の中に印刷特性をNl!4整するための各朴の添
加剤、無機フィラー等が均一に混合分散されていてもよ
い。一方、該樹脂層は撥数の層を密着させて一体化した
層として用いることもできる。この場合、少なくとも最
も外側の層は5%以上のゴムもしくは合成ゴムが配合さ
れた変性熱硬化性樹脂もしくは混合樹脂からなるときは
、第2の金属導体回路のジ]きはがし強さが特に増大化
する卸向かあり、多層回路の接続の信頼性を高めるりJ
1果が著しい。
Nl printing properties in the resin! Various additives, inorganic fillers, etc. for conditioning may be uniformly mixed and dispersed. On the other hand, the resin layer can also be used as an integrated layer in which several layers are brought into close contact with each other. In this case, when at least the outermost layer is made of a modified thermosetting resin or mixed resin containing 5% or more of rubber or synthetic rubber, the peel strength of the second metal conductor circuit is particularly increased. There is a need for wholesalers to improve the reliability of connections in multilayer circuits.
One fruit is remarkable.

次に、該樹脂層において基底層の回路の上に露出させて
おきたい部分だけを窓明けするには公知の種々の方法の
中から適当なものを選択して実施することができる。例
えば、該樹脂層を半硬化のフィルム状にして打抜加工で
窓明は箇所のみを除失したものを基底層の回路上に位置
合せして熱融着後、硬化させる方法とか、該樹脂層をペ
ースト状として、例えばスクリーン印刷法などにてパタ
ーンを作成するにあたり、窓明は部には該樹脂インクが
塗工されないような版を用いる方法等が望ましいと思わ
れる。
Next, in order to open a window in only the portion of the resin layer that is desired to be exposed above the circuit of the base layer, an appropriate method can be selected from among various known methods. For example, the resin layer may be made into a semi-cured film and only the window holes removed by punching, which is then aligned on the circuit of the base layer, heat-sealed, and then cured. When forming a pattern using a paste-like layer and using a screen printing method, for example, it is preferable to use a plate in which the resin ink is not applied to the window areas.

第2の金属導体回路としては、七ミアデイテイプ法、又
1デデイテイブ法などの手段によって金属めっきの回路
を析出させることができる。これらの手段で金属めっき
の回路を析出させるにあたって、めっきを析出させる部
分に、前もって機械的に又は化学的に、かつ微細で均質
に表面を粗化しておくとめっきの密着性を向上させるの
に有効である。この場合、絶縁層の全た7、又は表面層
が5%以上のゴムもしくは合成ゴムが配合された変性熱
硬化性樹脂もしくは混合樹脂からなるときはクロム酸・
硫酸混液等の化学粍化を行うことにより、好ましい粗化
面を形成するのに好都合合である1、 実施例 L 紙基材エポキシ樹脂片面合一張板スミライト北who−
4152(住人ベークライト製)に第1図に示す回路を
エツチング法により作成した。この上に電気絶縁性樹脂
層として、エポキシ用≦液性ソルダーレジストインク、
タムラのSR−γQG/MX−5を使用し、第2図に示
されるパターンの如くパット部のみを窓明けしたパター
ンで全面を約50μm厚さに被覆し硬化させる。この基
板表面を煮320の砥粒(トサ゛エメリー)で全面ムラ
なく微細に粗化した。続いて、通常の無電解めっき工程
に準じて塩酸処理、カタリスト処理、及びアクセレレー
タ処理を経て無電解釦1めつきを全面に約%μm析出さ
せる。さらに、全面に硫酸銅めっき浴にて電解めっきを
約20μm析出さぜた。これにレジストを印刷し、第3
図に示す回路をエツチング法により作成した。その結果
得られた2層(多層)配線板の回路は第4図に示される
。レジストを除去後、表面に再度第2図に示すパターン
のソルダーレジストを電気絶縁性樹脂層として被Uする
ことにより 回路を加工中の熱的、機械的なショックを
防ぐ処理としての加工も可能である。
As the second metal conductor circuit, a metal plating circuit can be deposited by means such as a seven-mia day tape method or a one day tape method. When depositing metal plating circuits using these methods, it is recommended to mechanically or chemically roughen the surface of the area where the plating is to be deposited in a fine and homogeneous manner in order to improve the adhesion of the plating. It is valid. In this case, if the entire insulating layer or the surface layer is made of a modified thermosetting resin or mixed resin containing 5% or more of rubber or synthetic rubber, chromic acid.
It is convenient to form a preferable roughened surface by chemical agitation such as a sulfuric acid mixture. 1. Example L Paper base epoxy resin single-sided laminated board Sumilite Kita who
4152 (manufactured by Juju Bakelite) by etching the circuit shown in FIG. On top of this, as an electrically insulating resin layer, epoxy ≦ liquid solder resist ink,
Using Tamura's SR-γQG/MX-5, the entire surface was coated to a thickness of about 50 μm with a pattern shown in FIG. 2 in which only the pad portions were opened, and then cured. The surface of this substrate was evenly and finely roughened over the entire surface with 320 abrasive grains (Tosa Emery). Subsequently, electroless button 1 plating is deposited to a thickness of about % μm over the entire surface through hydrochloric acid treatment, catalyst treatment, and accelerator treatment according to a normal electroless plating process. Furthermore, about 20 μm of electrolytic plating was deposited on the entire surface in a copper sulfate plating bath. Print a resist on this and print the third
The circuit shown in the figure was created using the etching method. The circuit of the two-layer (multilayer) wiring board obtained as a result is shown in FIG. After removing the resist, by covering the surface with a solder resist with the pattern shown in Figure 2 again as an electrically insulating resin layer, it is possible to process the circuit to prevent thermal and mechanical shock during processing. be.

実施例 2゜ 紙基材フェノール樹脂片面銅張積層板スミライトlc!
lo−2321(住人ベークライト製)に第1図に示す
回路をエツチング法により作成した。この上に、電気絶
縁性樹脂として紫外線硬化型レジストインクH工R(中
央銘板工業)を使用し、第2図に示される/ぐターンの
如く、バット部のみを惣明けしたノでターンで全面を約
30μm厚さに被覆し硬化さぜた。この塗膜の上に再反
第2図のパターンにて、 ニトリルゴム ニツボール1001  (日本ゼオン)
40部エホキシ樹脂 エピコーN0O1(シェル>  
   20部P、P−ジアミノジフェニルメタン   
     2部アエロジル             
      2部ベンジルアルコール        
      適 量を混合溶解したゴム変性熱硬化性枳
脂インクをH工Rの場合と同一パターンで印刷して、十
分乾燥させ約20μmの険pを形成させた。
Example 2゜Paper base phenolic resin single-sided copper clad laminate SUMILITE LC!
The circuit shown in FIG. 1 was created on LO-2321 (manufactured by Juju Bakelite) by etching. On top of this, ultraviolet curable resist ink H Engineering R (Chuo Meiban Kogyo) is used as an electrically insulating resin, and as shown in Figure 2, the entire surface is turned after opening only the butt part. was coated to a thickness of about 30 μm and cured. On top of this coating film, apply nitrile rubber Nitsuball 1001 (Nippon Zeon) in the pattern shown in Figure 2.
40 parts epoxy resin Epicor N0O1 (shell>
20 parts P,P-diaminodiphenylmethane
Part 2 Aerosil
2 parts benzyl alcohol
Appropriate amounts of the rubber-modified thermosetting resin ink were mixed and dissolved and printed in the same pattern as in the case of H-KoR, and sufficiently dried to form a rough patch of about 20 μm.

欣いで、 0r03  100g a2so43QQmJ 水       6001nl の早成で混合して作られた化学粗化液55℃中に5分間
浸漬した。これを十分水洗した後、実施例りに述べたの
と同一の通常の無電解めっき及び電解めっき工程に早し
て塩6シ処理以後の工程を行い、約20μmの電解めっ
き鋼を析出させた。更に、第3図に示す回路をエツチン
グ法により作成した。その結果第4図に相当する2層配
線板が得られた0 実施例 う。
Then, it was immersed for 5 minutes in a chemical roughening solution at 55° C. prepared by pre-mixing 0r03 100g a2so43QQmJ water 6001nl. After thoroughly rinsing this with water, the same normal electroless plating and electrolytic plating process as described in the example was carried out, followed by the salt treatment and subsequent steps to deposit about 20 μm of electrolytic plated steel. . Furthermore, the circuit shown in FIG. 3 was created by an etching method. As a result, a two-layer wiring board corresponding to that shown in FIG. 4 was obtained.

実施例とで得られた2層配線板の表面に、実施例Zにて
使用した絶縁インク、すなわち■工R+ゴム変性熱硬化
性樹脂インクを第2図のパターンのように印刷し、全面
を化学粗化した徒、塩酸、塩化パラジウム−塩化第一錫
の塩酸溶液、アクセレレータ処理する。これを一旦乾燥
して第5図のパターンをUV硬化型ソルダー・メツキレ
シストインクにて印刷し、無電解ニッケルめっき浴ナイ
コS (キザイ)に浸漬した。30℃で3時間処理した
結果、第5図のパターンの印刷で被覆されていない部分
にニッケルめっきが厚付けされ、基板全体として第6図
に示すような3層の回路からなる配線板が全くスルーホ
ールめっきを用いずに形成された。
On the surface of the two-layer wiring board obtained in Example Z, the insulating ink used in Example Z, that is, ■Product R + rubber-modified thermosetting resin ink, was printed as in the pattern shown in Figure 2, and the entire surface was printed. Chemically roughened waste, hydrochloric acid, palladium chloride-stannic chloride hydrochloric acid solution, accelerator treatment. This was once dried, and the pattern shown in FIG. 5 was printed using UV-curable solder/metsukiresist ink, and then immersed in an electroless nickel plating bath Nyco S (Kizai). As a result of treatment at 30°C for 3 hours, nickel plating was applied thickly to the areas not covered by the printing of the pattern shown in Figure 5, and the entire board consisted of three layers of circuits as shown in Figure 6. Formed without using through-hole plating.

比較例 L 紙フェノール系片面銅張板PLo−2321板厚1.6
朋を用い、第2図に対応して各窓明き相当箇所に直径1
朋のドリルで穴明けし、通常の銅スルーホールめっきプ
ロセスニ従って次の工程で厚さ20μmの工φ−ホール
めっきを施し、両面銅めつき枡とした。これの表面に第
1図のパターンで、め而に第3図のパターンでドライフ
ィルムレジストによりテンティングし、続いてレジスト
で破傷されずE出している釧をエツチングして回路を残
し、回路表面上のレジストを除去すれば、スルーホール
めっき法により、第4図に示す回路と等価な2層(両面
)配線板が得られる。
Comparative example L Paper phenolic single-sided copper clad board PLo-2321 board thickness 1.6
1 diameter at each window opening corresponding to Fig. 2.
A hole was drilled with my drill, and the next step was plating of a 20 μm thick φ-hole using the usual copper through-hole plating process, resulting in a double-sided copper-plated square. The surface of this was tented with a dry film resist in the pattern shown in Figure 1, and then in the pattern shown in Figure 3.Then, the resist was etched to leave the circuitry intact and exposed. If the resist on the surface is removed, a two-layer (double-sided) wiring board equivalent to the circuit shown in FIG. 4 can be obtained by through-hole plating.

比較例 2 ガラス布基材エポキシ樹脂片面絹張板スミラ・イトEI
+0−4756  (住方ヘークライト)を用いて第1
図に示す回路をエツチング法により作成した。この表向
に、実fffii例2.の場合と同様にして第2図のパ
ターンでH工Rを約30μm厚さに形成し硬化させた。
Comparative example 2 Glass cloth base epoxy resin single-sided silk clad board Sumira Ito EI
+0-4756 (Jumikata Heckley)
The circuit shown in the figure was created using the etching method. On the surface of this, actual fffii example 2. In the same manner as in the case of 2, H-work R was formed to a thickness of about 30 μm in the pattern shown in FIG. 2 and hardened.

この表面に銅粉入りフェノール樹脂系導電性ペーストを
第3]てに示すパターンで印刷し焼付けた。
On this surface, a phenolic resin conductive paste containing copper powder was printed and baked in the pattern shown in the third step.

この表面を液体ホーニングによって粗化し、無電解鋼め
っき浴の中につけると、ペースト膜の表面に露出してい
る銅粉の触媒作用により、銅めっきが回路部に析出する
。約10μのめっきが析出した。そして、第4図に示さ
れる回路と等価な2層回路の配線基板が得られた。
When this surface is roughened by liquid honing and placed in an electroless steel plating bath, copper plating is deposited on the circuit section due to the catalytic action of the copper powder exposed on the surface of the paste film. Approximately 10μ of plating was deposited. A wiring board with a two-layer circuit equivalent to the circuit shown in FIG. 4 was obtained.

これらの実施例及び比較例について評価した結果を表I
に示す。
Table I shows the evaluation results for these Examples and Comparative Examples.
Shown below.

表中の導通信頼性は一60℃30分〜125℃30分を
1サイクルとする導通劣化促進条件で処理後、導通抵抗
値が初期の20%以内に留まるサイクル数を表わしてい
る。
The continuity reliability in the table represents the number of cycles in which the continuity resistance value remains within 20% of the initial value after treatment under conditions that promote continuity deterioration, with one cycle of 30 minutes at -60°C to 30 minutes at 125°C.

表■から見ると、実施例で乎皆〜性は0.4kgf /
 cm以」二であるが、比較例でのめつきは密着力がき
わめて微小である。しかも、析出しためつきの粒子が粗
大であり、従って導通信頼性もよくない。
Looking at Table ■, the total weight in the example is 0.4 kgf/
However, the adhesion strength of the plating in the comparative example is extremely small. Moreover, the precipitated particles are coarse, and therefore the continuity reliability is also poor.

また、比較例1.では紙基材フェノール樹脂両面銅張積
層板の両面スルーホールめっき回路を作成したのである
が、導通信頼性は20ヤイクルまでしか保てず、スルー
ホール部で511.通不良が発生した。
Also, Comparative Example 1. We created a double-sided through-hole plating circuit using a paper-based phenolic resin double-sided copper-clad laminate, but the continuity reliability could only be maintained up to 20 cycles, and the through-hole section had a resistance of 511. A communication failure has occurred.

一方、各実施例では、第2層及び第3層の回路には粒子
の微細なめっきが形成され、基底層との接続や絶縁性イ
ンク又はこれに塗重ねられているゴム配合インク層との
密着性は強固である。特に、実施例26、う、でのめつ
きは強固に密着されている。比較例]、と同じブレイド
の銅張板を用いながら、導通信頼性はきわめて良好であ
ることが明らかである。
On the other hand, in each example, fine particle plating is formed on the circuits of the second and third layers, and is connected to the base layer and to the insulating ink or the rubber compound ink layer coated thereon. Adhesion is strong. In particular, the plating in Example 26 was firmly adhered. It is clear that the conduction reliability is extremely good even though the same braided copper clad plate as in [Comparative Example] is used.

表■の評価項目の方法について説明する。The method for the evaluation items in Table ■ will be explained.

「引剥強度」 該当する層の回路が形成された1≦2階で回路面に対し
90方向に引剥すのに要する力を回路中で除する。実施
例3の@3JN(Niめつき)及び比較例乙の第2層(
炉電解Ouめっき厚付)は共にめっき金属としての展延
性が乏しいので、セロハン粘着テープをめっき金属面に
貼付は補強して評価した。
"Peeling Strength" The force required to peel off the circuit in the 90 direction from the circuit surface at the 1≦2th floor where the circuit of the corresponding layer is formed is divided by the circuit. @3JN (Ni plating) of Example 3 and the second layer of Comparative Example B (
Since both the furnace electrolytic Ou plating (with thick furnace electrolysis) had poor spreadability as a plated metal, cellophane adhesive tape was attached to the plated metal surface for reinforcement for evaluation.

1半田耐熱性」 回路が形成された〃で板をそのま\半田浴の表面に浮か
べて、ふくれ発生までの時間を測定した。
1 Solder Heat Resistance After the circuit was formed, the board was floated on the surface of the solder bath, and the time until blistering occurred was measured.

「絶縁耐圧」 第41ズ1又は第6図の端子1と7間にて測定した。"Dielectric strength voltage" Measurement was made between terminals 1 and 7 in No. 41 and 1 in FIG.

「導通信頼性」 端子1−2.3−4.5−6.7−8.9−IC1tf
→1(但し、実施例う、の第3層については端子1B−
19間)の導通抵抗の変化が初期値の+20%を超える
までのサイクル数で表わした。
"Continuity reliability" Terminal 1-2.3-4.5-6.7-8.9-IC1tf
→1 (However, for the third layer of Example U, terminal 1B-
It is expressed as the number of cycles until the change in conduction resistance (between 19 and 19) exceeds +20% of the initial value.

各実施例及び比較例で得られた配線板に関する特性評価
結果を表1に示す。
Table 1 shows the characteristics evaluation results for the wiring boards obtained in each example and comparative example.

表 I 特性評価結果Table I Characteristic evaluation results

【図面の簡単な説明】[Brief explanation of drawings]

第1〜6図は回路の構成を説明するための実施例及び比
較例に使用したテストノぐターンで、第1図は基底層回
路パターン、第2図は樹脂被侃パターン、第3図は第2
層回路/ぐターン、第4図は2層配線回路ノくターン配
置図、第5図は第3層回路パターン、第6図は3層配線
回路パターン配線図をそれぞれ示すものである。 1・・・銅箔エツチング回路 2・・・基板接着面 3*・・窓明は箇所 4・・・電気絶縁樹脂層 5・・・銅めつき回路 6・・・樹脂被覆表面 7・・Φ基底層回路パターン 8拳・・第2fV41曲路パターン 9・・・回路不在部 10・・φ窓明は箇所 11@・・樹脂被楯表面 12・・・基底層(ロ)路パターン 13・・・第2層回路パターン 14・命・第3層回路パターン 15・・・回路不在部 住友ベークライト株式会社
Figures 1 to 6 are test patterns used in Examples and Comparative Examples to explain the circuit configuration. Figure 1 is the base layer circuit pattern, Figure 2 is the resin covering pattern, and Figure 3 is the test pattern. 2
FIG. 4 shows a layout diagram of a two-layer wiring circuit, FIG. 5 shows a third-layer circuit pattern, and FIG. 6 shows a wiring diagram of a three-layer wiring circuit pattern. 1...Copper foil etching circuit 2...Board adhesive surface 3*...Window brightness is at point 4...Electrical insulating resin layer 5...Copper plating circuit 6...Resin coating surface 7...Φ Base layer circuit pattern 8 fist...2nd fV41 curve pattern 9...Circuit absent area 10...φ window light is at location 11@...Resin shield surface 12...Base layer (b) road pattern 13...・Second layer circuit pattern 14・Life・Third layer circuit pattern 15...Circuit absent part Sumitomo Bakelite Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] (1)基板1枚につき2M以上の回路が形成1されてい
る多層配線基板において、基底層の金属導体回路上に電
気絶縁性を有する樹脂層が施され、かつ該樹脂層に蕃着
して第2の金属導体回路が形成され、該樹脂層には所要
箇所に窓明きされている部分があって、第2の回路と基
底層の回路とがその部分で電気的に導通されており、か
つその接続綿がめつきによる金属同志の接続で構成され
ていることを特徴とする多Jfff配線基板。
(1) In a multilayer wiring board in which 2M or more circuits are formed per board, a resin layer having electrical insulation properties is applied on the metal conductor circuit of the base layer, and the resin layer is adhered to the resin layer. A second metal conductor circuit is formed, and the resin layer has portions with windows at required locations, and the second circuit and the base layer circuit are electrically connected at those portions. A multi-Jfff wiring board, characterized in that it is constructed by connecting metals together by bonding, and connecting metals by plating.
(2)該樹脂層がそれ自体史に複数の絶縁樹脂片?から
形成されており、そのうぢ少なくとも最も外側の層は5
%以上のゴムもしくは合成ゴムが配合された変性熱硬化
性樹脂もしくは混合植脂から成ることを特徴とする特#
’f ft17求の範囲第1項記載の多層配線基板。
(2) Does the resin layer itself consist of multiple insulating resin pieces? At least the outermost layer is made up of 5
% or more of rubber or synthetic rubber.
'f ft17 The multilayer wiring board according to item 1.
(3)基板の片面もしくは両面に金属から成る基底層の
回路があり、その表面に舘出させておきたい部分だけ窓
明けして、他の部分には電気絶縁性樹脂層を塗着硬化せ
しめ、かくして得られん基板の該樹脂の塗羞硬化部と窓
明は部の各々について全面もしくはその−e=+:分を
金属めっきで回路を形成させる工程を含むことを特徴と
する多層配線基板の製造方法。
(3) There is a base layer circuit made of metal on one or both sides of the board. Open windows only in the parts that you want to expose on the surface, and apply and harden an electrically insulating resin layer to the other parts. , a multilayer wiring board characterized in that the coating photocured portions and the window coating of the resin of the thus obtained substrate include a step of forming a circuit by metal plating the entire surface or the −e=+: portion thereof. Production method.
(4)該樹脂層の塗着硬化工程が複数回の塗着硬化作業
の反覆から成り、そのうち少なくとも最後の塗着硬化作
業に使用する樹脂が5%以上のゴム又は合成ゴムが配合
された変性熱硬化性樹脂もしくは混合樹脂から成ること
を特徴とする特許請求の範囲第3項記載の多層配線基板
の製造方法。
(4) The coating and curing process of the resin layer consists of repeating the coating and curing operations multiple times, and the resin used in at least the last coating and curing operation is a modified rubber or synthetic rubber compounded in an amount of 5% or more. 4. The method of manufacturing a multilayer wiring board according to claim 3, wherein the multilayer wiring board is made of a thermosetting resin or a mixed resin.
JP14416182A 1982-08-20 1982-08-20 Many circuit boardsand method of producing same Pending JPS5934696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14416182A JPS5934696A (en) 1982-08-20 1982-08-20 Many circuit boardsand method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14416182A JPS5934696A (en) 1982-08-20 1982-08-20 Many circuit boardsand method of producing same

Publications (1)

Publication Number Publication Date
JPS5934696A true JPS5934696A (en) 1984-02-25

Family

ID=15355613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14416182A Pending JPS5934696A (en) 1982-08-20 1982-08-20 Many circuit boardsand method of producing same

Country Status (1)

Country Link
JP (1) JPS5934696A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS498233A (en) * 1972-05-11 1974-01-24
JPS502059A (en) * 1973-02-28 1975-01-10
JPS50111576A (en) * 1974-02-15 1975-09-02
JPS52145773A (en) * 1976-05-29 1977-12-05 Tokyo Shibaura Electric Co Method of producing multilayer printed circuit board
JPS5627000A (en) * 1979-08-10 1981-03-16 Kikkoman Shoyu Co Ltd Treatment of poultry* livestock skin

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS498233A (en) * 1972-05-11 1974-01-24
JPS502059A (en) * 1973-02-28 1975-01-10
JPS50111576A (en) * 1974-02-15 1975-09-02
JPS52145773A (en) * 1976-05-29 1977-12-05 Tokyo Shibaura Electric Co Method of producing multilayer printed circuit board
JPS5627000A (en) * 1979-08-10 1981-03-16 Kikkoman Shoyu Co Ltd Treatment of poultry* livestock skin

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