JPS5933986B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which the gate trigger sensitivity of a novel semiconductor-controlled rectifying element, such as a thyristor, can be adjusted by an external signal.

In general, the gate current, anode voltage, rate of increase in anode voltage, temperature, light irradiation, etc. required to switch a semiconductor-controlled rectifying element, such as a thyristor, from an off state to an on state are dependent on the semiconductor layer that makes up the thyristor. It strongly depends on the injection efficiency γ of electrons or holes from the emitter region to the base region at both outer junctions of the PNPN junction, the final emitter junction.

In conventional semiconductor-controlled rectifiers, the injection efficiency γ at the emitter junction is determined by the manufacturing process, including the formation of the PNP junction and its surface treatment. It could not be controlled electrically.

For this reason, it has not been possible to provide a function to adjust the gate trigger sensitivity of the semiconductor-controlled rectifying element to an arbitrary magnitude in response to the b1 external signal that is aligned to a desirable value from a circuit perspective.

Furthermore, increasing the gate trigger sensitivity is incompatible with increasing the blocking voltage against high temperatures and high rate of increase in off-state voltage (hereinafter referred to as Dv/Dt), and a solution has been desired. The present invention was made in view of the above-mentioned problems, and is capable of semiconductor-controlled rectification by controlling the injection efficiency γ of the emitter junction of a semiconductor-controlled rectifier, such as a thyristor, by the gate voltage of a field-effect transistor (hereinafter referred to as FET). The aim is to improve the characteristics and expand the functionality of the device.

The drawings will be explained below.

FIG. 1 is a front view of the structure of a semiconductor device showing an embodiment of the present invention.

This is made using a semiconductor such as silicon, and although Figure 1 shows a single P-gate thyristor in which the invention is implemented, it is integrated together with other elements in one semiconductor wafer. The present invention may be implemented in the following. 1 is a semiconductor device according to an embodiment of the present invention;
Reference numeral 2 denotes a thyristor portion, which, as is well known, has a four-layer structure of a P-type emitter region 3, an N-type base region 5, a P-type base region 5, and an N-type emitter region 6.

7 is an anode emitter junction formed between the P-type emitter region 3 and the N-type base region 4, 8 is a collector junction formed between the N-type base region 4 and the P-type base region 5, and 9 is a collector junction formed between the P-type emitter region 3 and the N-type base region 4. This is a cathode emitter junction formed by the P-type base region 5 and the N-type emitter region 6. Reference numeral 10 denotes an insulated gate FET formed in the thyristor portion 2 in cooperation with the thyristor portion 2. An annular FET 10 is formed adjacent to the P-type base region and spaced apart from the N-type emitter region 6 by a predetermined distance. An N-type auxiliary region 11, the N-type emitter region 6, an N-type channel region 12 formed in the P-type base region 5 sandwiched between the regions 11 and 6, and a region on the channel region 12. It consists of a covering gate oxide film 13 such as a silicon oxide film, and a gate electrode GM deposited on this gate oxide film 13.

14 is a PN junction formed by the P-type base region 6 and the N-type auxiliary region 11, 16 is an insulating film such as a silicon oxide film covering the silicon surface, and A. K is a pair of main electrodes that are in low resistance contact with the P-type emitter region 3 and the N-type emitter region 6, respectively, SA is the anode, and K is the cathode.

It should be noted that this cathode K is also used as the source electrode S of the insulated gate type FETlO. Gp is N
It is an electrode that short-circuits the PN junction 14 other than the portion forming the shaped channel region 12, and is a control electrode for flowing a gate current to the P-type base region 5 of the thyristor portion 2.
1. At the same time, it is also a drain electrode D for applying a drain voltage to the N type auxiliary region 11 which becomes the drain region of the insulated gate type FET portion 10. A feature of the structure of this semiconductor device 1 is that the insulated gate type FET section 10 is simultaneously worked into the PNPN four-layer structure constituting the thyristor section 2.

That is, the N-type emitter region 6 is also used as a source region, the N-type auxiliary region 11 is used as a drain region, and the P-type base region 5 existing between the above regions, the gate oxide film 13 thereon, and the gate electrode GM. M. I. S. By forming a structure (metal-insulator-semiconductor), one insulated gate FET is constructed, and the source-drain electrical path of the insulated gate FET bypasses the input signal applied to the control electrode of the thyristor portion. formed to
By controlling the channel conductivity between the source and drain regions of the insulated gate FET, the input signal applied to the control electrode is controlled.

Next, the operation of this semiconductor device 1 will be explained.

In the conventional thyristor, an input signal applied between the control electrode Gp and the cathode K flows from the control electrode Gp to the cathode K via the P-type base region 5 and the N-type emitter region 6. The voltage drop is the voltage applied to the cathode-emitter junction 9, D1. The higher this voltage is, the greater the injection efficiency γ of electrons from the N-type emitter region 6 to the P-type base region 5 becomes. However, in the present invention, because of the N type channel region 12 provided when the silicon oxide film 13 was formed, the source region 6 of the insulated gate type FETlO is connected to the drain region 11, and the P gate electrode Gp The electric path for the input signal formed through the P-type base region 5 is short-circuited by the resistance of the N-type channel region.

FIG. 2 shows the relationship between the voltage VSD between the source and drain and the current 1D between the gate electrode GM and the source electrode, using the N-type emitter region 6 and the N-type auxiliary region 11 as the source region and drain region of an insulated gate FETlO, respectively. FIG. 3 is an operation explanatory diagram in which the voltage GS between the power supply and the power supply terminal S is expressed as a parameter. The fact that the conductivity between the source and drain can be controlled by the magnitude of the voltage VGS applied to the gate electrode GM of the insulated gate type FETIO is the same as the operating principle of the FET.

That is, when a negative voltage is applied to the gate electrode GM with respect to the source electrode S, the P-type base region 5 facing the gate electrode r
Electrons on and near the surface of the DN channel region 12 are rejected, the thickness of the N channel region 12 decreases, and the resistance of the L channel region increases.

Then, at a certain voltage value when a negative voltage is further applied,
The N-type channel region disappears and the L source and drain are insulated. The pinched N-type emitter region 6 is connected to the N-type auxiliary region 11.
There is no short path to the P-type base region 5.
As explained above, since the thickness of the N-type channel region 12 changes depending on the voltage applied to the gate electrode GM, the channel resistance between the N-type emitter region 6 and the P-type base region 5 can be controlled. Accordingly, the amount of electrons injected from the N-type emitter region 6 to the P-type base region 5, that is, the injection efficiency γ, can be controlled.

Then, this electron injection efficiency γ is the N type channel region 1
By opening the gate electrode or applying a positive voltage, the thickness of the N-type channel region 12 increases, and the channel resistance decreases. Accordingly, the injection efficiency increases. γ decreases. Note that by applying a negative voltage to the gate electrode r, . Since the number of electrons injected from the N-type emitter region 6 recombining at the surface of the P-type base region 6 and the N-type channel region 12 is reduced, the injected electrons can effectively flow into the collector junction 8. A reaching effect also occurs.

FIG. 3 shows the gate electrode r in the semiconductor device of FIG.
The minimum current that triggers the thyristor part 2 of this semiconductor device 1 from off to on by applying a voltage GS to the gate electrode Gp and a current to the P gate electrode Gp, that is, the minimum current that triggers the thyristor part 2 of this semiconductor device 1 from off to on, that is, the gate trigger b is the current 1.
It is a characteristic diagram showing the relationship with gt.

In addition, the curve a in the figure shows the characteristic when the temperature is lower than the curve b (however, the temperature is constant). However, at this time, between the main electrodes (
The forward applied voltage between A and K is constant. In this characteristic diagram, the emitter injection efficiency γ increases at higher temperatures (FIG. 3b), so the semiconductor device 1 is turned on with a smaller gate trigger current of 1 gt.

However, by positively applying the gate voltage VGS, the channel resistance decreases, so the rate at which the input current to the P gate electrode Gp is bypassed increases, so it will not turn on unless the gate trigger current 1gt increases. It disappears. In this way, the gate trigger current 1gt can be controlled by the gate voltage VGS.

Therefore, when triggering the semiconductor device 1 by flowing a current through the control electrode Gp, if a negative voltage is applied to the gate electrode GM to quench the channel region 12, a small gate trigger current Gt can be used to switch. be able to.

In addition, if there is no switch when an input signal is applied to the control electrode Gp, a positive voltage is applied to the gate electrode GM, and there is almost no channel resistance, and the current due to one input signal flows from the N-type auxiliary region 11 to the N-type auxiliary region 11. shaped channel area 12,
Since it flows to the N type emitter region 6 and then to the cathode K, the N
Since almost no electrons are injected from the V) type emitter region 6 to the P type base region 5 until the thyristor 2 is turned on, the temperature dependence of the forward breakover voltage VBO and the Dv/Dt characteristics are improved. Additionally, erroneous firing due to external noise etc. is also reduced.

FIG. 4 is an operating characteristic curve diagram showing the relationship between the ambient temperature T and the forward breakover voltage BO when the present invention is applied to a heat-sensitive thyristor using the voltage VGS applied to the gate electrode as a parameter. A heat-sensitive thyristor is a thyristor that is triggered by sensing the ambient temperature, and when the temperature reaches a predetermined temperature, the forward breakover voltage with respect to the applied voltage decreases, thereby switching from off to on.

This switch temperature is determined by the relationship between the voltage applied between the main electrodes, the ambient temperature, and the forward breakover voltage. In this characteristic diagram, L-VGSO with respect to the gate electrode applied voltage VGS is VGS when the gate electrode GM and control electrode Gp are open.
O8l, G82, VO83, VGS4 are gate electrodes GM
At the gate voltage value when a negative voltage is applied to the control electrode and a positive voltage is applied to the control electrode, ・VGSl>VGS2>VGS3>
It is related to VGS4>.

That is, when the negative voltage applied to the gate electrode GM is increased, N
As the thickness of the shaped channel region 12 decreases and the channel resistance increases, the forward breakover voltage VBO decreases and the thyristor switches from off to on at lower temperatures.

Therefore, when the structure of the semiconductor device 1 of FIG. 1 is applied to a heat-sensitive thyristor, the switch temperature can be controlled over a wide range by the voltage applied to the gate electrode GM, and its application functions can be increased. As described above, in the structure of the semiconductor device 1 shown in FIG. 1 which is an embodiment of the present invention, the gate trigger current Gt of the P-gate type thyristor 2 is set to
It can be controlled by GS, and the breakover temperature can be adjusted or controlled at a constant voltage applied between the main electrodes, so it can be applied as a heat-sensitive thyristor.
This results in a semiconductor device with almost no drop in forward breakover voltage even at high temperatures and high Dv/Dt. moreover,
The semiconductor device according to this embodiment can be easily miniaturized because the FET portion is provided within the operating area of the thyristor.
Moreover, it has the advantage of being able to be handled as a single element. FIG. 5 is a structural sectional view showing another embodiment of the present invention, which will be described below. Note that the same or equivalent parts as in the embodiment shown in FIG. 1 are given the same reference numerals.

In the semiconductor device 1 in this embodiment, an N-channel insulated gate FETlO is provided on the thyristor outside the operating region of the P-gate thyristor 2.

Note that the position of the insulated gate FETlO is not limited to the thyristor, and it goes without saying that the FE-T may be provided on a separate substrate as long as it is outside the operating area of the P-gate type thyristor 2. In the figure, 16 is a P-type substrate, 17 is an N-type source region, 1
8 is an N-type drain region, and 19 is an N-type gate region.

The cathode K and control electrode of the P-gate thyristor 2, that is, the DP gate electrode Gp, are each an insulated gate FET.
It is coupled to a source electrode S and a drain electrode D of lO. In this way, the thyristor part 2 and the insulated gate FET
The operation of the semiconductor device 1, in which the portions 10 are formed in different operating regions and the conductive wire has a common horizontal electrode, is similar to the semiconductor device shown in FIG.
Since the conductivity of the N-type channel region 12 between the source region 17 and the drain region 18 is controlled by the magnitude of the voltage VGS applied to the thyristor 2, when the input signal to the thyristor 2 is applied to the control electrode Gp. , since the control electrode Gp and the drain electrode D are common, the input signal is bypassed to the insulated gate type FETlO.

Therefore, in the structure of this semiconductor device 1, the thyristor 2
Input signal to control electrode Gp, gate trigger current 1gt
is the voltage V applied to the gate electrode GM of the insulated gate FETlO.

This means that it can be controlled by S. Further, as in the embodiment shown in FIG. 1, the temperature characteristics and Dv/Dt characteristics are significantly improved at a constant voltage applied between the main electrodes (A-K). 6th
This figure is an equivalent circuit diagram of the embodiment of the present invention shown in FIGS. 1 and 5 above. A voltage VM is applied between the main electrodes of the P-gate thyristor 2 via a load resistor RL.

A control electrode Gp and a cathode K are input signal application terminals.
An input signal voltage VG is applied through a resistor RG. Further, this input voltage VG and the source-drain voltage VSD of the insulated gate type FETlO have a common power source. In this way, the voltage VGS applied to the gate electrode GM of the insulated gate type FETlO causes a current of 1 between the source and drain.

is controlled, the input signal to the control electrode Gp of the P-gate thyristor 2, that is, the gate trigger current 1
gt will be controlled. That is, the power source o of the gate trigger current Gt applied to the control electrode Gp of the P-gate type thyristor 2 is connected to the source of the insulated gate type FETlO,
Since the drain-to-drain power supply is common to VSD, the current from the common power supply is shunted and bypassed.
The gate trigger of the P gate type thyristor is controlled by the current 1gt by the gate voltage VGS of TlO.

The operation has been described above based on the embodiments of the present invention shown in FIGS. 1, 5, and 6.

In the embodiments, a case has been described in which a P-gate thyristor and a channel-type insulated gate FET are used. However, the present invention is not limited to this, and the present invention can be applied to an N-gate thyristor, a thyristor triggered by light or an electric field, and a bidirectional thyristor. It can be applied to semiconductor-controlled rectifying elements such as thyristors. Further, when the present invention is applied to a power thyristor, the channel area may be increased to increase the number of short-circuit points. Furthermore, regarding N-channel type insulated gate FET, P-channel type insulated gate FETl junction type FE-
It will be easily understood that a field effect transistor such as T may be used. As described above, the semiconductor device according to the present invention includes a semiconductor layer consisting of at least four consecutive regions in which adjacent regions have different conductivity types;
a pair of main electrodes provided on the outer region of the semiconductor layer;
a control electrode provided on at least one of the inner regions of the semiconductor layer; a field effect transistor formed inside or outside the semiconductor layer and having source and drain regions and a gate electrode; A source-drain electrical path is formed to bypass an input signal applied to the control electrode, and the electrical conductivity between the source and drain regions of the field effect transistor is controlled so that the input signal is applied to the control electrode. Since the input signal is controlled, the gate trigger current of the thyristor can be easily and effectively adjusted or controlled by a control power source having a high input resistance and a small size.

In addition, it is possible to easily adjust or control the breakover temperature with a constant voltage applied between the main electrodes, and
This has the advantage that a semiconductor device having extremely stable operating characteristics with almost no drop in forward breakover voltage even at high Dv/Dt can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the semiconductor device according to the present invention, FIG. 2 is an explanatory diagram of the operation of the semiconductor device according to the present invention, and FIGS. 3 and 4 are diagrams illustrating the operation of the semiconductor device according to the present invention. FIG. 5 is a sectional view showing another embodiment of the semiconductor device according to the present invention, and FIG. 6 is an equivalent circuit diagram of the embodiment shown in FIGS. 1 and 5. Note that the same or corresponding parts are shown in the figures. 1...
Semiconductor device, 2... Thyristor part, 3...
...P type emitter region, 4...N type base region, 5...P type base region, 6...N
type emitter region, 10... Field effect transistor, 11... N type auxiliary region, 12...
N-type channel region, 17...N-type source region, 18...N-type drain region, A...
Anode, K...Cathode, Gp...Control electrode, S...Source electrode, D...Drain electrode, GM...Gate electrode .

Claims (1)

[Claims] 1. A first conductivity type emitter region, a second conductivity type base region,
A semiconductor layer forming a four-layer structure in the order of a first conductivity type base region and a second conductivity type emitter region, an anode electrode provided in the first conductivity type emitter region, and a cathode provided in the second conductivity type emitter region a control electrode provided in the base region of the first conductivity type; a field effect transistor formed inside or outside the semiconductor layer and having source and drain regions and a gate electrode; , a drain-to-drain electrical path is formed to bypass an input signal applied between the control electrode and the cathode electrode, and conductivity between the source and drain regions of the field transistor is controlled. A semiconductor device characterized in that the input signal applied between a control electrode and the cathode electrode is controlled. 2 a first conductivity type emitter region, a second conductivity type base region,
A semiconductor layer forming a four-layer structure in the order of a first conductivity type base region and a second conductivity type emitter region, an anode electrode provided in the first conductivity type emitter region, and a cathode provided in the second conductivity type emitter region an electrode, a control electrode provided in the first conductivity type base region, a second conductivity type auxiliary region formed in the first conductivity type base region at a predetermined distance from the second conductivity type emitter region; an auxiliary electrode formed on the first conductivity type base region between the second conductivity type emitter region and the auxiliary region through an insulating film of a predetermined thickness; In addition to applying an input signal, the second conductivity type emitter region and the auxiliary region act as a field effect transistor having a source or a drain region, respectively, and the conductivity between the source and drain regions of the field effect transistor is controlled. A semiconductor device characterized in that an input signal applied to the control electrode is thus controlled.