JPS5933929A - Digital/analog converting circuit - Google Patents

Digital/analog converting circuit

Info

Publication number
JPS5933929A
JPS5933929A JP14425782A JP14425782A JPS5933929A JP S5933929 A JPS5933929 A JP S5933929A JP 14425782 A JP14425782 A JP 14425782A JP 14425782 A JP14425782 A JP 14425782A JP S5933929 A JPS5933929 A JP S5933929A
Authority
JP
Japan
Prior art keywords
output
digital
reference input
converter
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14425782A
Other languages
Japanese (ja)
Inventor
Yoshiro Sasano
笹野 良郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14425782A priority Critical patent/JPS5933929A/en
Publication of JPS5933929A publication Critical patent/JPS5933929A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To form the entire input/output characteristics as the N-power characteristic, by using N-set of D/A converters whose maximum value of the output is set by a reference input. CONSTITUTION:Input terminals D0-D3 (4-bit) of the D/A converters 1, 2 are connected in common, an output terminal OUT of the D/A converter 1 is connected to a reference input terminal Ref- of the D/A converter 2, a 0V voltage is applied to a reference input terminal Ref- of the D/A converter 1, a 5V voltage is applied to a reference input terminal Ref+ of the D/A converter 1 via a resistor R1, a 0V voltage is applied to a reference input Ref+ of the D/A converter 2, a 0V voltage is applied to the output terminal OUT of the D/A converter 1 and the reference input Ref- of the D/A converter 2 via a resistor R3, a 0V voltage is applied to the output terminal OUT of the D/A converter 2 via a resistor R4. The output Vout of the D/A converter 2 is VOUT=KX(D/15)<2>, where D is the input digital amount.

Description

【発明の詳細な説明】 産業上の利用分野 この発明はデジタル・アナログ変換回路に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a digital-to-analog conversion circuit.

近年のマイクロコンピュータの発達により、従来アナロ
グ回路で処理していた分野をデジタル処理に置き換え、
高機能化を目ざすことがよく行なわれている。このよう
な場合、処理された最終のデジタル量をアナログ量に変
換しなければならない。例えば溶接電源は、電圧値と電
流値とを指示しなければならないが、溶接ロボットを考
えた場合、どのような電圧値、電流値を与えるかは、ロ
ボット制御装置内のマイクロコンピュータでデジタル処
理される。このデジタルの電流値、電圧値をメータ等で
指示するにはデジタル・アナログ変換回路でアナログ量
に変換しなければならない。
With the recent development of microcomputers, fields that were traditionally processed using analog circuits have been replaced with digital processing.
It is common practice to aim for higher functionality. In such cases, the final processed digital quantities must be converted into analog quantities. For example, a welding power source must specify voltage and current values, but in the case of a welding robot, the microcomputer in the robot controller digitally processes what voltage and current values to give. Ru. In order to indicate these digital current and voltage values with a meter, etc., they must be converted into analog quantities using a digital-to-analog conversion circuit.

従来例の構成とその問題点 通常のデジタル・アナログ変換器(DAC)は、入力を
2進数で与えると、出力が電流または電圧で得られ、そ
の関係は直線状である。この種のDACは、出力の分解
能が入力の2進数の最低単位で定まり、出力は極めて安
定していて再現性に優れている。このDACのほかには
オペレイS/gナルアンプを用いて指数関数、平方根関
数等の関数特性を持たせたものもあるが、この場合は分
解能を厳密に定めるには、1子の安定性が直接関与する
ので、実際上は少々困難である。
Conventional configurations and their problems In a typical digital-to-analog converter (DAC), when an input is given in binary numbers, an output is obtained in the form of current or voltage, and the relationship between them is linear. In this type of DAC, the output resolution is determined by the lowest unit of the input binary number, and the output is extremely stable and has excellent reproducibility. In addition to this DAC, there are also DACs that use operational S/g null amplifiers to have functional characteristics such as exponential functions and square root functions. In practice, it is a little difficult because of the involvement of

DACの適用分野では、出力での分解能が差分てなく、
出力値に比例した量でよい場合が数多く見られる。例え
ば、前述の溶接電源への指示電流値では、差分を基本単
位として制御するのは意味がなく、電流値が小さいとき
は小さな電流増分とし、電流値が大きいときは大きな電
流増分とするのが実用的な制御である。しかしながら、
再現性、!J1品間のばらつきは厳密に押えられなけれ
ばならない。
In the field of DAC application, there is no difference in resolution at the output,
There are many cases where an amount proportional to the output value is sufficient. For example, in the above-mentioned command current value to the welding power source, it is meaningless to control using the difference as a basic unit, and it is better to use small current increments when the current value is small, and large current increments when the current value is large. This is a practical control. however,
Reproducibility,! Variations between J1 products must be strictly controlled.

このようにするには、従来例に記した二つのものの利点
を兼ね備えることが要求される。厳密さを重視して通常
のDACを用いるとすれば、電流の最大値を増分の最小
値で割ったビット長のものが必要となり、電流値の大き
いところでは、極めて無駄な使い方となる。DACのビ
ット長の大きいものは高価であるので、求められている
機能に比し、コストが上昇する。
In order to do this, it is required to combine the two advantages described in the conventional example. If a normal DAC is used with emphasis on accuracy, it will require a bit length equal to the maximum current value divided by the minimum increment value, and this will be an extremely wasteful use where the current value is large. Since DACs with a large bit length are expensive, the cost increases relative to the desired functionality.

発明の目的 この発明は出力の分解能を出力の値に比例させることが
でき、かつ再現性に優れ、製品間でのばらつきが少なく
、安価なデジタル・アナログ変換回路を提供することを
目的とする。
OBJECTS OF THE INVENTION It is an object of the present invention to provide an inexpensive digital-to-analog conversion circuit that can make output resolution proportional to output value, has excellent reproducibility, has little variation between products.

発明の構成 この発明のデジタル・アナログ変換回路は、出力の最大
値を基準入力で設定できるDACをN個(Nは2以上の
整数)用い、第1段のDACの出力で第2段のDACの
基準入力を定め、第2段のDACの出力で第3段のDA
Cの基準入力を定め、これを第N段まで順次行うことに
より、全体の入出力特性をN乗特性としたものである。
Structure of the Invention The digital-to-analog conversion circuit of the present invention uses N DACs (N is an integer of 2 or more) whose maximum output value can be set by a reference input, and uses the output of the first stage DAC to convert the output of the second stage DAC. The reference input of the second stage DAC is determined as the reference input of the third stage DAC.
By determining a reference input of C and sequentially performing this process up to the Nth stage, the overall input/output characteristics are made to be N-th power characteristics.

より詳しく説明する。一般に、DACは、出力の最大値
を定める基準入力を持っており、必要とする出力の最大
ス1aをこの基準入力で定め、一方、2進入力を与えて
前記基準入力を比例分配するのが通常の用い方であるが
、この発明ではDACを直列に並べ、2進入力は共通と
し、基準入力を前段のDAC出力で制御するものである
。こうすることで、例えば2個のDACを直列接続した
場合には全体の出力は人力の乗算となる。よって、N個
のDACを直列に並べればN乗となる。
Let me explain in more detail. Generally, a DAC has a reference input that determines the maximum output value, and the required maximum output level 1a is determined by this reference input.On the other hand, it is preferable to give a binary input and distribute the reference input proportionally. In the present invention, the DACs are arranged in series, the binary inputs are common, and the reference input is controlled by the output of the preceding DAC, which is a common usage. By doing this, for example, when two DACs are connected in series, the overall output becomes a multiplication of human power. Therefore, if N DACs are arranged in series, it becomes the Nth power.

実施例の説明 以下の実施例では2乗特性ケもつデジタル・アナログ変
換回路について説明する。
DESCRIPTION OF EMBODIMENTS In the following embodiments, a digital-to-analog conversion circuit having square-law characteristics will be described.

第1図社実施例で用いられる4ビツトのDACであり、
デジタル久方は入力端子り。−D3に2進数で与えられ
、基準電位V−は基準入力端子Ref−に与えられ、基
準電位7hは基準入力端子Ref+に与えられ、基準入
力端子Ref+が基準入力端子Ref−と同一となるよ
うに電流制限抵抗R全通して基準入力端子Ref+に電
流I。が流れ込む。このときに、DACの出力端子OU
Tへの流入電流IはI=Io・1否−・曲(1) ■。=0二      ・・・・・(2)で与えられる
。Dは入力のデジタル量である。
Figure 1 is a 4-bit DAC used in the company example,
Digital Kugata has an input terminal. -D3 as a binary number, the reference potential V- is given to the reference input terminal Ref-, and the reference potential 7h is given to the reference input terminal Ref+, so that the reference input terminal Ref+ is the same as the reference input terminal Ref-. A current I is passed through the current limiting resistor R to the reference input terminal Ref+. flows in. At this time, the output terminal OU of the DAC
The inflow current I into T is I=Io・1no−・Song (1) ■. =02...Given by (2). D is the input digital quantity.

第・(・1)式より、2進入力りが一定でも、基準電位
V+またはV−を変えれば、出力が液化することが判る
From equation .(.1), it can be seen that even if the binary input is constant, if the reference potential V+ or V- is changed, the output will be liquefied.

実施例のデジタル・アナログ変換回路は、第2図に示す
ように、DAC1、2の入力端子り。−D3を各々共通
接続し、 DAC1の出力端子OUTをDAC2の基準
入力端子Ref−に接続し、DAC1の基準入力端子R
ef−にQVの電圧を加え、DACの基準入力端子Re
f+に抵抗R□を介して5vの電圧を加え、DAC2の
基準入力端子Ref十にQVの電圧を加え、DAC1の
出力端子OUTとDAC2の基準入力端子Ref−に抵
抗R3を介してOVの電圧を加え、DAC2の出力端子
OUT K抵抗R4を介してoVの電圧を加えている。
As shown in FIG. 2, the digital-to-analog conversion circuit of the embodiment has input terminals of DACs 1 and 2. -D3 are connected in common, the output terminal OUT of DAC1 is connected to the reference input terminal Ref- of DAC2, and the reference input terminal R of DAC1 is connected.
Applying the voltage of QV to ef-, the reference input terminal Re of the DAC
A voltage of 5V is applied to f+ via a resistor R□, a voltage of QV is applied to the reference input terminal Ref1 of DAC2, and a voltage of OV is applied to the output terminal OUT of DAC1 and the reference input terminal Ref- of DAC2 via a resistor R3. , and a voltage of oV is applied via the output terminal OUTK resistor R4 of the DAC2.

第2図では最終出方を負で与えるようにしているが、こ
れは回路の説明を簡単にするためで、ここにオペレイシ
ョナルアンブを用いれば、この電圧値は任意となる。ま
た、抵抗R工〜R4は以下の説明を簡単化するため、抵
抗値をすべて同一のRとしているが、同一である必要は
ない。
In FIG. 2, the final output is given as a negative value, but this is to simplify the explanation of the circuit, and if an operational amplifier is used here, this voltage value can be arbitrary. Further, in order to simplify the explanation below, the resistance values of the resistors R to R4 are all assumed to be the same R, but they do not need to be the same.

このデジタル・アナログ変換回路の人出力の関係につい
て求める。まず、前段のDAC1については、 ■o工=5/R・曲(4) が成立する。後段のDAC2Kついては、vOUT=R
−12・・曲(5) l2=Io2・■・・・・・・(6) Io2= Vl/R・・−・−(71 v1= Rx T 1・−・−f8] が成立する。I  、I  はDAC1、DAC2の基
準01   02 電流である。上式を順次代入することで、が得られる。
Find the relationship between the human output of this digital-to-analog conversion circuit. First, regarding the front-stage DAC 1, the following holds true: (4) o = 5/R. For the latter stage DAC2K, vOUT=R
-12...Song (5) l2=Io2・■・・・・・・(6) Io2= Vl/R・・−・−(71 v1= Rx T 1・−・−f8] is established. I , I is the reference 01 02 current of DAC1 and DAC2. By sequentially substituting the above equations, can be obtained.

Dが入力% vOUTが出力であるから、2乗特性であ
る。
Since D is the input percentage and vOUT is the output, it is a square characteristic.

これをグワ7としたのが第3図でちる。出力での分解能
は第(9)式の微分係数1し・Dで与えられ、25 これはこの発明の意図を満足する。
Figure 3 shows this as Gwa 7. The resolution at the output is given by the differential coefficient 1.D of equation (9), which satisfies the intent of the invention.

このように、この実施例のデジタル・アナログ変換回路
は、DAC1、DAC2K同一の2進入力を与え、後段
のDAC2の基準電圧を前段のDAC1の出力で与える
よう圧したため、出力の分解能を出力の2乗に比例させ
ることができ、従来のようなオペレイシ日ナルアンプを
用いるものとは異なり分解能を厳密に定めることができ
、したがって再現性に優れ、さらにDAC1、DAC2
はビット数の多いものを必要としないため、安価である
In this way, the digital-to-analog conversion circuit of this embodiment gives the same binary input to DAC1 and DAC2K, and the reference voltage of DAC2 in the subsequent stage is given by the output of DAC1 in the previous stage, so the resolution of the output is It can be made proportional to the square of the square, and unlike conventional systems that use operational amplifiers, the resolution can be strictly determined, resulting in excellent reproducibility.
is inexpensive because it does not require a large number of bits.

発明の効果 この発明のデジタル・アナログ変換回路は、出力の分解
能を出力のN乗に比例させて入出力特性をN乗特性とす
ることができ、かつ再現性に侵れ、製品間でのばらつき
が少なく、安価であるという効果がある。
Effects of the Invention The digital-to-analog converter circuit of the present invention can make the output resolution proportional to the Nth power of the output and make the input/output characteristics Nth power characteristics, and also reduces reproducibility and variations between products. It has the advantage of being less expensive and less expensive.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の実施例で用いられるDACの構成図
、第2図はデジタル・アナログ変換回路の回路図、第3
図はその人出力特性図である。 1.2・・・DAC%Do〜D3・・・入力端子、 R
ef−・・・基準入力端子、OUT・・・出力端子 第1図 □D 第3図
Figure 1 is a configuration diagram of a DAC used in an embodiment of the present invention, Figure 2 is a circuit diagram of a digital-to-analog conversion circuit, and Figure 3 is a circuit diagram of a digital-to-analog conversion circuit.
The figure shows the person's output characteristics. 1.2...DAC%Do~D3...Input terminal, R
ef-...Reference input terminal, OUT...Output terminal Fig. 1 □D Fig. 3

Claims (1)

【特許請求の範囲】[Claims] 出力の最大値を基準入力で設定可能なN個(Nは2以上
の整数)のデジタル・アナログ変換器の各ビットのデジ
タル入力端子をそれぞれ共通接続し、前記N個のデジタ
ル・アナログ変換器の基準入力端子および出力端子間を
縦続接続したデジタル・アナログ変換回路。
The digital input terminals of each bit of N digital-to-analog converters (N is an integer of 2 or more) whose maximum output value can be set by the reference input are connected in common, and the Digital-to-analog conversion circuit with cascade connection between reference input terminal and output terminal.
JP14425782A 1982-08-19 1982-08-19 Digital/analog converting circuit Pending JPS5933929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14425782A JPS5933929A (en) 1982-08-19 1982-08-19 Digital/analog converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14425782A JPS5933929A (en) 1982-08-19 1982-08-19 Digital/analog converting circuit

Publications (1)

Publication Number Publication Date
JPS5933929A true JPS5933929A (en) 1984-02-24

Family

ID=15357886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14425782A Pending JPS5933929A (en) 1982-08-19 1982-08-19 Digital/analog converting circuit

Country Status (1)

Country Link
JP (1) JPS5933929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179224A (en) * 1986-01-31 1987-08-06 Nec Home Electronics Ltd Digital/analog converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179224A (en) * 1986-01-31 1987-08-06 Nec Home Electronics Ltd Digital/analog converter

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