JPS5933319U - automatic gain control circuit - Google Patents

automatic gain control circuit

Info

Publication number
JPS5933319U
JPS5933319U JP12804782U JP12804782U JPS5933319U JP S5933319 U JPS5933319 U JP S5933319U JP 12804782 U JP12804782 U JP 12804782U JP 12804782 U JP12804782 U JP 12804782U JP S5933319 U JPS5933319 U JP S5933319U
Authority
JP
Japan
Prior art keywords
control circuit
gain control
automatic gain
level
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12804782U
Other languages
Japanese (ja)
Other versions
JPH021950Y2 (en
Inventor
岡田 景吉
一浩 五水井
Original Assignee
富士通テン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通テン株式会社 filed Critical 富士通テン株式会社
Priority to JP12804782U priority Critical patent/JPS5933319U/en
Publication of JPS5933319U publication Critical patent/JPS5933319U/en
Application granted granted Critical
Publication of JPH021950Y2 publication Critical patent/JPH021950Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は先行技術のブロック回路図、第2図はその具体
的な電気回路図、第3図および第4図は他の先行技術の
ブロック回路図、第5図は第3図の具体的な電気回路図
、第6図は本考案の一実施例の電気回路図、第7図は本
考案の他の実施例の電気回路図である。 21.51・・・自動利得制御回路、22・・・電圧増
幅回路、23・・・減衰回路、24・・・電圧増幅/イ
ンピーダンス変換回路、25・・・レベル検出回路、2
6.33.34,36.53・・・トランジスター、 
 ′27〜30. 37. 3B、  45. 46.
 54・・・抵抗、32,35,39,41.42−・
・コンデンサ、43.44・・・ダイオード、52・・
・インピーダンス変換回路。
Figure 1 is a block circuit diagram of the prior art, Figure 2 is a specific electrical circuit diagram thereof, Figures 3 and 4 are block circuit diagrams of other prior art, and Figure 5 is a concrete example of Figure 3. FIG. 6 is an electrical circuit diagram of one embodiment of the present invention, and FIG. 7 is an electrical circuit diagram of another embodiment of the present invention. 21.51... Automatic gain control circuit, 22... Voltage amplification circuit, 23... Attenuation circuit, 24... Voltage amplification/impedance conversion circuit, 25... Level detection circuit, 2
6.33.34, 36.53...transistor,
'27-30. 37. 3B, 45. 46.
54...Resistance, 32, 35, 39, 41.42-.
・Capacitor, 43.44...Diode, 52...
・Impedance conversion circuit.

Claims (1)

【実用新案登録請求の範囲】 一方の入力に与えられる信号のレベルに応じてインピー
ダンスを変化させることにより、他方の入力に与えられ
る信号を減衰して一定レベルとする減衰回路から一定レ
ベルの信号を能動素子に与えて出力するとともに、その
出力信号の一部をレベル検出回路を介して前記一方の入
力に与えるようにした自動利得制御回路において、 前記能動素子の両端には、第1の抵抗および第1の抵抗
よりも十分に犬なる抵抗値を有する第2の抵抗をそ井そ
れ直列に接続し、能動素子と第2の抵抗との接続点から
の増幅されたレベルの信号を前記レベル検出回路に与え
るようにしたことを特徴とする自動利得制御回路。
[Claims for Utility Model Registration] A signal of a constant level is obtained from an attenuation circuit that attenuates the signal applied to the other input to a constant level by changing the impedance according to the level of the signal applied to one input. In the automatic gain control circuit, the signal is supplied to an active element for output, and a part of the output signal is supplied to the one input via a level detection circuit. A second resistor having a resistance value sufficiently higher than that of the first resistor is connected in series, and the amplified level signal from the connection point between the active element and the second resistor is detected as the level. An automatic gain control circuit characterized in that the automatic gain control circuit is configured to provide a gain control circuit.
JP12804782U 1982-08-24 1982-08-24 automatic gain control circuit Granted JPS5933319U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12804782U JPS5933319U (en) 1982-08-24 1982-08-24 automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12804782U JPS5933319U (en) 1982-08-24 1982-08-24 automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPS5933319U true JPS5933319U (en) 1984-03-01
JPH021950Y2 JPH021950Y2 (en) 1990-01-18

Family

ID=30290610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12804782U Granted JPS5933319U (en) 1982-08-24 1982-08-24 automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPS5933319U (en)

Also Published As

Publication number Publication date
JPH021950Y2 (en) 1990-01-18

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