JPS5932806B2 - Multivariable function generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multivariable function generator that generates gradient values of a multivariable function in conjunction with a digital differential analyzer.

Conventionally, in the analysis of dynamic systems that require various multivariable functions, multivariable function generators have been used in addition to various computers, and analytical calculations have been performed using the multivariable functions generated. So-called MVFG (Multi
VariableFunctionGenerator
, ) was used to generate multivariable functions, but this MV
The FG stores in memory the gradient value of the function at each division point of the variable calculated by the digital computer, and when the calculation output of the analog computer reaches any division point, reads the contents of the memory, The MVFG is used to obtain the gradient value of a function, and the configuration of the MVFG is a mixture of analog and digital circuits, which has disadvantages such as the complexity of the interface circuit with the computer and the high price of the MVFG itself. However, there has been a demand for a multivariable function generator that works in conjunction with the digital differential analyzer described below.

In other words, a digital differential analyzer (Digi
talDifferential” to frog aly2e. '
DDA (hereinafter referred to as "DDA") was developed and has received awards in simulations for dynamic systems such as trajectory calculations and circuit analysis because it eliminates the low calculation accuracy and low reproducibility of analog computers, and has features such as high calculation speed and ease of handling. It is being used. Digital computers are also being applied to the analysis of dynamic systems due to the development of various software and higher calculation speeds, but as the calculations become more complex, the time required for calculations increases, which increases the operating cost. Although it has shortcomings such as lack of interactivity with humans, it has excellent quantitative data processing ability, and DDA is considered to compensate for these shortcomings and at the same time combine the advantages of digital and analog computers. has been developed, and calculations using multivariable functions, such as calculating the route of a navigation object, are now required for DDA. Tazushi, DD
Like an analog computer, A is equipped with various calculation elements, and these calculation elements are connected depending on the calculation purpose before use, but essentially it calculates increments or differential values based on the piecewise quadrature method. It is equipped with only one set of arithmetic circuits for economic efficiency in terms of hardware configuration, and ``configures the arithmetic circuit as a desired arithmetic element according to the instruction of the arithmetic mode, stores the arithmetic results in the arithmetic result memory, A serial calculation type is preferred, in which the next calculation element is configured by the next calculation mode command, the calculation result is also stored in another address of the calculation result memory, and this operation is repeated. By accessing the calculation results via the calculation result memory, an operation corresponding to the connection between calculation elements in an analog computer is realized.

Therefore, the DDA executes a predetermined calculation according to the calculation cycle regulated by the synchronization signal, and the calculation result in the previous calculation cycle becomes the calculation input for the current calculation via the calculation result memory, The write address to the operation result memory called ΔZ memory is specified sequentially from the start address of ΔZ memory according to the order of each operation cycle according to the address designation signal from the address counter that operates based on the synchronization signal. Designation of the read address from the memory is performed according to a signal read from the wired memory storing the connection information described above in response to an address designation signal from the address counter.

The present invention generates the gradient value of the multivariable function required by the DDA when performing arithmetic processing using a multivariable function using the DDA, and fundamentally eliminates the drawbacks of the conventional MVFG. A segment point memory that has a purpose and stores a predetermined segment point of a variable and a segment value of a variable corresponding to this segment point are stored for each segment point, and a read address is specified by the output of the segment point memory. a comparator that compares the output of this interval value memory with the variable output from the DDA, and updates the contents of the segment point memory with the approximate segment point closest to the variable output based on the output of this comparator. The present invention provides an extremely effective multi-variable function generator that can be configured entirely by digital circuits, and is equipped with a division point control circuit and sends gradient values according to functions of variables according to approximate division points to the DDA. It is something to do.

Hereinafter, details of the present invention will be explained with reference to figures showing embodiments, but for convenience, DDA will be explained first. Figure 1 shows
This is a block diagram of the entire configuration including the DDA, and is provided with a timing pulse generator TPG that generates clock pulses and various timing pulses as synchronization signals.
A generates an address designation signal and gives it to the connection memory MC that stores connection information and the selector SL, but at the beginning of the calculation cycle when it operates as one calculation element, the selector SL receives the output of the connection memory MC. Since the calculation results are sent to the ΔZ memory MZ as a memory, the contents read from the address of the wired memory MC specified by the address designation signal from the address counter CUA are sent to the ΔZ memory MZ via the selector SL. The contents of the ΔZ memory MZ read out by the addressing signal are sent to the arithmetic circuit 0P as an arithmetic input.

On the other hand, after the arithmetic operation of the arithmetic circuit 0P ends but before entering the next arithmetic cycle, the timing pulse generator TPG generates a switching signal CS as a timing pulse, and the selector S
As a result, the selector SL directly gives the address designation signal from the address counter CUA to the ΔZ memory MZ, and stores the calculation result from the calculation circuit 0P at the specified address at this time. .

It should be noted that the above operations are sequentially repeated in response to the address designation signal from the address counter CUA. In addition, a signal specifying the calculation mode of the calculation circuit 0P in each calculation cycle is stored in the calculation mode memory MM, and is read out according to the address designation signal from the address counter CUA, and then applied to the calculation circuit 0P. Therefore, the circuit 0P operates as a predetermined calculation element in each calculation cycle. In this case, the connection memory MCl operation mode memory MM and the ΔZ memory MZ are at address A.
Each has a total of 256 addresses from dO to Ad255, and according to the change of the calculation cycle by the address counter CUA, the connection memory MC and calculation mode memory M
M is sequentially addressed from its first address, and based on this address, the arithmetic circuit 0P is configured as a predetermined arithmetic element, and at the same time, Δ
The read address of the Z memory MZ is specified, and the arithmetic circuit 0P performs arithmetic operation using this as an arithmetic input, and then gives the result of this arithmetic operation to the ΔZ memory MZ and inputs it to the address counter C.
The UA stores the data in sequentially specified addresses starting from the first address according to the transition of the calculation cycle. In other words, one DD
Regarding A, the calculation elements corresponding to the number of addresses in each memory are configured, and when the total number of addresses is 256, 25
It has become a noh tradition to use six calculation elements in sequence.
In addition, since the calculation result of the calculation circuit 0P is obtained as an increment, the contents of the ΔZ memory MZ also indicate an increase/decrease or no change in the differential value, and the absolute value representing the total amplitude of the variable cannot be obtained from these.・Although it is not possible, Y in the arithmetic circuit 0P
The register YR, which is called a register, is designed to store the added absolute value during arithmetic operations.
It has become preferable to exchange variables via R.

For the above DDA, a multivariable function generator (Digital DifferentialFun) to which this method is applied
ctiOnGenerateOr. Hereinafter, DDFG) is
The main components are a segmentation point memory MN that stores the segmentation points of variables and an interval value memory MX that stores the interval values of variables corresponding to each segmentation point of the variable, and holds the variable output given from the register YR of the DDA to these. It is constructed by adding a variable latch circuit LX and a gradient value memory MG that stores the gradient values of the function corresponding to each division point of the variable. The actions of people are becoming regulated.
Here, taking an example of a function f(x) with one variable x, its value D
Assuming that the change is as shown in Fig. 2, when the variable DD/D for each n
Indicated by x.

Therefore, when the variable output from register YR is set to X, X is compared with segment values X1 to XO indicating the absolute value of Once G is determined, the gradient value G corresponding to X can be found from the division point.

Based on the above principle, the function f(x
) is stored in the gradient value memory MG, and the read address is specified by a signal indicating the approximate segment point.In order to obtain the approximate segment point, the gradient value G of A circuit such as MX is provided.

In addition, in the DDA, a total of 256 calculation elements are configured in this case, and calculations are performed sequentially according to each predetermined calculation mode, but in this example, 16 out of the total 256 calculation elements are configured. is defined as one that handles variables of a multivariable function, and corresponding to this multivariable function calculation element, each 6-bit 1 is stored in the segmentation point memory MN.
Six addresses AdO to Adl5 are provided, and correspondingly, the interval value memory MX is provided with memories MxO to Mzl5.

Furthermore, in this example, the division points 1 to n in FIG. 2 have a total of 64 intervals, and accordingly, each memory MxO-Mxl5 of the interval value memory MX has 64 addresses AdO-Ad63 of 16 bits each. It is becoming.

That is, in the DDA, the address counter CUA corresponds to the addresses AdO to Ad255 of each memory MC, MM, and MZ.
If the period in which all of the
The calculation is performed in synchronization with the calculation cycle in which the multivariable function operand elements of A are configured.

On the other hand, since the multi-variable function calculation element of the DDA handles each variable x-z individually, the control memory MP stores whether the variable handled at each time is the first variable X, the second variable y, or the third variable. Depending on whether the
corresponds to the number of addresses, each with 256 addresses and 3
A read-only memory divided into areas is used, and each address has a capacity of 8 bits. Among the addresses of each memory MC, MM, and MZ of the DDA, there are predetermined areas that are allocated to calculation elements for multivariable functions. A control signal is stored at the same address in each area as the determined address.

However, in the multivariable function calculation element of the DDA, the one that sends the variable output The orders specified by the counters CUA are far apart, and the address counters C
Since the address designation of the suspension memory MP also changes with the transition of the address designation signal from the UA, each control signal for performing a series of controls is transmitted to each address of the control memory MP according to the transition of the address designation. Stored. Furthermore, in addressing the control memory MP, the same address in each area is simultaneously designated by the lower 8 bits of the address designation signal from the address counter CUA of the DDA, and the upper bits are designated by the 2-bit signal from the variable memory MV. The upper bit specifies the area.

Variable memory MV is each memory MC, MM, MZ of DDA
Similarly, it has the address AdO-Ad255, and the first variable
to the third variable z is stored, and the address counter CUA of the DDA
The same address is specified for each of the memories MC, MM, and MZ of DA at the same time, and information corresponding to the variables to be handled is read out, thereby specifying the area of the control memory MP.

Therefore, by addressing the address counter CUA of the DDA, an arithmetic element for a multivariable function that sends variable output X is configured on the DDA side, and at the same time, the DDFG
On the side, the same address is specified for the control memory MP and the variable memory MV, so that the control memory MP sends the control signal LS, from the area corresponding to the variable to be handled to the variable latch circuit LX, and registers YR. The variable output X from the circuit LX is held by the same circuit LX.

Then, according to the address designation transition of the address counter CUA, the control memory MP transfers the control signal AS to the division point memory M.
MN, thereby specifying the address of the memory MN.

Then, the contents of the designated address are read out and given to the cycle discrimination circuit CD, where +1 is added to the signal indicating the read division point. That is, if the read segmentation point is segmentation point 3 in FIG. 2, the signal at segmentation point 4 is sent out from the cycle discrimination circuit CD, and is applied as an address designation signal to the interval value memory MX. On the other hand, each memory MxO in the interval value memory MX
~Mxl5 corresponds to the calculation element for multivariable functions on the DDA side, and one of them is selectively specified by the address counter CUA, and from the selected one in the memories MxO~Mxl5, according to the division point 4. The interval value X4 of the variable x obtained is sent out as a 16-bit signal.

On the other hand, the output of register YR and the output of variable latch circuit LX are also 16 bits, and if the output of variable latch circuit LX is A and the output of interval value memo 1JMX is B, then the comparison of A-B is is performed in the comparator CPR, and if the variable output X is the interval value X2 and X3 in FIG.
If it is between, A-B becomes negative, and therefore a negative signal is given to the demarcation point control circuit DC.

When receiving a negative signal, the division point control circuit DC adds -1 to the output of the cycle discrimination circuit CD, and sends the signal from the division point 4 to the division point memory MN again as a signal indicating the division point 3.

At this time, as the address designation of the address counter CUA changes, the control memory MP generates the control signal AS again and the write-only control signal WS, so that the signal indicating the division point 3 is read from the division point memory MN. is written to the address where it was performed. That is, in this case, even if the content is updated, the content itself does not change. Next, the cycle discrimination circuit CD adds -1 to the signal indicating the segment point 3 from the segment point memory MN, and sends the signal indicating the segment point 2 to the section value memory MX. Then, since the interval value memory MX sends out a signal indicating the interval value The division point control circuit DC directly sends the output indicating division point 2 of the cycle discrimination circuit CD to the division point memory MN without performing any addition. That is, when the input of the demarcation point control circuit DC is positive or zero,
The output of the cycle discrimination circuit CD is sent out as is. At this time, as the address designation of the address counter CUA changes, the control memory MP further generates a control signal AS and a control signal WS for write control, and in order to give these to the dividing point memory MN, the memory MN is A signal indicating division point 2 is definitively written to the first designated address.

Therefore, when variable output X is between interval values X2 and X3, the contents of segment point memory MN are updated with segment point 2 as the approximate segment point closest to variable output X.

Furthermore, if the cycle discrimination circuit CD repeats the addition of +1 and -1 to the output of the dividing point memory MN, it will discriminate this cycle and stop its operation. A bit is given, and depending on whether the value indicated by this bit is an odd or even number, an operation of first adding 1 and then adding +1 is also performed.

However, in this case as well, the approximate segmentation points are finally stored in the segmentation point memory MN as described above. Note that the division point stored in the division point memory MN and the variable output X are +
If A-B is too far apart to be positive even by adding 1 and -1, the contents of the segment point memory MN will not be a perfect approximate segment point, but the iteration on the DDA side will be repeated. Each time, the contents of the segment point memory MN approach the accurate approximate segment point, and there is always a gap between the interval value corresponding to the approximate segment point and the interval value corresponding to the adjacent segment point on the side where the variable increases. Converges to a state where variable output X exists.

In addition, the cycle discrimination circuit CD may be constructed of an adder/subtractor, a counter, etc., and the division point control circuit DC may be constructed of various gate circuits, adders, etc.

As described above, the approximate segment point for the variable output X is stored in the segment point memory MN, so that if the gradient value memory MG is addressed using this, the gradient value to be determined is read from the memory MG.

However, there are cases where a function of only the first variable x is required, a case where a function of the first and second variables X, y is required, and a case where a function of the first to third variables x-y is required. In the value memory MG, gradient values of functions based on the first and second variables X and y are stored using matrix-like addresses with the first variable X and the second variable y as axes that intersect with each other. Furthermore, in addition to providing a plurality of the above-mentioned matrix-like addresses according to changes in the third variable z, the first to third variables x
The gradient value of the function by -y is stored at each address. Therefore, the read address of the gradient value memory MG must be specified in a multidimensional manner depending on the types of variables forming the functional expression. For this reason, the control memory MP receives the control signal LS2 when handling the first variable x according to the area designation of the variable memory MV after the contents of the division point memory MN are determined in accordance with the transition of the address designation signal from the address counter CUA.
is sent to the first variable latch circuit Lx, when the second variable y is handled, the control signal LS3 is sent to the second variable latch circuit Ly, and when the third variable z is handled, the control signal LS4 is sent to the third variable latch circuit Lz. Approximate division points are held in each of the first to third variable latch circuits Lx-Lz according to the variables, and the operation of obtaining the above approximate division points and the operation of holding them are performed according to the type of variable required. repeat.

This held content is a signal indicating the approximate division point of the variable output X representing the first to third variables xz, and the output of each variable latch circuit Lx-Lz is decoded by the decoder DEC, and When there is only x, it is unidimensional; when the first and second variables are X and y, it is binary; when the first to third variables are x-
When it is z, it becomes a ternary addressing signal and is applied to the same memory MG.

Therefore, the gradient value corresponding to the function of the variable output X is read out from the gradient value memory MG, and the gradient value corresponding to the function of the variable output
Since it is sent to the register YR of the DA, the desired slope value is held in the register YR of the DDA by configuring a multivariable function calculation element for receiving the slope value on the DDA side in synchronization with this point. be done.

Note that when using the first and second variables X, y or the first to third variables x-y for calculation, an interval value is also required, so the interval value is The output of value memory MX is also sent to register Y via the data bus.
It is supposed to be given to R.

In addition, in the control memory MP and the variable memory M, predetermined information is stored in advance as the same address as the address of the calculation element for multivariable functions in each of the memories MC, MM, and MZ on the DDA side. Memory MN
The interval value memory MX and gradient value memory MG include DD.
In accordance with the calculation to be executed on the A side, each division point, each interval value, and each gradient value calculated in advance by another digital computer or the like are stored.

As shown in Figure 2 as an example, the function f(x)
When the value D exhibits a sudden change in some parts, it is only necessary to determine the distribution of division points 1 to n depending on the speed and speed of the change situation.
The same applies to other variables Y and z.

Note that the number of division points and the capacity of each memory can be determined according to the calculation conditions and the configuration of the DDA side. Point memory MN to division point control circuit D
Circuits other than C can be modified in various ways depending on conditions.

As is clear from the above description, according to the present invention, the entire structure is composed of a digital circuit, and the signals handled are DDA.
Since the digital signal is the same as that on the side, interlocking with the DDA becomes reliable and easy, and at the same time, the multivariable function generator can be realized at low cost. The gradient value becomes accurate, which has a great effect on calculations using multivariable functions in DDA.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, and Fig. 2 is a block diagram showing an embodiment of the present invention.
It is a figure which shows the example of the function of a variable. MN: Division point memory, CD: 1 cycle discrimination circuit, MX: Interval value memory, DC:
...Section point control circuit, MG...Gradient value memory, 1 to n...Section point, X, ~XO...
...Interval value.

Claims (1)

[Claims] 1 A segment point memory that stores predetermined segment points of variables, and an interval value that stores the interval value of the variable according to the segment point for each segment point, and whose read address is specified by the output of the segment point memory. a comparator for comparing the output of the interval value memory with the variable output from the digital differential analyzer; and a comparator for comparing the output of the interval value memory with the variable output from the digital differential analyzer; A multivariable function generating device, comprising: a dividing point control circuit for updating, and transmitting a gradient value corresponding to a function of the variable according to the approximate dividing point to the digital differential analyzer.