JPS5931870B2 - Dual-gate short-barrier gate field effect transistor, its manufacturing method, and its driving method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a double-gate short-barrier gate field effect transistor, and a method for manufacturing and driving the same.

In the following description, a short barrier gate field effect transistor will be referred to as a MESFET, and a double gate short barrier gate field effect transistor will be referred to as a double gate MESFET.
SFETl Single-gate short barrier gate field effect transistors are respectively referred to as single-gate MESFETs.
A double-gate MESFET is a semiconductor device having a structure in which, for example, an ohmic source electrode, a first shot gate electrode, a second shot gate electrode, and an ohmic drain electrode are arranged on an n-type semiconductor layer. The first stage portion of the device including the electrode and the second stage portion of the device including the second shot gate electrode and the drain electrode are each semiconductor devices that are considered equivalent to a single gate MESFET. Twin-gate MESFETs are commonly used as cascode amplifiers, as well as modulators, demodulators, and mixers. When this semiconductor device is used as a cascode amplifier capable of low noise gain control, the gain control function is controlled between the first stage part and the second stage part by the DC voltage value applied to the second gate of the second stage part.
This is achieved by simultaneously changing the gain characteristics of the stage sections, and the noise characteristics of the device at this time are mainly determined by the noise characteristics of the first stage section. In recent years, there has been a demand for twin-gate MESFETs that can be used at frequencies in the microwave band, particularly in the telecommunications-related application sector, but they have not been widely used for the following two reasons. The first reason is that when used as the amplifier mentioned above, the noise level of the device is too high than required;1 and the second reason is that in order to be usable in the microwave band, This is because the gate MES-FET must have an extremely fine structure, and it is extremely difficult to economically produce large quantities of twin-gate MESFETs with such a fine structure. As a method to improve the drawback mentioned in the first reason, the characteristics of the double gate MESFET are improved by making the thickness of the n-type semiconductor layer in the first gate part thinner than that in the second gate part. An attempt to improve this is described by Asai et al. in Japan Society of Applied Physics, Vol. 43, p. 442.
yOfApplledPhysics, VOl43, l
974, P. 442. ), manufacturing a twin-gate MESFET with such a complicated structure has the drawback of being accompanied by great difficulties in terms of production technology.

Further, although the gain characteristics of the prototype twin-gate MESFET reported here have been improved, the noise characteristics do not exhibit sufficiently low noise characteristics. Another attempt was made by Zweel et al. to reduce noise by providing an electrode between two gates and attaching a first stage neutralization circuit to this electrode. LEEE Journal, Solid State Circuits, Vol. SC-4, p. 170 (Zieland Takagi, LEEEI, SO
lidState Circuits, VOl. SC-4
．． 1969, p. 170. ), it is difficult to form such a neutralization circuit in the microwave band, and it has not been realized to date.

Furthermore, although the above two attempts are not clearly stated in the above two documents, they have the drawback that low noise characteristics cannot be maintained within the control gain range.

The drawback mentioned in the second reason will be explained in more detail.

A dual-gate MESFET that can be used in the range of 10 GHz to 15 GHz has a fine structure in which the electrode lengths of the first gate and the second gate are both 1 micron or less, and the distance between these two electrodes is 3 microns or less, and the first The distance between the gate electrode and the source electrode must be 1 micron or less and the accuracy must be 0.1 micron or less.

Semiconductor devices with such fine structures are extremely difficult to manufacture using optical contact exposure technology, which is normally used for mass production.1 They are manufactured in small quantities using expensive, top-performance electron beam exposure technology. . Therefore, the object of the present invention is to
First, the twin-gate ME exhibits low noise characteristics in the microwave band.
The purpose of the present invention is to provide a double-gate MESFET, and a second purpose is to provide a manufacturing method for mass-producing such a double-gate MESFET.Thirdly, the purpose is to provide a double-gate MESFET according to the present invention when the gain is controlled over a wide range in the microwave band. An object of the present invention is to provide a method for driving a twin-gate MESFET without losing its low-noise characteristics.

The dual-gate MESFET, which is the premise of the present invention, has a first transistor on the surface of the semiconductor substrate that has shot barrier characteristics with the semiconductor substrate.
two metal film pieces made of a metal of Each metal film piece has a structure in which it is separated by a semiconductor substrate surface or a semiconductor substrate surface covered with a protective film, and two metal film pieces made of a first metal are separated by a semiconductor substrate surface covered with a protective film.
Of the two metal film pieces made of a second metal sandwiching these two gate electrodes, the metal film piece adjacent to the first gate electrode has a source electrode and a second gate electrode. The adjacent metal film piece forms a drain electrode.

Here, the semiconductor substrate refers to an n-type semiconductor layer formed on an insulator or a high-resistance semiconductor crystal. The manufacturing method according to the present invention provides a method for manufacturing the above-mentioned gate MESF-ET.1 The first manufacturing method includes a step of depositing a first metal film having shot barrier properties on the surface of a semiconductor substrate; forming two masks on one metal film at a distance equal to the length of the intermediate metal piece; a part not covered by the mask and a peripheral part following the part under the mask; removing the first metal film and leaving portions of the first metal corresponding to two metal film pieces; depositing a second metal that makes ohmic contact with the semiconductor substrate almost perpendicularly to the sample surface; A second metal film is deposited on the semiconductor substrate surface exposed to the deposited metal, and a first metal film is deposited on the semiconductor substrate.
a process of forming three second metal film pieces by cutting the parts and intervals corresponding to two metal film pieces of the metal, corresponding to the two metal film pieces of the first metal film on the semiconductor surface; The method includes a step of removing the first metal film except for two parts: a portion and a terminal portion for applying an external voltage to each film piece.

The second manufacturing method uses a three-layered first mask as the above-mentioned mask, in which the first layer of material on the semiconductor substrate surface serves to protect the semiconductor substrate surface, and the second layer of material serves to protect the semiconductor substrate surface. , the material of the third layer and the second mask material have properties that are not attacked by the etchant, and the material of the second layer provided on the first layer has the property of not being attacked by the etchant of the third layer. The material of the third layer provided on the second layer has a property that it is not damaged by the corrosive liquid of the second layer.

This second manufacturing method includes a step of forming a three-layer first mask having the same shape as the mask used in the first manufacturing method on the semiconductor substrate surface, and corroding and removing the periphery of the second layer of the first mask. In the process, a second metal that makes ohmic contact with the semiconductor substrate is deposited almost perpendicularly to the sample surface, and three second metal film pieces are deposited on the third layer of the first mask and on the exposed semiconductor substrate surface. The step of forming a second layer on top of the third layer by removing the third layer
Step of removing the metal film pieces, removing the second layer film pieces except for the parts sandwiched by the second metal film pieces and the voltage application terminal parts to the first gate and the second gate. Process, 1st
A step of depositing a second mask material, which is not affected by the etchant of the layer material and the second layer material, on the sample surface in a direction substantially perpendicular to the sample surface;
removing the second mask film on the layer to expose the portion of the first layer that was under the film piece of the second layer;
removing the layer using a second mask to expose this portion of the semiconductor substrate; removing a first metal from the sample surface that has a shot barrier property with the semiconductor substrate and is not eroded by the etchant of the second mask material; forming a first metal film deposited on the exposed semiconductor substrate surface and a second mask from a direction substantially perpendicular to the second mask;
The first metal film on the second mask is removed at the same time as the first mask is removed. A first example of manufacturing a double-gate MESFET having a structure that is the premise of the present invention by the first manufacturing method will be shown with reference to FIG. Figure 1a
is a 70μ long film formed on the high resistance GaAs crystal 11.
m1 thickness 0.2μm electron density 2X1017c7rL-3
n-type GaAs layer 12 on the crystal surface with n-type GaAs layer 12 of
As the first metal film 13 exhibiting shot barrier properties, aluminum is deposited, for example, with a thickness of 0.6 μm, and photoresist films 15 to 18 with a thickness of 0.8 μm are formed thereon. The photoresistor films 16 and 17 have a length of 3 μm and are spaced apart from each other by 2 μm. In FIG. 1b, a portion of the first metal film not covered by the masks 15 to 18 and a peripheral portion under the mask adjacent to this portion are removed, and a first metal film piece 19, each having a length of 1 μm, is removed. Leave 20.

If aluminum is used as the first metal, removal is performed with phosphoric acid at 50° C. for 3 minutes.

It is easy to accurately control this chemical corrosion process, and long, thin membrane pieces 19 and 20 are formed in a uniform shape without breakage. For example, aluminum stripes 1 μm thick, 0.5 μm wide (corresponding to the gate length), and 300 μm long can be formed using a 2 μm wide mask by the chemical etching method described above. It was possible. The first method for removing the metal film is to remove the part not covered by the mask by ion milling or sputter milling, and then remove the peripheral part by chemical etching. is also valid.

In FIG. 1c, a metal that makes ohmic contact with the n-type GaAs layer 12, such as a gold-germanium alloy, is deposited almost perpendicularly to the crystal surface by vapor deposition or sputtering to a thickness of 0. .1 μm second metal film piece 2
1 to 27 are formed.

A narrow gap separates the first metal film piece and the second metal film piece adjacent to each other on the GaAs crystal surface. Figure 1d
Now, by removing the masks 15 to 18 with an organic solvent such as acetone, the second metal film pieces 21 and 2 on the masks are removed.
After removing 3, 25, and 27, 450
The selected n-type GaAs layer 12 is formed by heat treatment at ℃ for 30 seconds.
and second metal layers 22, 24, 26 are alloyed to form an ohmic contact electrode. In FIG. 1e, the first metal film on the high-resistance GaAs crystal surface is
Fourth metal film piece 19 corresponding to the gate and second gate
, 20, and then a gold film 28, 2 is placed on the second metal film piece 22, 26.
9 to 1 to 2μ by vapor deposition or plating method.
This figure shows the formation of a source electrode and a drain electrode which are formed to a thickness of m and can be easily bonded.

FIG. 2 shows a plan view of a double-gate MESFET manufactured by an embodiment of the first manufacturing method.

12a indicated by a dotted rectangle indicates the outer periphery of the n-type GaAs layer. 19a and 20a are a first gate 19} and a second gate made of the first metal left in the step of FIG. 1e, respectively.
This is a bonding pad to gate 20.

The length of the n-type GaAs layer in the vertical direction is usually 100 to 300
It is μm.

In the above-described embodiment, the masks 15 to 18 were photoresist films, but the mask material may also be metals such as fnium, molybdenum, and chromium.

When such a metal film is used as a mask, the masks 16 and 17 and the second metal coatings 23 and 25 thereon do not need to be removed. In the above embodiment in which GaAs is used as the n-type semiconductor crystal, the first
An example using aluminum as the metal material was shown;
It is also possible to use other materials such as platinum, chromium, molybdenum, titanium, gold, silver, or composite films thereof.

As the ohmic metal material, in addition to gold-germanium alloy, gold-germanium-nickel alloy, nickel-germanium alloy, etc. are also possible. Furthermore, semiconductor crystals include silicon, indium arsenic, indium
Mixed crystals of gallium, indium, arsenic, etc. can also be used.

In the first embodiment, the distance between adjacent metal pieces was 1 μm, but as this distance increases, the direct current loss in this portion adversely affects the microphone mouth wave characteristics of the double-gut MESFET. Therefore, it is desirable that this distance be approximately 2 μm or less.

Referring to FIG. 3, a second method for manufacturing a double-gate MESFET having the structure that is the premise of the present invention by the second manufacturing method will be described.
An example is shown below.

FIG. 3a shows a structure formed on a high-resistance GaAs crystal 11 with a length of 70 μm, a thickness of 0.2 μm, and an electron density of 2×10−17.
? -3 on the GaAs crystal surface with n-type GaAsl2,
The first layer, which has a property that is not affected by the material of the second and third layers and the corrosive liquid of the second mask material, and plays the role of surface protection.
A layer 31, for example a 0.2 .mu.m thick silicon oxide film applied by chemical vapor deposition or sputtering, is deposited on top of which a second layer of the material of the third layer is not exposed to the etchant. A film 41, for example, an aluminum film with a thickness of 0.6 μm deposited by a vapor deposition method or a sputtering method, is formed, and film pieces 55 to 58 made of a third layer material, for example, photoresist film pieces are formed thereon. Show the place.

The photoresist film pieces 56 and 57 have a length of 3 μm and are spaced apart from each other by 2 μm}D, and are easily formed by a normal optical contact exposure method. In Figure 3b, the second layer and the first
The portions of the layer not covered by the photoresist film strips are shown removed.

This removal is preferably carried out by ion milling or sputter milling using a photoresist film piece as a mask, but after removing the second layer of aluminum film with phosphoric acid, the first layer of silicon oxide may be removed by ion milling or sputter milling. In this way, a three-layered first mask structure is formed. FIG. 3c shows the second layer portion of the first mask narrowed by laterally chemically etching the exposed second layer portion by 1.0 μm. When aluminum is used as the second layer material,
A phosphoric acid solution at 50°C is suitable. At this time, the silicon oxide that is the first layer material and the photoresist that is the third layer material are not corroded. Second layer film 4 below third layer films 56 and 57
The length of 6,47 is easily controlled to exactly 10 μm. In Figure 3d, an n-type G
A second metal film piece 2 is deposited with a second metal, such as a gold-germanium alloy, making ohmic contact with the aAs layer 12.
1 to 27 are formed.

In FIG. 3e, the third layer film pieces 55 to 58 and the second metal film pieces 21, 23, 25, 27 deposited thereon are removed using a third layer film remover such as acetone. Remove L/.
three second metal film pieces 22 deposited on the GaAs crystal;
Leave 24 and 26.

Furthermore, the second metal film piece and GaAs are alloyed by heat treatment at 450°C for 30 seconds in a hydrogen atmosphere. This figure shows the unnecessary portion of the second layer film removed.

FIG. 3g shows a sample having the shape shown in FIG. Shows where it has been applied.

A chromium film with a thickness of 0.4 μm is suitable as the second mask film. FIG. 3h shows that the second layer film pieces 46, 47 and the second master film deposited thereon are removed by the corrosion of the second layer material.
It is shown after being removed with a corrosive solution, such as phosphoric acid.
At this time, portions of the protective film pieces 36 and 37 each having a length of 1 μm that are not covered by the second mask 59 are exposed. In FIG. 3 1, the protective film piece 36
, 37 is removed with an etchant for the first protective film, such as hydrofluoric acid, to form n-type GaAs.
The corresponding portion of the layer 12 is exposed, and the n-type GaAs layer 12 is
The first gold layer, for example, an aluminum film with a thickness of 0.4 μm, which exhibits the barrier properties, is deposited from a substantially vertical direction. 2 deposited on the n-type GaAs layer
The two first metal film pieces 19 and 20 are connected to the second metal film piece 22.
, 24, and 26 on the same n-type GaAs layer, and are separated by protective film pieces 36a, 36b, 37a, and 37b. In FIG. 3j, the second mask 59 is immersed in its etchant,
At the same time, the first metal film on the second mask is removed, for example by removal with hydrochloric acid Mm - exposing the three second metal strips 22, 24, 26.

In this way, the first gate electrode 19, the second gate electrode 20, the source electrode 22, and the intermediate metal film piece 2 each having a length of 1 μm are formed.
4. Drain electrode 26 is formed. In order to facilitate the bonding of the source electrode and the drain electrode,
In FIG. 1, gold films 28 and 29 with a thickness of 1 μm are used as the source electrode 22 and the drain electrode, respectively. It is formed on the in-electrode 26 by a vapor deposition method or a plating method.

In the second embodiment, silicon oxide was used as the first protective film, but a high-resistance GaAs film or a high-resistance G
An aAlAs mixed crystal film can also be used as a protective film.

At this time, the high resistance GaAs film or GaAlAs mixed crystal film is formed by chemical vapor deposition, liquid phase epitaxial growth, or vapor deposition. When these high-resistance semiconductor films are used, the density of surface states on the surface of the n-type GaAs layer is significantly reduced, so the surface stability is superior to that when silicon oxide is used. Further, in this case, a mixed solution of sulfuric acid, hydrogen peroxide, and water is convenient as the etchant for the high-resistance semiconductor film. Aluminum oxide or silicon nitride may be used as other protective film materials. In this case, hot phosphoric acid is suitable as the protective film etchant. 1st
Aluminum is used as the shot contact metal in the second embodiment. In addition, platinum, chromium, molybdenum, titanium, gold, and composite films thereof may be used as the first metal film.

Furthermore, although GaAs is used as the semiconductor material in the second embodiment, other semiconductor materials such as silicon,
It is also possible to use indium/arsenic, gallium, indium/arsenic mixed crystals, etc.

In the two manufacturing methods described above, the minimum line width of the formed mask was 2 μm, and all of them were formed by optical exposure. The gate length of the manufactured double-gate ME-SFET was 1 μm for both the first gate and the second gate, and the 1 source electrode and the first gate were located exactly 1 μm apart.
Moreover, it is formed without any alignment work. on the other hand,
With conventional manufacturing methods, in order to set such fine electrodes of 1 μm in a predetermined position with an accuracy of ±0.1 μm,
This was only possible in small quantities with the highest performance electron beam exposure technology.

The manufacturing method according to the present invention has an outstanding effect that even a double-gate MESFET having a gate length of 0.5 μm or less can be manufactured in mass production. Further, the manufacturing method of the present invention provides a double gate ME having a structure having an intermediate metal film piece.
Although applicable only to SFETs, this intermediate metal piece is
As will be described later, the characteristics of the twin-gate MESFET are significantly improved compared to the conventional ones, and a new drive method is also possible. The electrical characteristics of the dual-gate MESFET manufactured by the first manufacturing method of the present invention will be described in comparison with the characteristics of a conventional dual-gate MESFET.

Here, the conventional twin-gate MESFET refers to the twin-gate MESFET of the first embodiment, except that there is no intermediate metal piece.
This means a twin-gate MESFET manufactured by electron beam exposure with the same dimensions and structure as . An input signal is applied to the first gate via a bias circuit and a tuner, and an output signal is output from the drain electrode via the tuner and bias circuit. Measurements were performed in the frequency band from 4 GHz to 16 GHz, the input tuner was adjusted to obtain the minimum noise figure at each frequency, and the output tuner was adjusted to maximize the output gain. The DC applied voltages are a drain voltage of 4V and a first gate voltage of -1.5V, and the first source electrode and the second gate electrode are grounded both in terms of DC and microwave. The drain current at this time is
It is 10mA. These conditions correspond to bias conditions that minimize the noise level. Further, the intermediate metal film piece of the double-gate MESFET according to the present invention is not connected to other electrodes or the outside in terms of direct current or microwave, but is in a floating state. Fig. 4 is a diagram showing the measured noise figure and power gain. These and ClC' respectively show the characteristics of a single gate MESFET with a gate length of 1 μm, which is shown for comparison.

The single gate MESFET is biased with a drain voltage of 4V1 and a drain current of 10mA. Note that D' is a characteristic when using the 1-drive method described later. From this Figure 4, it can be seen that the power gain of the conventional twin-gate MESFET is
It can be seen that it is 3 to 4 dB larger than that of ESFET.

However, its noise characteristics are about 1 compared to that of a single gate.
At the same time, you can see that it is getting worse by dB. On the other hand, the twin-gate MESFET manufactured by the manufacturing method of the present invention maintains a slightly larger power gain than the conventional twin-gate MESFET, while exhibiting a noise figure approximately equal to that of the single-gate MESFET.

That is, the twin-gate MES-FE manufactured by the manufacturing method of the present invention
The advantage of T is that it achieves significantly lower noise than conventional twin-gate MESFETs while achieving a much larger output power gain value than single-gate MESFETs. Below, a twin-gate MESFET according to the present invention will be described.
We will briefly explain why this shows such low noise characteristics.

It is well known that the noise characteristics of a twin-gate MESFET are defined by the noise characteristics of its first stage portion.

It has been found that, in the case of a semiconductor substrate such as GaAs, this noise is mainly generated from the region of the n-type GaAs layer where a high electric field of 3 KV current or more is present. In a dual-gate MES-FET with a conventional structure, electrons passing through the channel formed in the n-type GaAs layer narrowed by the depletion layer under the first gate are not sufficiently decelerated. It flows into the channel two gates below. In other words, since the first stage part and the second stage part are correlated with each other, the high electric field region of 3K or more in the first stage part is the second stage part.
It extends in the direction of the gate electrode. For this reason, compared to a normal single-gate MESF-ET, the double-gate MESFET with the conventional structure has a longer high electric field region and has a higher D1 noise level. On the other hand, in the twin-gate MES-FET manufactured by the manufacturing method of the present invention, most of the electrons that have passed through the first stage flow into the intermediate metal piece, where they are rapidly decelerated and the magnitude of the electric field becomes almost zero. .

Therefore, in the multi-gate MESFET according to the present invention, the length of the high electric field region is approximately the same as that of the single-gate MESFET, and a low noise characteristic comparable to that of the b1 single-gate MESFET has been achieved. The length of the intermediate metal piece of the double-gate MESFET structure used in the present invention must be long enough for a considerable portion of the electrons to flow into the intermediate metal piece.
This length corresponds to about twice or more the thickness of the n-type semiconductor layer. The low noise characteristics described above were obtained when the intermediate metal piece of the dual-gate MESFET according to the present invention was used in a floating manner, but by applying a negative DC bias to the second gate electrode to reduce the power gain. However, there still remains the drawback that the noise figure becomes somewhat large.

FIG. 5 shows the dependence of the noise figure and power gain on the second gate voltage Vg2 at 4 GHz.

Each symbol in the figure is the same as that in FIG. The twin-gate MESFET (AjA●) according to the present invention is different from the conventional one (B
, B'), the increase in the noise figure due to gain reduction is smaller, but the noise figure still increases by 3 dB while the gain decreases by 7 dB. Suppressing this rise in noise figure is essential in order to use the double gate MESFET for the purpose of automatic gain control. In the twin-gate MESFET used in the present invention, by utilizing the newly introduced intermediate metal piece 24, five driving methods are possible for suppressing the above noise increase.

FIGS. 5D and 5D' show noise characteristics and gain characteristics when gain control is performed using the driving method described below.

As clearly seen from the figure, the gain value is nearly twice that of A and A', and at the same time, the noise figure hardly increases even if gain control is performed. For example, even though the gain is reduced by 7 dB, the noise figure is kept within 0.5 dB. Therefore, the twin-gate MESF-
It is clear that when ETs are used in accordance with the novel driving method of the present invention, twin gate MESFETs can be used satisfactorily for low noise automatic gain control, which was even difficult to use in the past.

These five driving methods will be explained in detail below. FIG. 6 is a circuit diagram showing this first driving method according to the present invention, and inside the dotted line 60 is a double gate MESFE used in the present invention.
Indicates T.

An input signal is applied to the first gate electrode 19 via the capacitor 61. A DC voltage Vg is applied to the first gate electrode via an inductance 63. A DC voltage G2 for gain control is applied to the second gate electrode 20 to which a matching circuit 67 is connected via an inductance 64.
The output signal is connected to the DC voltage Vd via the inductance 65.
is taken out via the capacitor 62 from the drain electrode 26 to which is applied. In this one driving method according to the present invention,
Furthermore, it is characteristic that a constant DC voltage Vm is applied via an inductance 66 to the intermediate metal piece 24 to which the matching circuit 68 is attached. As a result, the first stage portion and the second stage portion have a feature that they are completely independent in terms of direct current. The characteristics shown by D and D' in FIG. 5 are the characteristics when the intermediate voltage Vm is 1.5 and the applied L first gate voltage - 15V and the drain voltage 4.0V.

The characteristics of this driving method shown in FIG. 5, such as low noise, high gain, and sufficient gain control, are that the intermediate voltage V
This is caused by the fact that the first stage portion and the second stage portion become independent in terms of direct current due to the introduction of m, which will be explained below. FIG. 7 shows the relationship between the drain voltage Vd and drain current Ld of the circuit shown in FIG.
．． 2V. This is an example of what happens when 3V is removed. As can be seen from FIG. 7, the current-voltage characteristic of the second stage portion depends only on the voltage Vd-Vm between the drain electrode and the intermediate metal film piece and the second gate voltage Vg2, and depends on the first gate voltage g1. does not depend on it at all. Conversely, the current-voltage characteristics of the first stage portion depend only on the voltage Vm between the intermediate metal film piece and the source electrode and the first gate voltage Vgl, and the second gate voltage Vg2
does not depend on it at all. In this manner, by applying a constant DC voltage to the intermediate metal film piece, the first stage portion and the second stage portion became completely independent in terms of DC current. Therefore, in this driving method,
Regardless of the value of the second gate voltage Vg2, the first
The stage portion can be DC biased in a state exhibiting low noise characteristics, and gain control using the second gate voltage Vg2 can be performed only in the second stage portion. For this reason, Figure 5D
As shown in Figure 2, the low-noise characteristics are not lost even when the gain is reduced, which is an unprecedented and outstanding effect. On the other hand, in the conventional double-gate MESFET drive method, the intermediate electrode film piece 24 is not present, and therefore no DC voltage is applied, and the first stage portion and the second stage portion are connected to each other in a direct current manner. It was not independent.

For this reason, when the second gate voltage Vg2 was made negative, the first stage part entered the operation region of the triode, and the noise level in the first stage part became significantly large. Generally, it is well known that the noise figure of a multistage amplifier is mainly determined by the first stage. In this conventional driving method, when the second gate voltage Vg2 is changed for gain control, the noise level in the first stage inevitably increases, resulting in an increase in the noise figure of the output section. Shimatsuta. Because of this drawback, twin-gate MESFETs have not traditionally been widely used in amplifiers with automatic gain control. On the other hand, if the twin-gate MESF-ET used in the present invention is driven by V)1 according to the method according to the present invention, a microwave amplifier with a low-noise automatic gain control function can be easily manufactured. Become. FIG. 8 shows a plan view of a double-gate MESFET used in the above driving method.

In the figure, 24a is a bonding pad of the intermediate metal film piece 24. The double-gate MESFET shown in FIG. 8 is manufactured using a photoresist in which the bonding pad is exposed on the intermediate metal piece in the manufacturing process shown in the embodiment of the first or second manufacturing method according to the present invention. If membranes are used, they can be manufactured in large quantities using the same manufacturing process. The length of the intermediate metal film piece 24 in the channel direction is the first
In order to suppress the phase shift of the signal between the step portion and the second step portion, the thickness is preferably 100 μm or less. For the twin-gate MESFET used in FIG. 8, this length was chosen to be 30 μm. In the above-mentioned driving method, a DC current is passed through the intermediate metal film piece through the bonding pad 24a, so in order to suppress the DC loss, a 1 μm thick layer is placed on the intermediate metal film piece 24 and the bonding pad 24a. It is effective to apply a gold film with a thickness of ~2 μm by vapor deposition or plating. This gold film may be deposited at the same time as the gold film is deposited on the source electrode 22 and drain electrode 26 in the step of the first or second manufacturing method. The twin-gate MESFES according to the invention can also be used as a low-noise, high-gain amplifier without gain control.

For this purpose, it is necessary to apply a suitable voltage to the third gate electrode. In order to obtain a sufficiently large gain, it is necessary to apply a voltage to the second gate electrode so that the potential is equal to that of the intermediate electrode, but if this voltage is too high, a forward current will flow to the second gate electrode. Please be careful as there is a risk that the flow may flow in and destroy the element. FIG. 9 is a circuit diagram showing a second driving method using a double-gate MESFET according to the present invention, in which the second gate electrode 20 is connected to the intermediate electrode 2.
4 is connected by a circuit element 69 that blocks the microwave signal but has a sufficiently small resistance in terms of direct current, and connects to the ground line, and hence the source electrode 22, by a circuit element 69 that allows the microwave signal to pass but does not pass direct current. They are characterized in that they are connected by a circuit element 70 that does not pass through.

In this circuit, the second gate electrode 20 is automatically connected to the intermediate electrode 2.
It is assumed that the potential is equal to 4. The circuit element in the diagram is a twin-gate MES.
It can be formed on the same semiconductor substrate as the FET, and the first and second gate electrodes and the intermediate electrode do not need to be connected outside the device. The above-mentioned circuit elements 69 and 70 may be passive elements or active elements as long as they can fulfill the above-mentioned functions.
Alternatively, a combination of both may be used. FIG. 10 is a plan view of the above-described semiconductor device.

The length of the intermediate metal piece 24 is suitably between 0.5 μm and 30 μm. It is appropriate that the circuit element 69 has an inductance of 10 mH or more, and the circuit element 70 has a capacitance of 20 pF or more. First and second gate electrodes 1
A multi-gate ME-SFET having the structure shown in FIG. 10, in which the lengths of 9, 20 and the intermediate metal piece 24 are all 1 μm and the width is 300 μm, has a minimum noise figure of 3.0 at 10 GHz.
The maximum available power gain in dB1 was 16.2 dB.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross section of an embodiment according to a first manufacturing method of a double-gate MESFET of the present invention according to each step. FIG. 2 is a plan view of a double-gate MESFET manufactured by the first manufacturing method. FIG. 3 is a diagram illustrating a cross-section of an embodiment of the second manufacturing method of a double-gate MESFET of the present invention according to each step. FIG. 4 shows the frequency dependence of the noise figure and power gain of various twin-gate MESFETs, and FIG. 5 shows the second gate voltage dependence, respectively. In FIGS. 4 and 5, A and A' represent the noise characteristics 7 and gain characteristics when the twin-gate MESF-ET according to the present invention is driven with the intermediate metal film floating and the input and output matched. , and B and B' are conventional twin-gate MES
LC and C' are the noise characteristics and gain characteristics when the FET is driven with input and output matching.
LD, D' exhibiting similar characteristics of T, the first one according to the present invention
The noise characteristics and gain characteristics when using one driving method are shown respectively. FIG. 6 is a circuit diagram showing the first driving method of the present invention, FIG. 7 is a diagram showing the relationship between drain current and drain voltage, and FIG. 8 is a circuit diagram showing the first driving method of the present invention. FIG. 3 is a plan view showing the structure of a twin-gate MESFET used in the method. FIG. 9 is a circuit diagram showing a second driving method according to the present invention. FIG. 10 is a circuit diagram showing a circuit diagram of a second driving method according to the invention. FIG. 2 is a plan view of a gate MESFET. In the figure, 11 is a high-resistance GaAs crystal, 12 is an n-type GaAs layer, and 13 is an n-type GaAs layer.
type GaAs layer and shot barrier.The first metal film exhibiting two characteristics, 15. 16, 17, 18 are photoresist films, 1
9 is a first gate electrode, 20 is a second gate electrode, 21, 2
2, 23, 24, 25, 26, and 27 are second metal films that make ohmic contact with the n-type GaAs layer, 22 is a source electrode, 24 is an intermediate metal film piece, and 26 is a drain electrode.
8 and 29 are gold films deposited on the source and drain electrodes, respectively. Further, 12a is the outer periphery of the n-type GaAs layer, 119a is a bonding pad for the first gate electrode 19, 20a is a bonding pad for the second gate electrode 20, and 24a is a bonding pad for the intermediate metal film piece 24. 31 is a protective film corresponding to the first layer of the first mask having a three-layer structure, 41 is also a second layer film, 55, 56, 57, and 58 are photoresist film pieces corresponding to the third layer 136, 37 is a protective film piece, 46 and 47 are second layer film pieces, 59 is a second mask gourd, and 36a, 36b, 37a, and 37b are protective film pieces that cover the n-type GaAs layer.

Claims (1)

[Claims] 1 source electrode, first Schottky barrier gate electrode, second
A Schottky barrier gate electrode and a drain electrode are sequentially arranged on a flat surface of a semiconductor substrate, and these two gate electrodes are arranged in a region sandwiched between the first Schottky barrier gate electrode and the second Schottky barrier gate electrode. An intermediate metal film piece is provided in ohmic contact with an independent semiconductor substrate, and a first circuit having a function of allowing direct current to pass through but blocking alternating current is provided between the intermediate metal film piece and the second Schottky barrier gate. A second circuit is integrally provided on the semiconductor substrate so as to connect with the electrode, and has a function of allowing alternating current to pass through but blocking direct current. A double-gate Schottky barrier gate field effect transistor characterized by being integrated on a substrate. 2. A first metal film is formed on a semiconductor substrate with a flat surface, and three predetermined parts on the first metal film, namely, a part corresponding to the formation of a source electrode installed in parallel, and an intermediate part are formed on the first metal film. a step of installing a mask film in a portion excluding a portion corresponding to the formation of the metal film piece and a portion corresponding to the formation of the drain electrode;
By removing the first metal film of the three parts and the adjacent peripheral parts of the first metal film covered by the mask following these parts, the area between the semiconductor surfaces corresponding to the adjacent peripheral parts is removed. leaving two pieces of the first metal film on the mask, and depositing the second metal on the flat surface from a direction substantially perpendicular to the mask, leaving two pieces of the first metal film exposed on the mask and on the second metal film. forming a second metal film piece on the semiconductor surface portion and separated from the first metal film piece by the adjacent peripheral portion; A source electrode and a drain electrode sandwiching one metal film piece, and an intermediate metal film piece sandwiched between two first metal film pieces, between each adjacent first metal film piece. A method for manufacturing a double-gate Schottky barrier gate field effect transistor, comprising the steps of: arranging the adjacent peripheral portions with a gap corresponding to the length of the surface of the semiconductor substrate. 3. A first metal film is formed on a semiconductor substrate having a flat surface, and three predetermined parts on the first metal film are formed, namely, a part corresponding to the formation of a source electrode installed in parallel, and a middle part. a step of installing a mask film in a portion excluding a portion corresponding to the formation of the metal film piece and a portion corresponding to the formation of the drain electrode;
By removing the first metal film of the three parts and the adjacent peripheral parts of the first metal film covered by the mask following these parts, the area between the semiconductor surfaces corresponding to the adjacent peripheral parts is removed. leaving two pieces of the first metal film on the mask, and depositing the second metal on the flat surface from a substantially perpendicular direction, leaving two pieces of the first metal film on the mask and on the three pieces exposed to the second metal film. forming a second metal film piece on the flat surface portion and separated from the first metal film piece by the adjacent peripheral portion; A source electrode and a drain electrode are sandwiched between two first metal film pieces, and an intermediate metal film piece sandwiched between two first metal film pieces is connected to an adjacent first metal film piece. A step of installing a mask film piece and a second metal plastic piece on the mask film piece after depositing the second metal with a gap corresponding to the length of the surface of the semiconductor substrate in the adjacent peripheral portion between them. 1. A method for manufacturing a double-gate Schottky barrier gate field-effect transistor, comprising the step of removing . 4. On a semiconductor substrate with a flat surface, excluding three predetermined parts, that is, the part corresponding to the formation of the source electrode, the part corresponding to the formation of the intermediate metal piece, and the part corresponding to the formation of the drain electrode, which are installed in parallel. The first mask order of the three-layer structure is the first layer material in contact with the semiconductor surface and the second layer material in contact with the semiconductor surface.
The third layer, the third layer, and the second mask material are made of materials that are not affected by the etchant and have the property of protecting the semiconductor surface. A step of selecting and forming a material that is not affected by the corrosive liquid of the second layer as the material of the second layer by using a material that is not affected by the corrosive liquid of the third layer as the material of the third layer; a step of etching away only the peripheral portion of the second layer of the mask to obtain a first mask having a structure having a second layer having dimensions shorter than the first and third layers;
by depositing a metal on a flat surface from a direction substantially perpendicular to the flat surface, and forming a second metal film piece on the third layer of the first mask and on the three exposed parts of the semiconductor surface, forming a source electrode, an intermediate metal film piece, and a drain electrode, each separated by a first layer of a first mask, on a semiconductor surface; a third layer of the first mask; second
A second mask material that is not corroded by the first layer and second layer etchant is applied in a direction substantially perpendicular to the flat surface, and a second mask material is formed. and removing the second layer of the first mask and the second mask film thereon, and removing the second layer of the first mask and the second mask film thereon, and removing the second layer of the first mask that is between the three metal pieces of the second mask and not covered by the second mask. a step of exposing the first layer of the portion; and removing only the exposed first layer using a second mask to expose the semiconductor substrate of this portion;
A first metal that is not affected by the corrosive liquid of the second mask material and that forms a Schottky barrier with the semiconductor substrate is deposited from a direction substantially perpendicular to the sample surface, and a second metal is deposited on the second mask and the second metal. forming a first metal film piece on two exposed parts of the semiconductor surface sandwiched by the metal film pieces; and removing a second mask and the first metal film piece thereon. , a first gate electrode made of a first metal is placed on the surface of the semiconductor substrate between the source electrode and the intermediate metal film piece, with the semiconductor surface region covered with the first layer protective film piece separated; A first layer is formed on the surface of the semiconductor substrate between the piece and the drain electrode.
leaving a second gate electrode of a first metal across the semiconductor surface region covered with a piece of protective film of a layer. . 5. A method for manufacturing a double-gate Schottky barrier gate field-effect transistor according to claim 4, characterized in that a high-resistance semiconductor film is used as the first layer material. 6. The intermediate electrode is connected to a direct current source via an inductance and driven, and is installed between the first Schottky barrier gate electrode and the second Schottky barrier gate electrode and makes ohmic contact with the semiconductor substrate. A method for driving a dual-gate Schottky barrier-gate field effect transistor with an intermediate electrode. 7 automatic biasing of the second Schottky barrier gate electrode by connecting the intermediate electrode and the second Schottky barrier gate electrode through a first circuit that passes direct current and has an alternating current blocking function; A first Schottky barrier gate electrode and a second Schottky barrier gate electrode are connected to the source electrode via a second circuit that passes alternating current and has a direct current blocking function.
A method for driving a double-gate Schottky barrier gate field effect transistor comprising an intermediate electrode disposed between a Schottky barrier gate electrode and in ohmic contact with a semiconductor substrate.