JPS5931866B2 - Method for manufacturing Schottky barrier semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention &L relates to a method of manufacturing a Schottky barrier semiconductor device which has a small reverse leakage current and is easy to manufacture.

Schottky barrier diodes (hereinafter referred to as S, B, and D) generally have a surface protective film 2 made of silicon oxide or the like on the upper main surface of a semiconductor substrate 1, and an opening in this surface protective film 2, as shown in FIG. A Schottky barrier is formed by bonding a barrier metal 3 to a low concentration semiconductor region 12 of a semiconductor substrate 1.

Note that the semiconductor substrate 1 is usually an epitaxial substrate having a semiconductor region 12 with a low concentration on a semiconductor region 11 with a high concentration. However, in this structure, the first
Since the electric field tends to concentrate in the peripheral part A of the junction between the barrier metal 3 and the semiconductor region 12 in the figure, the reverse leakage current is large, making it difficult to manufacture S, B, and D with ideal breakdown voltages. It was hot. Therefore, various methods have been recently proposed to reduce the reverse leakage current.

For example, as shown in Fig. 2a, a p+ guard ring 4 is provided at a location corresponding to the peripheral edge portion A in Fig. 1, or a means of deforming the planar structure itself, for example, the most practical method is shown in Fig. 2b. As shown, the semiconductor substrate 1 is
A method has been developed in which the electrode is etched to a depth of .mu.m or more to create a curved portion at the peripheral edge of the electrode. The guard ring structure shown in FIG. 2a certainly improves the reverse breakdown voltage, but on the other hand, a p+n junction is formed between the p+ guard ring 4 and the n-type semiconductor, which causes minority carrier People get angry and make the high frequency characteristics worse.

In addition, because the guard ring structure requires the thickness of the silicon to be thickened by the depth of the guard ring, and because the impurity concentration distribution changes due to heat treatment such as diffusion, the forward voltage This has the disadvantage that not only the drop becomes large, but also the design of the element becomes difficult. Furthermore, since the number of diffusion steps is increased, the manufacturing process becomes more complicated and the cost becomes higher. In addition, the method of deeply etching the semiconductor surface shown in Figure 2b weakens the electric field concentration around the electrode,
It has been theoretically and experimentally confirmed that the reverse leakage current can be reduced and the reverse breakdown voltage can be improved to near the theoretical value using a planar type element using a pn junction, and it has become a well-known fact.

However, in this structure, only the semiconductor substrate is selectively chemically etched during the manufacturing process, so even if the barrier metal is formed, the eaves 5 of the surface protection film remain as shown in FIG. 2b, and the board 6 is not formed. Because of its ease of use, the current situation is that it is actually only possible to obtain a reverse breakdown voltage comparable to that of the conventional planar type. It has been found that the reason for this is that the barrier metal does not adhere to the semiconductor region 12 directly under the eaves portion 5 of the surface protection film in the board 6 portion. Therefore, we first developed an S. B.
I suggested D.

(Japanese Patent Application No. 50-130269) A feature of this structure is that the barrier metal is formed by a plating method. The one shown in FIG. 2C is the S. B.
It is a sectional view of D. This product is easy to manufacture and has extremely high performance, ie, a small reverse leakage current. B. Provide D. However, depending on the manufactured rod, the reverse leakage current may be large and the expected breakdown voltage may not be obtained. As a result of investigating the cause, it was found that the leakage current was generated from the interface B between the semiconductor region 12, the surface protection film 2, and the barrier metal 3. This interface B is a location where impurities and certain kinds of charges are likely to accumulate, and where mechanical stress such as distortion is likely to occur, depending on the method of forming the surface mixing film 2. In this invention, a barrier metal is attached to such an interface B by a plating method. S. has no structure.
B. This paper proposes a manufacturing method for D, which eliminates the above-mentioned drawbacks.

An explanation of one embodiment of the SBD manufactured according to the present invention is given in the third section.
Do this using diagrams.

In the figure, 1 to 3 are the same as those shown in FIGS. 1 and 2, 7 is an electrode formed on the barrier metal 3, 8 is an ohmic electrode provided on the lower main surface of the semiconductor substrate 1, and 21 is an opening in the surface protective film. Here, as the semiconductor substrate 1,
On top of the n+-n conventional structure, an n-layer semiconductor region 13 is added.
The one grown epitaxially is used. Here, the carrier concentration is in the relationship Nn+ (n+ semiconductor region 11)>Nn (n layer semiconductor region 12)>>Nn- (n- semiconductor region 13). The surface of the semiconductor region 13 of this structure is covered with a surface protective film 2 made of silicon oxide or the like, and an opening 21 for forming a barrier metal is opened using a normal photolithography technique. Furthermore, the exposed semiconductor surface is deeply etched. This depth d is about 1 to 10 μm. And d is the thickness Tm of the n layer
and n is the thickness of one layer Tn-, so that the following holds true.

It is sufficient for Tn- to be 0.5 to 1.0 μm, but if it is too thin, the interface with the surface protective film tends to be affected. Also,
In the case of Tn-kid, the angle θ between the barrier metal 3 and the n-n layer boundary line approaches 180C, and the electric field is again concentrated at this point, resulting in the effect of deeply etching the semiconductor substrate 1 and creating a curvature. will disappear. Therefore, the appropriate thickness of the n layer is about 0.1 to 0.5 times Dl7). Next, Nl was applied as a barrier metal to the deeply etched semiconductor substrate.
, Pt, Au, or alloys such as NiPd. In the case of electroplating, the deposition rate is proportional to the amount of electricity.

Therefore, it is easy to understand that if the specific resistance of the n-layer is made sufficiently larger than that of the n-layer, most of the current will flow through the n-layer and not through the n-layer. Therefore, the barrier electrode is selectively formed only in the exposed portion of the n-layer. Because the curvature of its periphery is large, concentration of electric field hardly occurs, and it is not easily affected by the surface protective film as in the conventional case. As can be seen from the above explanation, S. B. D can be obtained by a simple method and has very high practical value. Next, an embodiment of the manufacturing method according to the present invention will be described.

n- that has been washed with an organic solvent such as trichlene, etc.
A 1.0 μm thick SlO2 film 2 is formed on the upper main surface of the Si wafer 1 by thermal oxidation. Here, the carrier concentration and thickness of each layer in the n-Si wafer are determined as follows. After this, the opening 21 for barrier metal formation is formed using photolithography technology.
The opening 21 is opened to expose the Si surface.

The exposed S1 surface is chemically etched with a commonly used etching solution consisting of hydrofluoric acid and nitric acid to form a recess with a depth d24 μm.

Then, barrier metal 3 is electroplated using n-Si wafer 1 as a cathode. The current density at that time is 0.2A/
If the concentration is below Cd, precipitation into the n layer will hardly occur. A NiPd alloy plating solution is used as the plating solution.
The thickness of the plating is preferably 0.05 to 0.5 μm. 0.
If it is thinner than 0.5 μm, pinholes are likely to be formed, and the metal (for example, gold) formed thereon will diffuse into the Si.

On the other hand, if it is thicker than 0.5 μm, the internal strain of the plating film becomes large and it becomes easy to peel off.

Next, an electrode 7 for protecting the barrier metal 3 is formed.
This electrode 7 is suitably formed using gold by a plating method.
Even in this case, it is not formed on the n layer. Finally, if an ohmic electrode 8 made of nickel or the like is formed on the lower main surface of the semiconductor substrate 1, the S.I. B. D is completed. As explained above,
When a semiconductor substrate having a surface protection film is partially etched, the semiconductor substrate is inevitably undercut, resulting in an overhang of the surface protection film. In the conventional barrier metal forming method, the barrier metal did not adhere to the lower part of the eaves, resulting in a large reverse leakage current. However, if this invention is used to create an electrode structure in which the barrier metal is deposited also on the lower part of the eaves, but not on the part in contact with the surface protective film, an excellent S with low reverse leakage current can be achieved. ．． B. D can be obtained with good reproducibility. FIG. 4 shows an example of reverse voltage and current characteristics in an area of about 8.5 d in the above embodiment. Figure 4A shows the characteristics of the conventional device, which has a large leakage current and a low breakdown voltage. Figure 4 shows the characteristics according to the present invention, and the leakage current is very small and the withstand voltage is high. In addition, S. B. The pressure yield of D is not shown in Figure 5. The number of chips is arbitrarily selected from 50 pieces and 10 pieces, and the number of chips with respect to withstand voltage is shown. FIG. 5C shows the case without the n layer, which is easily influenced by the surface protective film and has a gentle curve with a peak around 35V. FIG. 5 2 shows the case where there is one layer of n according to the present invention, which has a sharp peak around 40, and it can be seen that the yield of withstand voltage is significantly improved. Although the case where an n-Si wafer is used as the substrate has been explained above, it goes without saying that P-Si can also be used as a substrate.
Other semiconductors such as Ge, GaAs, and epitaxially grown semiconductors have similar effects.

Although the embodiments have been described with respect to diodes, it goes without saying that the present invention can be applied to semiconductor devices having shot barrier electrodes other than diodes. As explained above, according to the present invention, a shot barrier is formed in a predetermined second semiconductor region by electroplating, and a drop in breakdown voltage at the boundary between the surface protective film and the semiconductor substrate is prevented, and a high breakdown voltage is achieved. A shot barrier semiconductor device with high yield can be obtained.

[Brief explanation of the drawing]

Figure 1 shows a general S. B. Cross-sectional view showing D, Figure 2 a-c
is the conventional S. B. FIG. 3 is a sectional view showing an improved structure of S.D. manufactured by applying this invention. B. Sectional view of D, 4th
The figure shows the S. B. The reverse characteristic diagram of D, FIG. 5, is a diagram showing the withstand voltage yield. In the figure, 1 is a semiconductor substrate, 2 is a surface protective film, 3 is a barrier metal, 5 is an eaves portion, 11 is a first semiconductor region, 12 is a second semiconductor region, and 13 is a third semiconductor region.

Claims (1)

[Claims] 1. A second semiconductor region having the same conductivity type as the first semiconductor region having a high impurity concentration and having a lower impurity concentration is formed, and further on the second semiconductor region. a step of forming a third semiconductor region having the same conductivity type as the third semiconductor region and having a sufficiently lower impurity concentration than the third semiconductor region; a step of forming a surface protection film on the third semiconductor region; a step of removing a portion by a photolithography process to expose the surface of the third semiconductor region, and performing air etching from the exposed semiconductor surface to form a recess extending beyond the third semiconductor region into the second semiconductor region. forming a barrier metal layer on the exposed surface of the second semiconductor region by electroplating using the first semiconductor region as an electrode in the recess; forming an electrode on the barrier metal layer; A method for manufacturing a Schottky barrier semiconductor device, including the step of: 2. Claim 1, wherein each semiconductor region is made of silicon and a surface protective film is formed by thermal oxidation.
A method for manufacturing a Schottky barrier semiconductor device as described in 1.