JPS5931992B2 - semiconductor rectifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a new μm film with small forward potential drop and high speed.
Regarding junction diodes.

Forward potential drop (hereinafter abbreviated as FVD).

Demand for small diodes ( ) has increased in recent years with the development of low-voltage, large-current rectifier circuits, such as switching regulators. Conventionally, as a small FVD diode, a Schottky barrier diode that utilizes a rectifying contact between a metal and a semiconductor is known.

This Schottky barrier diode has a FVD of conventional P
Although it has the advantage of being smaller than an N-junction diode, it is difficult to obtain a large-area rectifying contact that can carry a large current uniformly and with good reproducibility, and its reverse leakage current characteristics at high temperatures are different from conventional ones. Since it has the disadvantage of being inferior to a PN junction diode, it is difficult to put it into practical use. The present inventors first proposed a new PN junction diode that improved the FVD to the same or lower level as the above-mentioned Schottky barrier diode and had excellent high frequency characteristics (Japanese Patent Application No. 1983
-93109).

FIG. 1 shows the structure of a diode which is a conventional example for the present inventors.

In the figure, an n-type semiconductor single-crystal layer 12 is formed adjacent to an n+-type semiconductor single-crystal layer 11, a p-type single-crystal layer 16 is formed on a part of the surface of the N-type single-crystal layer 12, and both A Pn junction is formed at the interface. A p-type guard ring 13 is formed surrounding the p-type single crystal layer 16. A p-type semiconductor polycrystalline layer 15 is formed above the p-type single crystal layer 16 and the p-type guard ring 13. 14 is a 5102 protective layer.

When p-type polycrystalline layer 15 is deposited on the surface of n-type semiconductor layer 12 by high-temperature vapor phase growth, an extremely thin p-type silicon single layer 16 is formed by diffusion of impurities from p-type polycrystalline layer 15. be done. This type of diode is characterized by low FVD and short reverse recovery time trr. This principle will be explained below. The present inventors have already proposed that the forward potential drop VF of a Pn junction diode can be reduced by reducing the total amount of impurities per unit area of the p layer in the Pn junction of a Pnn+ structure diode (see above). (see official bulletin).

In the figure showing the relationship between FVD (5Q) of the diode shown in Figure 2a, DB in the figure is the thickness of the n-type single crystal layer 12.The effect of reducing FVD by reducing Q as shown in Figure 2b. is more significant as the thickness DB of the n-type single crystal layer 12 becomes smaller.The reason for this will be explained with reference to FIG. 3.
When b is relatively large, b is relatively small. Pnn
As shown in FIG. 2a, the FVD of the + structure diode is expressed as the sum of the potential drop VJ at the junction <15 and the potential drop VB at the n-type single crystal layer 12, that is, F-B+V.

As shown in FIG. 3, when the total amount Q of impurities in the p-type single crystal layer 16 is reduced, the potential drop VJ at the junction is reduced. On the other hand, as for the potential drop B in the n-type single crystal layer 12, the number of minority carriers injected into this layer 12 decreases, so the carriers contributing to conductivity modulation decrease, and VB increases. The degree of increase in VB strongly depends on the thickness DB of the N-type single crystal layer 12, which also affects conductivity modulation. In other words, reducing DB not only reduces the thickness of the n-type single crystal layer 12 as a resistor, but also has the effect of promoting an increase in the number of carriers that contribute to conductivity modulation. The effect is to suppress the degree of increase in B. Therefore, if DB is made small, the FVD of the diode can be made small by making the total amount Q of impurities in the p-type single crystal layer 16 small. In this way, the smaller DB is, the smaller the forward potential drop VF can be, but on the other hand, in order to obtain a predetermined reverse breakdown voltage, DB needs to have a thickness of a certain value or more, so n The thickness DB of the type semiconductor layer 12 is determined in consideration of the reverse breakdown voltage. In addition to lowering FVD by reducing Q, the n-type semiconductor layer 12
Since the number of minority carriers injected into the signal is reduced by reducing Q, the reverse recovery time Trr can also be reduced at the same time.

FIG. 4 shows the expansion of the depletion layer when a reverse voltage is applied to the diode shown in FIG. 1.

The reverse breakdown voltage of the device is determined by the radius of curvature R of the guard ring portion and the thickness of the n-type semiconductor layer 12, but it is not the actual thickness DB of the n-type semiconductor layer 12 that contributes to the reverse breakdown voltage, but the guard ring. DW is obtained by subtracting the depth D of . On the other hand, FV
The thickness of the n-type single crystal layer 12 contributing to D is DB. Note that the thickness of the p-type single crystal layer 16 is extremely thin in order to reduce Q, so it is so small that it can be ignored. As mentioned above, in order to reduce FVD, it is necessary to make the thickness of the n-type single crystal layer 12 as small as possible, but for the present inventor, as shown in FIG. In the case where a guard ring is used to improve the reverse breakdown voltage of This is disadvantageous in reducing the loss of the diode. Moreover, when a guard ring is formed, holes are injected into the n-type semiconductor layer 12 from the guard ring 13 of the p-type diffusion layer when forward current is applied, increasing the number of minority carriers in the n-type semiconductor layer 12, thereby increasing the reverse recovery time Trr. It was becoming the cause. In this way, the inventor believes that in the conventional example of a diode with a guard ring, the guard ring is used to prevent an increase in reverse leakage current due to electric field concentration at the junction end. I was getting used to it.

The purpose of the present invention is to solve the above-mentioned disadvantages and to reduce the forward potential drop.
Another object of the present invention is to provide a diode that does not cause an increase in reverse recovery time.

The semiconductor rectifying device of the present invention is characterized in that a semiconductor single crystal layer of one conductivity type having a predetermined thickness and a recess provided on its surface is formed with a semiconductor of the other conductivity type having a predetermined impurity concentration along the recess surface. This is where a single crystal layer is formed.

An embodiment of the present invention will be described below with reference to the drawings.

To obtain the diode of this example, (a) a silicon substrate having an n type silicon single crystal layer 12 epitaxially formed on an n+ type silicon single crystal layer 11 and (b) 110
The SiO2 oxide film 14 was formed by steam oxidation at 0°C for 130 minutes.
is formed to a thickness of 1 μm, and a part of the n-type single crystal layer 12 is exposed by photoetching.

(c) Next, the exposed surface portion of the n-type single crystal layer 12 is etched by 3 μM by vapor phase etching in an epitaxial reactor. Etch to a depth of 100 mL to create a recess.

(d) Subsequently, polycrystalline silicon is grown by an epitaxial method using trichlorosilane containing diborane at a temperature of 900° C. for 25 minutes to form a p-type polycrystalline silicon layer 15 to a thickness of 201 tm. During this polycrystalline layer formation,
Boron is released from the p-type polycrystalline silicon layer 15. The p-type single crystal layer 21 is simultaneously formed by diffusion into the type silicon layer 12, which is as thin as 0.05 μm and has a low impurity concentration. Thereafter, electrodes are formed on the surfaces of the p-type polycrystalline layer 15 and the n+-type single-crystalline layer 11 by vapor deposition, and then lead terminals are attached to complete the diode. The function of the diode of this example obtained through the above steps will be explained below.

A Pn junction is formed at the interface between the p-type single crystal silicon layer 21 and the n-type silicon layer 12, and when viewed in cross section as shown in FIG. 5d, the end of the rectifying portion is curved. This portion serves as a guard ring that alleviates electric field concentration at the end of the rectifying portion when a reverse voltage is applied. The impurity concentration of the p-type silicon layer 21 is 6X1017at0ms/C! ! l
This is sufficient to obtain a withstand voltage of 100V. According to this structure, since the thickness of the N-type silicon layer 12 directly under the rectifying portion is thinner, the forward potential drop VF can be made smaller than in the conventional guard ring method. Furthermore, since the p-type silicon layer 21 has a very thin thickness of 0.05 μm, the total amount of impurities at the end of the rectifying section is 3×10 9 at0 ms/CT per unit length in the circumferential direction! It is L.

In contrast, conventional standard guard rings have a radius of 3 μm.
, under the condition that the impurity concentration is 2×1018 at001 S/ml, the total amount of impurities is 3×1011 at0 ms/C per unit length in the circumferential direction of the guard ring! It is RL. That is, according to the present invention, the total amount of p-type impurities is two orders of magnitude smaller.
Therefore, the injection of holes into the n-type silicon layer during forward current conduction is very small, and the reverse recovery time does not increase due to the guard ring as in the conventional case. Also,
According to experiments by the inventors, when DB is 30 μm or less, Q
The effect is that the FVD is lowered by the reduction in the FVD.
In addition, in practice, the upper limit of Q is 1×1016at0ms/d
, and the lower limit is 2×10 11 at0 ms/Crl. When Q is larger than the above upper limit, FVD does not decrease in practical terms. Also, if Q is smaller than the above lower limit, the p-type single crystal layer 2
Unless the thickness of the diode is made small, holes will occur and it will not be possible to obtain the reverse breakdown voltage required for a diode in practical use. As described in detail above, according to the present invention, it is possible to obtain a Pn junction diode with lower loss and higher speed than the conventional one.

Moreover, according to the present invention, there is no need for a guard ring diffusion process as in the conventional method, so there is an advantage that the manufacturing process can be shortened compared to the conventional method. Further, in the above embodiment, etching to form a recess on a part of the surface of the n-type silicon layer 12 was carried out using vapor phase etching, but this can also be carried out by other chemical etching using an HF-HNO3 type acid.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of a conventional low-loss diode with a guard ring, and Figure 2 is a diagram showing the total amount of impurities per unit area of a p-type single crystal layer and the forward potential drop FVD of the diode. Figure 3 is a diagram showing the relationship between Q and potential drop at each part of the diode when the thickness DB of the n-type single crystal layer is relatively large and relatively small. For the inventors, this is a diagram showing the expansion of the depletion layer of a conventional low-loss diode with a guard ring when a reverse voltage is applied, and FIG. 5 is a diagram showing the main manufacturing process of an embodiment of the present invention. . Explanation of symbols, 11...n+ type semiconductor single crystal layer,
12...N-type semiconductor single crystal layer, 13...
・P-type guard ring, 14...SiO2 film, 1
5...p-type semiconductor polycrystalline layer, 16, 21...
...p-type semiconductor single crystal layer.

Claims (1)

[Claims] 1. A first semiconductor single crystal layer of one conductivity type, and a first semiconductor single crystal formed adjacent to the first semiconductor single crystal layer and having a recessed portion on the opposite surface to the first semiconductor crystal layer. The layer has an impurity concentration lower than that of the layer and has a thickness of 30μ directly below the recess.
A Pn junction is formed between the second semiconductor single crystal layer of one conductivity type having a conductivity of less than m and the second semiconductor single crystal layer adjacent to the recess surface and along the recess shape, and the total amount of impurities is 2. ×10^1^1~10^1^6atoms/cm^2
, and the conductivity type of the third semiconductor single crystal layer is changed by diffusion of an impurity that is adjacent to the third semiconductor single crystal layer and determines the conductivity type of this layer. A semiconductor rectifier comprising at least a semiconductor polycrystalline layer of the other conductivity type, and a pair of electrodes in ohmic contact with the first semiconductor single crystal layer and the semiconductor polycrystalline layer.