JPS5931254B2 - Synchronized starting pulse train generator - Google Patents

Synchronized starting pulse train generator

Info

Publication number
JPS5931254B2
JPS5931254B2 JP533576A JP533576A JPS5931254B2 JP S5931254 B2 JPS5931254 B2 JP S5931254B2 JP 533576 A JP533576 A JP 533576A JP 533576 A JP533576 A JP 533576A JP S5931254 B2 JPS5931254 B2 JP S5931254B2
Authority
JP
Japan
Prior art keywords
signal
pulse train
circuit
oscillation
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP533576A
Other languages
Japanese (ja)
Other versions
JPS5289050A (en
Inventor
哲郎 米沢
清志 土屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP533576A priority Critical patent/JPS5931254B2/en
Publication of JPS5289050A publication Critical patent/JPS5289050A/en
Publication of JPS5931254B2 publication Critical patent/JPS5931254B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03Astable circuits

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【発明の詳細な説明】 本発明は電子機器、その他制脚装置において、電源投入
時に自動的に所定パルス列を発生させるための装置に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for automatically generating a predetermined pulse train when power is turned on in electronic equipment and other leg restraint devices.

従来、電源投入時に自動的に所定処理を実行させるため
の信号発生方法として、第1図おヨヒ第2図に示すよう
に、電源投入信号Wvに同期して抵抗1、コンデンサ2
で構成される回路で積分動作を開始させ、所定のレベル
に達した時に論理信号に変換動作する増巾器3を通し、
出力信号W。
Conventionally, as a signal generation method for automatically executing a predetermined process when the power is turned on, a resistor 1 and a capacitor 2 are connected in synchronization with the power-on signal Wv, as shown in Fig.
The signal is passed through an amplifier 3 that starts the integration operation in a circuit consisting of , and converts it into a logic signal when it reaches a predetermined level.
Output signal W.

を得ることにより、電源投入時の過渡状態を経過後に、
所定処理を実行させるための論理信号W。
After passing through the power-on transient state,
A logic signal W for executing a predetermined process.

を得ることが行なわれてきた。It has been done to obtain.

しかし、この方法は、レジスタ回路等のりセット用信号
として用いる場合を除いて種々の難点があった。
However, this method has various drawbacks except when used as a signal for setting a register circuit or the like.

すなわち、積分回路の定数の変動、増巾器の動作レベル
の温度変化等により、遅延時間に変動が生ずるとともに
、緩和な積分信号を論理信号としてステップ状信号に変
換する時に生ずるチャツタ信号が、しばしば発生した。
In other words, fluctuations in the constants of the integrating circuit, temperature changes in the operating level of the amplifier, etc. cause fluctuations in the delay time, and chatter signals that occur when converting a gentle integral signal into a step signal as a logic signal often occur. Occurred.

また、単一レベル変化しか得られないために、複雑な処
理シーケンスを実行させるには、別の回路と組合せるこ
とが必要であった。
Also, since only a single level change could be obtained, combinations with other circuits were required to perform complex processing sequences.

本発明&ζ上述の欠点を除去するために成されたもので
、その特徴とするところは、外部信号によって同期化制
御のできる発振回路と、電源起動待積分動作を開始する
積分回路を備え、その積分回路出力信号と、上記発振回
路の信号との論理積信号により、同期化制御信号を作成
し、前記発振回路を停止制御し、電源起動時に起動パル
ス列を発生するように構成したところにある。
The present invention &ζ has been made to eliminate the above-mentioned drawbacks, and its features include an oscillation circuit that can be synchronized by an external signal, and an integration circuit that starts the integration operation while waiting for the power supply to start. A synchronization control signal is created by an AND signal of an output signal of an integrating circuit and a signal of the oscillation circuit, the oscillation circuit is controlled to stop, and a starting pulse train is generated when the power supply is started.

以下、第3図および第4図を用いて、詳細に説明する。A detailed explanation will be given below using FIGS. 3 and 4.

抵抗1、コンデンサ2の直列回路に電源WVが投入され
ると、緩和な積分信号wIを発生する。
When power supply WV is applied to the series circuit of resistor 1 and capacitor 2, a gentle integral signal wI is generated.

また、電源投入に同期して発振回路6は発振を開始する
Further, the oscillation circuit 6 starts oscillating in synchronization with the power-on.

論理積回路4に、発振回路6の帰還信号WFと積分信号
W工を入力し、その論理積を得るように構成すると、緩
和な積分信号を論理信号として、“1“と“01′に区
別する電圧レベルを第4図に示すようにVsとすると、
積分信号W□がVsに到達し、且つ、帰還信号WFが1
11“の状態にある時、両者の論理積が得られる。
When the AND circuit 4 is configured to input the feedback signal WF of the oscillation circuit 6 and the integral signal W and obtain the logical product, it is possible to distinguish between "1" and "01" using the relaxed integral signal as a logic signal. Assuming that the voltage level is Vs as shown in Figure 4,
The integral signal W□ reaches Vs, and the feedback signal WF becomes 1
11'', the logical product of both can be obtained.

この出力を否定回路5を介して発振回路6を停止状態に
制御すると、緩和な積分信号に基づくチャツタ信号の発
生を防止し、且つ、発振回路6の停止寸前のパルス巾を
常に発振時の定常パルス巾に保つことができる。
When this output is controlled to stop the oscillation circuit 6 through the inverter 5, it is possible to prevent the generation of a chatter signal based on a gentle integral signal, and to always keep the pulse width of the oscillation circuit 6 on the verge of stopping to the steady state during oscillation. The pulse width can be maintained.

これに対し、例えば、発振出力信号と積分信号の単なる
論理積を取った信号は、第4図WF信号の最後のパルス
信号Pに示されるように、所定パルス巾より狭くなる可
能性がある。
On the other hand, for example, a signal obtained by simply ANDing the oscillation output signal and the integral signal may have a pulse width narrower than the predetermined pulse width, as shown in the last pulse signal P of the WF signal in FIG.

このような信号が生ずると、所定パルス列を必要とする
電子機器にチャツタ信号と同様、未確定な信号を与える
ことになり誤動作の原因となる。
When such a signal is generated, an undefined signal similar to a chatter signal is given to electronic equipment that requires a predetermined pulse train, causing malfunction.

つぎに、本発明の第5図を用いて、発振出力信号と積分
信号の、同期化停止制御によって発振パルス巾を常に定
常パルス巾に保つための動作について説明する。
Next, using FIG. 5 of the present invention, an explanation will be given of an operation for always maintaining the oscillation pulse width at a steady pulse width by synchronization stop control of the oscillation output signal and the integral signal.

ナントゲート(以下NANDゲートと記す。NAND gate (hereinafter referred to as NAND gate).

)10.11,12と抵抗13、コンデンサ14で構成
される発振回路6は、NANDゲート9の出力が°11
1′の状態にあると、抵抗13、コンデンサ14で定ま
る発振周波数で、常に発振を持続する。
)10.The oscillation circuit 6, which is composed of 11, 12, a resistor 13, and a capacitor 14, has an output of the NAND gate 9 at 11
In the state 1', oscillation is always maintained at the oscillation frequency determined by the resistor 13 and capacitor 14.

従って、出力増巾器15の出力端子16からは電源投入
とともに、所定パルス巾のW8信号を得ることができる
Therefore, the W8 signal with a predetermined pulse width can be obtained from the output terminal 16 of the output amplifier 15 when the power is turned on.

また、帰還信号端子8の信号WFは、NANDゲート1
1の入力信号に相当するため、Ws倍信号否定信号に相
当する信号が出力される。
Further, the signal WF at the feedback signal terminal 8 is the NAND gate 1
Since this corresponds to an input signal of 1, a signal corresponding to a Ws times signal negation signal is output.

このWF倍信号NANDゲート9に入力されるNAND
ゲート9は緩和な積分信号W□との論理積信号の否定信
号を出力する。
NAND input to this WF multiplied signal NAND gate 9
The gate 9 outputs a negative signal of the AND signal with the relaxed integral signal W□.

このとき、帰還信号WFがIf □ IIのときに積分
信号wIが11′に到達する場合と、帰還信号がII
I IIのときに積分信号がIf I Ifに到達する
場合とが考えられる。
At this time, there is a case where the integral signal wI reaches 11' when the feedback signal WF is If □ II, and a case where the integral signal wI reaches 11' when the feedback signal WF is If □ II;
A case can be considered in which the integral signal reaches If I If when I II.

前者の場合には、論理積が得られず、帰還信号WFがI
I I IIとなるまで待たされることになる。
In the former case, the logical product cannot be obtained and the feedback signal WF is
You will have to wait until I II II.

後者の場合には、帰還信号wFがIf I IIとなっ
ているところに緩和な積分信号W■がII I IIに
到達するために、雑音、その他の影響を受けて、NAN
Dゲート9の出力からは、しばしばチャツタ信号が発生
する。
In the latter case, when the feedback signal wF is If I II, the mild integral signal W reaches II I II, so the NAN is affected by noise and other factors.
A chatter signal is often generated from the output of the D gate 9.

この信号は発振回路6を構成するNANDゲートに入力
されるが、しかし他の一方の入力信号すなわちNAND
ゲート12の出力は、この時常にII () IIの状
態に存在するのでNANDゲート10の出力にはチャツ
タ信号は伝達されない。
This signal is input to the NAND gate constituting the oscillation circuit 6, but the other input signal, that is, NAND
Since the output of the gate 12 is always in the II () II state at this time, no chatter signal is transmitted to the output of the NAND gate 10.

なぜならば、帰還信号WFがII I IIの状態にあ
るときNANDゲート9の出力がII I IIとなっ
ていたのだから、発振回路内のNANDゲ−)10のも
う一方の入力は10゛でなげればならない。
This is because when the feedback signal WF is in the state of II I II, the output of the NAND gate 9 is II I II, so the other input of the NAND gate 10 in the oscillation circuit must be at 10°. Must be.

よってNANDゲート9の出力にチャツタが存在しても
、発振回路の主要部には伝達されず、NANDゲート1
00入力で阻止される。
Therefore, even if chatter exists in the output of NAND gate 9, it is not transmitted to the main part of the oscillation circuit, and
Blocked by 00 input.

発振周波数の半周期経過後NANDゲート12の出力が
If I IIに変化しても、NANDゲート9の出力
でしゃ断されるので、発振ループは切離される。
Even if the output of the NAND gate 12 changes to If I II after a half cycle of the oscillation frequency has elapsed, it is cut off by the output of the NAND gate 9, so the oscillation loop is disconnected.

従って、第4図WFの波形は、本発明を用いると、所定
パルス巾より狭いパルスPは存在せず、点線で示される
状態で停止する。
Therefore, when the present invention is used, the waveform of FIG. 4 WF does not have a pulse P narrower than the predetermined pulse width, and the waveform stops at the state shown by the dotted line.

このように本発明を用いると、電源投入時に自動的に所
定パルス列を発生でき、且つ、そのパルス巾を常に発振
時定数に維持し、一定時間後、同期化停止制御ができる
ので、種々の装置に応用でき、実用に供しきわめて有効
である。
As described above, by using the present invention, a predetermined pulse train can be automatically generated when the power is turned on, and the pulse width can always be maintained at the oscillation time constant, and synchronization stop control can be performed after a certain period of time, so that it can be used in various devices. It can be applied to various fields and is extremely effective in practical use.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は積分回路を用いた論理信号発生時の波形図、第
2図は第1図を抵抗し、コンデンサ2、増巾器3を用い
て実現した結線図、第3図は本発明を実現するための動
作説明図であり、4は積分信号W□と発振回路6の帰還
信号%の論理積を得るための論理積回路、5は否定回路
、7は同期化起動パルス列を取り出す出力端子である。 第4図は本発明の各部の動作波形図、第5図は本発明の
実施例であり、同期化発振回路6は、NANDゲート1
0,11,12と抵抗13、コンデンサ14により構成
され、9は同期化制御信号を作成するNANDゲート、
15は出力増巾器である。
Fig. 1 is a waveform diagram when generating a logic signal using an integrator circuit, Fig. 2 is a wiring diagram realized by using a resistor, a capacitor 2, and an amplifier 3 as shown in Fig. This is an explanatory diagram of the operation to realize this, where 4 is an AND circuit for obtaining the AND of the integral signal W□ and the feedback signal % of the oscillation circuit 6, 5 is an inversion circuit, and 7 is an output terminal for taking out the synchronized activation pulse train. It is. FIG. 4 is an operation waveform diagram of each part of the present invention, and FIG. 5 is an embodiment of the present invention.
0, 11, 12, a resistor 13, and a capacitor 14; 9 is a NAND gate for creating a synchronization control signal;
15 is an output amplifier.

Claims (1)

【特許請求の範囲】[Claims] 1 外部信号によって発振制御される同期化発振回路と
、電源起動時に積分動作を行なう積分回路を備え、その
積分回路出力信号と前記発i回路帰還信号との論理積信
号により、前記発振回路を停止制御するようにしたこと
を特徴とする同期化起動パルス列発生装置。
1 Equipped with a synchronized oscillation circuit whose oscillation is controlled by an external signal and an integration circuit that performs an integration operation when the power is turned on, the oscillation circuit is stopped by an AND signal of the integration circuit output signal and the oscillator i circuit feedback signal. A synchronized activation pulse train generator characterized in that the synchronized activation pulse train generator is configured to control the synchronized activation pulse train.
JP533576A 1976-01-20 1976-01-20 Synchronized starting pulse train generator Expired JPS5931254B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP533576A JPS5931254B2 (en) 1976-01-20 1976-01-20 Synchronized starting pulse train generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP533576A JPS5931254B2 (en) 1976-01-20 1976-01-20 Synchronized starting pulse train generator

Publications (2)

Publication Number Publication Date
JPS5289050A JPS5289050A (en) 1977-07-26
JPS5931254B2 true JPS5931254B2 (en) 1984-08-01

Family

ID=11608351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP533576A Expired JPS5931254B2 (en) 1976-01-20 1976-01-20 Synchronized starting pulse train generator

Country Status (1)

Country Link
JP (1) JPS5931254B2 (en)

Also Published As

Publication number Publication date
JPS5289050A (en) 1977-07-26

Similar Documents

Publication Publication Date Title
JPH04232519A (en) Self-adjusting clock generator
US4864255A (en) Oscillator capable of quickly supplying a stable oscillation signal
JPS6240886B2 (en)
SE8101540L (en) SPEED regulating device
US4857868A (en) Data driven clock generator
JPS5931254B2 (en) Synchronized starting pulse train generator
JPH05303444A (en) Clock signal feeder
JPS6148726B2 (en)
JPS63185121A (en) Oscillation stop preventing circuit
JPS6348203B2 (en)
JP2995804B2 (en) Switching regulator soft start circuit
JPH049336B2 (en)
JPH06188631A (en) Oscillation circuit
JPH03274810A (en) Semiconductor integrated circuit
JPH118538A (en) Repeat signal stop detection circuit
JPS6333806B2 (en)
SU941975A1 (en) Computer clocking device
SU1401577A1 (en) Pulse shaper
JPH1068763A (en) Timing signal generating circuit
JP3147441B2 (en) Switching power supply controlling semiconductor device and switching power supply device
JPH0366220A (en) Oscillator circuit
KR100760868B1 (en) Device for stabilizing fail fault of microprocessor
JPS61198812A (en) Reference signal generating circuit
JPH0449705Y2 (en)
JPH0147812B2 (en)