JPS5931254B2 - Synchronized starting pulse train generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for automatically generating a predetermined pulse train when power is turned on in electronic equipment and other leg restraint devices.

Conventionally, as a signal generation method for automatically executing a predetermined process when the power is turned on, a resistor 1 and a capacitor 2 are connected in synchronization with the power-on signal Wv, as shown in Fig.
The signal is passed through an amplifier 3 that starts the integration operation in a circuit consisting of , and converts it into a logic signal when it reaches a predetermined level.
Output signal W.

After passing through the power-on transient state,
A logic signal W for executing a predetermined process.

It has been done to obtain.

However, this method has various drawbacks except when used as a signal for setting a register circuit or the like.

In other words, fluctuations in the constants of the integrating circuit, temperature changes in the operating level of the amplifier, etc. cause fluctuations in the delay time, and chatter signals that occur when converting a gentle integral signal into a step signal as a logic signal often occur. Occurred.

Also, since only a single level change could be obtained, combinations with other circuits were required to perform complex processing sequences.

The present invention &ζ has been made to eliminate the above-mentioned drawbacks, and its features include an oscillation circuit that can be synchronized by an external signal, and an integration circuit that starts the integration operation while waiting for the power supply to start. A synchronization control signal is created by an AND signal of an output signal of an integrating circuit and a signal of the oscillation circuit, the oscillation circuit is controlled to stop, and a starting pulse train is generated when the power supply is started.

A detailed explanation will be given below using FIGS. 3 and 4.

When power supply WV is applied to the series circuit of resistor 1 and capacitor 2, a gentle integral signal wI is generated.

Further, the oscillation circuit 6 starts oscillating in synchronization with the power-on.

When the AND circuit 4 is configured to input the feedback signal WF of the oscillation circuit 6 and the integral signal W and obtain the logical product, it is possible to distinguish between "1" and "01" using the relaxed integral signal as a logic signal. Assuming that the voltage level is Vs as shown in Figure 4,
The integral signal W□ reaches Vs, and the feedback signal WF becomes 1
11'', the logical product of both can be obtained.

When this output is controlled to stop the oscillation circuit 6 through the inverter 5, it is possible to prevent the generation of a chatter signal based on a gentle integral signal, and to always keep the pulse width of the oscillation circuit 6 on the verge of stopping to the steady state during oscillation. The pulse width can be maintained.

On the other hand, for example, a signal obtained by simply ANDing the oscillation output signal and the integral signal may have a pulse width narrower than the predetermined pulse width, as shown in the last pulse signal P of the WF signal in FIG.

When such a signal is generated, an undefined signal similar to a chatter signal is given to electronic equipment that requires a predetermined pulse train, causing malfunction.

Next, using FIG. 5 of the present invention, an explanation will be given of an operation for always maintaining the oscillation pulse width at a steady pulse width by synchronization stop control of the oscillation output signal and the integral signal.

NAND gate (hereinafter referred to as NAND gate).

)10.The oscillation circuit 6, which is composed of 11, 12, a resistor 13, and a capacitor 14, has an output of the NAND gate 9 at 11
In the state 1', oscillation is always maintained at the oscillation frequency determined by the resistor 13 and capacitor 14.

Therefore, the W8 signal with a predetermined pulse width can be obtained from the output terminal 16 of the output amplifier 15 when the power is turned on.

Further, the signal WF at the feedback signal terminal 8 is the NAND gate 1
Since this corresponds to an input signal of 1, a signal corresponding to a Ws times signal negation signal is output.

NAND input to this WF multiplied signal NAND gate 9
The gate 9 outputs a negative signal of the AND signal with the relaxed integral signal W□.

At this time, there is a case where the integral signal wI reaches 11' when the feedback signal WF is If □ II, and a case where the integral signal wI reaches 11' when the feedback signal WF is If □ II;
A case can be considered in which the integral signal reaches If I If when I II.

In the former case, the logical product cannot be obtained and the feedback signal WF is
You will have to wait until I II II.

In the latter case, when the feedback signal wF is If I II, the mild integral signal W reaches II I II, so the NAN is affected by noise and other factors.
A chatter signal is often generated from the output of the D gate 9.

This signal is input to the NAND gate constituting the oscillation circuit 6, but the other input signal, that is, NAND
Since the output of the gate 12 is always in the II () II state at this time, no chatter signal is transmitted to the output of the NAND gate 10.

This is because when the feedback signal WF is in the state of II I II, the output of the NAND gate 9 is II I II, so the other input of the NAND gate 10 in the oscillation circuit must be at 10°. Must be.

Therefore, even if chatter exists in the output of NAND gate 9, it is not transmitted to the main part of the oscillation circuit, and
Blocked by 00 input.

Even if the output of the NAND gate 12 changes to If I II after a half cycle of the oscillation frequency has elapsed, it is cut off by the output of the NAND gate 9, so the oscillation loop is disconnected.

Therefore, when the present invention is used, the waveform of FIG. 4 WF does not have a pulse P narrower than the predetermined pulse width, and the waveform stops at the state shown by the dotted line.

As described above, by using the present invention, a predetermined pulse train can be automatically generated when the power is turned on, and the pulse width can always be maintained at the oscillation time constant, and synchronization stop control can be performed after a certain period of time, so that it can be used in various devices. It can be applied to various fields and is extremely effective in practical use.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram when generating a logic signal using an integrator circuit, Fig. 2 is a wiring diagram realized by using a resistor, a capacitor 2, and an amplifier 3 as shown in Fig. This is an explanatory diagram of the operation to realize this, where 4 is an AND circuit for obtaining the AND of the integral signal W□ and the feedback signal % of the oscillation circuit 6, 5 is an inversion circuit, and 7 is an output terminal for taking out the synchronized activation pulse train. It is. FIG. 4 is an operation waveform diagram of each part of the present invention, and FIG. 5 is an embodiment of the present invention.
0, 11, 12, a resistor 13, and a capacitor 14; 9 is a NAND gate for creating a synchronization control signal;
15 is an output amplifier.

Claims (1)

[Claims] 1 Equipped with a synchronized oscillation circuit whose oscillation is controlled by an external signal and an integration circuit that performs an integration operation when the power is turned on, the oscillation circuit is stopped by an AND signal of the integration circuit output signal and the oscillator i circuit feedback signal. A synchronized activation pulse train generator characterized in that the synchronized activation pulse train generator is configured to control the synchronized activation pulse train.