JPS5931094B2 - Arithmetic control method for electronic calculator with program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic control system for a programmable electronic computer having a program setting function.

Generally, in electronic desktop calculators, when a calculation is performed by operating an equal key, the result is obtained based on the settings of the round switch and decimal point designation switch. In other words, use the round switch to select free calculation mode or rounding calculation mode such as rounding, rounding down, etc., and then select d
Selection is made using mold point designation switches, and calculation result values are determined based on the designations of these switches and are recognized and displayed. Such arithmetic means were also used when executing program arithmetic operations in a programmable electronic calculator. Therefore, in conventional electronic calculators with programs, the calculation result value obtained by executing each program calculation for a program that is set to execute multiple calculations in succession is the calculation result of each calculation block. The result is a result value according to the specifications of each of the above switches, for example, cumulative calculations, scientific calculations that use approximation formulas many times to first obtain partial values and accumulate them sequentially, or multiple calculations. If you want to obtain each value and calculate the average of the resulting values (calculation to obtain standard deviation), etc., by rounding down or rounding to the nearest whole number, follow the mode set in advance with each switch above. Obtaining the result of each calculation block and sequentially executing subsequent calculations based on this value,
When the final result value is obtained, there is an inconvenience that there is a large difference between the actual result value and the final result value. Therefore, each equal operation in the calculation block before obtaining the final result obtains the result in free mode, and only when obtaining the final result do truncation or rounding to the nearest whole number. Although calculation results can be obtained, it is impossible to switch and control each of the above switches each time a program calculation is being executed due to the calculation system of the computer.Therefore, conventional program control has been used to obtain highly accurate calculation results. I couldn't get it. This invention was made in view of the above-mentioned circumstances, and in the program settings, an operation mode that follows the designation of the round switch and an operation mode that executes free mode calculation regardless of the designation of the round switch can be arbitrarily set. It is an object of the present invention to provide an arithmetic control method for an electronic calculator with a program, which can improve the versatility of the program for each operation when the operator uses the program, and can obtain highly accurate arithmetic results by executing the program operations. shall be.

An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 1, 11 is a keyboard, and this keyboard 11 includes numerical keys (1), (2), etc. (1), 6 (numeric keypad 1), etc. In addition to the usual function keys such as yen, various programmable keys for program settings are provided, and this programmable key group includes an equal key (hereinafter referred to as the free equal key) dedicated to the free calculation mode. It will be done. Reference numeral 12 denotes an arithmetic processing unit (hereinafter referred to as a processor unit) that controls various calculations and the overall operation. It is equipped with a functional unit that decodes various microinstructions and judgment signals, etc., a code generating functional unit, an address control functional unit that controls internal and external memory addresses, an arithmetic unit, a gate control unit, a flag storage unit, etc. There is. Reference numeral 13 denotes a mode designation flip-flop which is brought into the set state by the equal key 5 judgment signal N-Eq obtained from the processor unit 12, and set state by the free equal key 1 judgment signal F-Eq; Round switch for selecting and specifying free calculation (F), rounding calculation (Cut), rounding calculation (5/4), etc. 3, 15 is decimal point designation switch, 16 is digit signal Kl, K2...・KE, KP・・・・
...and the pit timing signal Tl in the above signal KE
, T2, . . . , a timing signal generating section φ. The set output signal of the above-mentioned flip-flop 13, the set output signal of the round switch 14, and the noise signal generator 16 are
The pit timing signals Tl, T2, T3 of the digit signal KE obtained from the above are supplied to a mode determination circuit 17 which obtains a mode determination signal. This mode determination circuit 17 is composed of AND gates A1 to A5, an inverter INV1, and an OR gate 01, and a flip-flop 13.
When the flip-flop 13 is in the set state, a mode determination signal synchronized with the bit timing signal T1 is obtained from the AND gate A3 regardless of the setting state of the round switch 14, and when the flip-flop 13 is in the set state, the setting state of the round switch 14 is obtained. , the corresponding AND gate A3,A
4 or A5 to obtain a mode determination signal according to the designation of the round switch 14 synchronized with the pit timing signal Tl, T2 or T3. Further, the setting output signal of the decimal point designation switch 15 is encoded by the encoder 18, and this encoded output (decimal point designation code) and the AND gate A3, A4, A5 output of the mode determination circuit 17 are controlled by data input via the OR gate 02. The signal is supplied to the circuit 19. This data input control circuit 19 inputs the output data of the OR gate 02, read data (DR) of the data memory (to be described later), numerical input data (DNu) obtained from the processor unit 12, and adder output data (DAO).
), register input control signal (XIN), mode sampling signal (MOD), data read out from other memory sections (DEX.R), etc., and controls input to the x register 20 for calculation and display. , AND gate A6, A7, A8 OR gate 03, inverter I
Consists of N2, NV3, etc. When the mode sampling signal (MOD) and the timing signal KE for storing data in the most significant digit of the display x register 20 are output, the mode determination signal obtained via the OR gate 02 is outputted from the AND gate A8 and Corresponding pits assigned to the mode bit storage digits of the , the third storage bit synchronized with T3 is referred to as the γ bit). That is, bit timing signal T1
The free mode determination signal obtained from the AND gate A3 in synchronization with the bit timing signal T2 is stored in the α bit, and the cut mode determination signal obtained from the AND gate A4 in synchronization with the bit timing signal T2 is stored in the β bit. 5/ obtained from AND gate A5 in synchronization
The 4 (rounded off) mode determination signal is stored in γ bits. Furthermore, at the time of outputting the timing signal KP, the decimal point code obtained from the encoder 18 is placed in the lower bits of the point exponent digit of the x register 20, and the decimal point information indicating the decimal point position of the placed number or calculation result is placed in the upper bits of the above digit. stored timing signals KE, KP and K
Numerical data is stored in the X register 20 in synchronization with the data input timing signal KD obtained from the timing signal generator 16 at times other than when F (timing for specifying the digit in which various calculation mode codes are stored) occurs. It is something that can be stored in a region. The contents of this X register 20 are supplied to the Y register 21 for calculation via an adder circuit provided in the processor unit 12, and a mode for detecting the calculation mode from the contents of the α, β, and γ bits in the mode bit storage digit. The signal is supplied to the detection section 22 and the display buffer register 23, and further supplied to the data memory 24 via the gate circuit G1. The mode detection unit 22 reads the contents of the α bit and β bit of the X register 20 with a read pulse φ1, and reads out the contents with a read pulse φ2 using two flip-flops Fa and Fb, and a timing signal KE-T3.
・It is composed of three flip-flops Fα, Fβ, Fγ whose read is controlled by φ1 and read by read pulse φ2, and the flip-flops Fα, Fγ are
Each set output of β, Fγ is a mode detection signal Dα, Dβ,
It is supplied to the processor unit 12 as Dγ. The data memory 24 also includes a plurality of (n) word data storage sections Ml, M2, .
w and a read address selector ASR that selects and specifies the data storage area to be read. This data memory 24 and the program memory 25 that stores the set microprogram are configured to include start address data AD8T obtained from the processor unit 12 and update address zeta AD(+1) which is controlled by +1 increments.
The address register 26 stores the
The address of the data memory 24 is specified according to the contents stored in the upper side (Au) of the address register 26, and the address of the data memory 24 is specified according to the contents stored in the upper side (Au) of the address register 26. The address of the program memory 25 is specified by the row specification based on the upper side (Au) content of the address register 26 and the column specification based on the lower side (AL) content. The data read from the data memory 24 is sent to the data input control circuit 19 via the gate circuit G3, and the data is sent to the program memory 25 by the operation of the programmable keys on the keyboard 11 during program setting (writing). Microprogram data inputted by the processor unit 12 is sent out via the processor unit 12, and the microprogram data is sequentially written into the address area specified by the address register 26 via the gate circuit G4. Microprogram data read out during program execution is stored in the instruction register 27 via the gate circuit G5, and then sent to the instruction determining section 28 via the gate circuit G6. Judgment result information obtained from the instruction judgment section 28 is sent to the processor unit 12. Further, the data stored in the display buffer register 23 is decoded by the display decoder 29 and supplied to the display section 30.
Further, 31 is a changeover switch for selecting and specifying the execution and setting of program calculations, and in the execution mode, the movable terminal is switched and connected to the fixed terminal COm, and the setting (writing) is performed.
In mode, it is switched and connected to the fixed terminal w. The output of this changeover switch 31 is determined by a determining section 32, and the determined signal is supplied to the processor unit 12. Here, the operation will be explained with reference to the flowchart shown in FIG. 2. At the time of program setting, the selector switch 31 is first selectively switched to the program setting (writing) side. As a result, the determination section 32 outputs a determination signal indicating program setting (writing) based on the sampling signal for the changeover switch at a predetermined timing output from the processor unit 12, and the processor unit 12. In response to this judgment signal, the processor unit 12 activates an internal memory (ROM) in order to sequentially write the program data inputted by keys from empty addresses in the program memory 25. A predetermined series of control micro-instructions causes the program memory 2 to
5, and set the write start address obtained by the search in the address register 26, etc.
Preparations for setting the program are made, and furthermore, control is performed to display that the preparation for setting has been completed by controlling the microinstructions. The series of operating procedures at this time is substantially the same as that of an existing computer having a program setting function, and since it is not the gist of the present invention, a detailed explanation will be omitted. When the programmer selectively operates the keys on the keyboard 11 in accordance with the desired program step, the code corresponding to the operated key is stored in the X register 20 via the data input control circuit 19, and this The contents of the X register 20 are supplied to a display buffer register 23 and also to the processor unit 12. The code stored in the display buffer register 23 is decoded by the decoder 29, and the contents of the key input are displayed on the display section 30. Furthermore, the processor unit 12
Then, detect the program content to be written from the input contents of the X register 20, encode it and write it to the address area of the program memory 25 specified by the address register 26, and further update the contents of the address register 26. Sends updated address data AD(+1). In this way, program settings are sequentially executed. When setting this program, when performing a program key operation to instruct the execution of each calculation block, for example, if you want to obtain only the final calculation result by rounding, set the final calculation step. When inputting the program key to instruct the execution of each calculation block except for the function keys, the free equal key of the programmable key group is operated instead of the equal key of the function key group, and the decimal point processing after execution of the calculation is performed in free mode. Only when setting the program and obtaining the final calculation result, simply input the = program key to indicate that the decimal point processing after execution of the calculation will be performed according to the mode state of the mode switch by operating one equal key in the function key group. . Therefore, the code corresponding to the free equal key is written in the program memory 25 at each step of obtaining the calculation result, except for the step of obtaining the final calculation result. Here, the operation when executing a calculation based on the program set as described above will be explained with reference to the flowchart shown in FIG. Switch selection.

As a result, a judgment signal indicating execution of the program operation is obtained from the judgment section 32 in synchronization with the sampling signal for the changeover switch, and this judgment signal is sent to the processor unit 12.
supplied to Based on this determination signal, the processor unit 12 first performs display control in order to issue a program selection designation instruction. When a program is specified by operating the keyboard 11, the processor unit 1
In step 2, the execution start address of the specified program is detected from the contents of this key input, and the detected address is set in the address register 26, and then the program memory 25 is access controlled and the contents of the address area specified by the address register 26 ( The microinstruction code (program microinstruction code) is read out, and execution of the arithmetic program is started.
After the microinstruction code read from the program memory 25 is stored in the instruction register 27, it is sent to the instruction determination section 28, where the contents are determined, and the determination information is sent to the processor unit 1.
Sent to 2. The processor unit 12 determines the contents of this judgment information and executes display or address update control in order to sequentially advance the program steps according to a preset program. , the number setting of calculation data such as the number of operations, the number of operands, etc., and the instruction to end the setting of the number of operations, etc. are executed. As a result, the operation data is stored in the X register 20 and Y register 21 (step 1). If the program content stored in the instruction register 27 in a certain calculation step is a code for setting an equal key or a free equal key, this judgment signal is sent to the processor unit 12, Therefore, the processor unit 12 determines that the calculation execution step has come (step 2), and, prior to starting the calculation, determines based on the judgment information whether the calculation mode is the calculation mode with the equal key setting or the calculation mode with the free equal key setting. Make a judgment (Step 3). If it is determined that the free calculation mode is set by the free equal key setting, the processor unit 12 outputs the free equal key determination signal F-Eq, and sets the mode specifying flip-flop 13 to the set state (step 1). 4). As a result, a free mode determination signal is output from the AND gate A3 of the mode determination circuit 17 in synchronization with the bit timing signal T1 (step 5), and this determination signal is further transmitted via the OR gate 02 and the data input control circuit 19. It is stored in the α bit of the mode bit storage digit assigned to the X register 20. In other words, ``1'' is written only to the alpha bit of the mode bit recording digit (step 6).The processor unit 12 then stores the function information based on the contents of the flag bit digit of the X register 20 and the X...Y registers 20, 21. The calculation is executed based on the calculation data stored in the numerical data storage area (step 7).Meanwhile,
The readout output of the mode bit storage digit of the X register 20 is sent to the mode detection section 22, and at this time, the content of the α bit is
”, the mode detection signal Dα is obtained from the flip-flop Fα, and this mode detection signal Dα is supplied to the processor unit 12. After the processor unit 12 executes the operation of one operation block, the mode detection section 2
From the mode detection signal obtained in step 2, it is determined whether to obtain the calculation result of the free mode or the rounding calculation result of cut mode, 5/4 mode, etc. (step 8), and in this case, the mode detection signal Dα is input. Therefore, post-processing related to the decimal point is executed to output the free mode calculation result (step 9). The calculation result data post-processed in the free mode is then sent to the data input control circuit 19.
After being stored in the numerical data storage area of the X register 20 via (Step 10).
Furthermore, the processor unit 12 outputs a computation end signal when the post-processing is completed, and this computation end signal causes each flip-flop Fa, Fb, Fα of the mode detection section 22 to be activated.
, Fβ, and Fγ are cleared. In this manner, when the free equal key setting step is reached during execution of program calculations, free mode calculation results are obtained for each calculation program regardless of the setting state of the round switch 14. Therefore, when executing a program of a certain calculation block, for example, the final calculation block, the program memory 25
Therefore, when the instruction code based on the equal key setting is read out, this code is set in the instruction register 27, and the contents of this code are judged by the instruction judgment section 28.

By supplying this judgment signal to the processor unit 12, the processor unit 12 judges that it is the step to execute the operation (step 2), and further executes the operation according to the designation of the round switch 14 by setting the equal key. mode is determined (Step 3). Based on the result of this judgment, the processor unit 12 outputs an equal key judgment signal (N-Eq) and puts the mode specifying flip-flop 13 into the reset state (step 11).
). As a result, the AND gate Al of the remote judgment circuit 17
, A2 are in the open state, and a mode determination signal according to the designation of the round switch 14 is obtained from the mode determination circuit 17. That is, for example, when the round switch 14 is set to 5/
If the mode is set to 4 mode, a 5/4 mode determination signal is output from the AND gate A5 in synchronization with the bit timing signal T3 (step 12). This judgment signal is then sent to the OR gate 02 and the data input control circuit 19.
The decimal point designation code obtained from the encoder 18 in synchronization with the timing signal KP is stored in the γ bit of the mode bit storage digit assigned to the It is stored in the lower bit. Then, the processor unit 12 executes calculations based on the contents of the XlY registers 20 and 21 (step 7), while the readout output of the mode bit storage digit of the X register 20 is sent to the mode detection section 22 for mode detection. The mode detection signal Dγ is output from the section 22. After the processor unit 12 executes the operation of one operation block (final operation block),
It is determined from the mode detection signal Dγ obtained by the mode detection unit 22 that a calculation result of 5/4 mode is to be obtained (step 8), and post-processing is executed to round off values less than or equal to the specified point (step 8). 13). The final arithmetic result data processed after the 5/4 mode is stored in the numerical data storage area of the X register 20 via the data input control circuit 19, and then sequentially sent to the display buffer register 23. is displayed on the display section 29, and is also transferred and stored in the designated address area of the data memory 24 together with the mode signal of the mode bit storage digit (step 10). In this way, when executing program calculations, mode calculations according to the designation of the round switch 14 and free mode calculations in which calculations are performed in free mode regardless of the designation of the round switch 14 can be executed, allowing highly accurate program calculations. The final result is obtained. In other words, to give an example, when obtaining the final result by rounding off to the second decimal place in a program calculation, conventionally, the round switch is set to 5/5 in advance of the program calculation.
4 mode and set the decimal point designation switch to the 2nd place, and the calculations for each calculation block are executed according to this setting, so x-5.61, x'64.55,! -5.
84, so the final calculation result z is 76.00.

On the other hand, as in the above embodiment, the calculation blocks 1, 2, 3
The calculation results of X, Xl, . x
= 5.6088, x' = 64.5498, f
=5.8353, so the final calculation result z is 7
5.99, which is a highly accurate value that is very close to the actual value of 75.993. Further, the results of each of the above calculations are stored at a predetermined location in the data memory 24 together with the post-processing mode code. Therefore, when reading the above calculation result to the calculation section for use in another calculation program later, the program must determine whether it is the calculation result obtained in floating mode or the calculation result performed in rounding mode. Since there is no need to assemble a program and a very simple program is required, the burden on the operator is greatly reduced. In the above embodiment, a free equal key is provided in the programmable key group, and it is explained that it is used only when setting a program.
The present invention is not limited to this, and when performing calculations without using a program, it is also possible to use the free equal key to execute free calculations without changing the round switch.

Further, in the above embodiment, the arithmetic unit (adder circuit), flag storage unit (flag register), etc. are provided in the processor unit 12, but the structure is not limited to this, and may be provided separately outside. In short, various applications are possible without departing from the gist of the invention. As detailed above, according to the present invention, when executing a program operation,
By being equipped with a function to obtain free mode calculation results regardless of the specified mode of the round switch, and a function to obtain mode calculation results according to the specified mode of the round switch,
For various calculations, it is possible to execute programmed calculations in the mode desired by the operator, obtain highly accurate program calculation results, and provide a versatile calculation control system for a programmable electronic calculator.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the embodiment. 11...keyboard, 12...-key input cover part, 13...flip-flop for mode specification, 14...round switch, 15...
... Decimal point designation switch, 16 ... Timing signal generation section, 17 ... Mode judgment circuit,
18...Encoder, 19...Data input control circuit, 20...X register, 21...
... Y register, 22 ... Mode inspection section,
23... Display buffer register, 24...
...Data memory, 25...Program memory, 26...Address register, 27...
...Instruction register, 28...Instruction judgment unit, 29...Display decoder, 30...
...Display section, 31...Selector switch, 32
. . . Judgment unit, N-Eq . . . Equal key judgment signal, F-Eq . . . Free equal key judgment signal.

Claims (1)

[Claims] 1. In a programmable electronic calculator equipped with a keyboard equipped with programmable keys, a decimal point designation switch, and a round switch, the keyboard is provided with a normal equals key and a specific equals key for floating arithmetic operations, and when executing program arithmetic operations, these means for determining which of the above-mentioned equal key settings the program content is in, prior to execution of the calculation, when the program content programmed by the operation of the equal key is read out and the step for executing the calculation is reached; Based on this determination result, when the calculation mode is based on a specific equal key setting, the mode specification code for floating calculation is set regardless of the specification of the round switch, and when the calculation mode is based on the normal equal key setting, the mode specification code is set for the round switch. and means for executing post-processing of the operation according to the mode specification code stored in the storage means after the program operation is executed. Arithmetic control method for electronic calculators.