JPS5931036A - Wire bonding stopping circuit - Google Patents

Wire bonding stopping circuit

Info

Publication number
JPS5931036A
JPS5931036A JP57140962A JP14096282A JPS5931036A JP S5931036 A JPS5931036 A JP S5931036A JP 57140962 A JP57140962 A JP 57140962A JP 14096282 A JP14096282 A JP 14096282A JP S5931036 A JPS5931036 A JP S5931036A
Authority
JP
Japan
Prior art keywords
circuit
wire
bonding
signal
gold wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57140962A
Other languages
Japanese (ja)
Other versions
JPS6361776B2 (en
Inventor
Kenji Mogi
健司 茂木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP57140962A priority Critical patent/JPS5931036A/en
Publication of JPS5931036A publication Critical patent/JPS5931036A/en
Publication of JPS6361776B2 publication Critical patent/JPS6361776B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/78268Discharge electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8503Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the bonding pad part of the title device from a mis-striking by a method wherein the gold wire short-circuit condition between the tip of a capillary and a spark electrode, and the condition that the sending out quantity of the gold wire from the tip of the capillary is small are detected, and action of a bonding arm is stopped. CONSTITUTION:The wire bonding stopping circuit is constructed of a discharge current detecting circuit 1, a delay circuit 2, a signal comparing circuit 3, and a prohibiting signal generating circuit 4. The discharge current detecting circuit 1 is the circuit to detect existence of a current to flow to a spark discharge circuit 5, and to convert the current into a pulse signal. The discharge current circuit 5 is constructed of a high voltage DC electric power source 6, a switch 7, a resistor 8, a wire clamping means 9, the gold wire 10, and the spark electrode 11. The gold wire short-circuit condition between the tip of the capillary 13 and the spark electrode 11, and the condition that the sending out quantity of the gold wire 10 from the tip of the capillary 11 is small are detected by the circuit thereof, and action of the bonding arm 14 is stopped.

Description

【発明の詳細な説明】 本発明はワイヤポンディング停止回路、特にスi+−り
放電を利用した自動ワイヤボンディング装置に使用する
ワイヤポンディング停止回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wire bonding stop circuit, and more particularly to a wire bonding stop circuit used in an automatic wire bonding apparatus that utilizes a switching discharge.

半導体集積回路(IC)部品の製造において、ICチッ
プのポンディングパッド部とリードフレームのビン端子
間を金属リード線で結線するボンディング作業の高速化
はIC部品の大量生産の為極めて重要な課題である。
In the production of semiconductor integrated circuit (IC) components, speeding up the bonding process, which connects the bonding pads of IC chips and the pin terminals of lead frames using metal lead wires, is an extremely important issue due to the mass production of IC components. be.

この問題を解決する為、近年自動ワイヤボンハング装置
がIC製造ラインに大量に採用されている。
To solve this problem, automatic wire bonding devices have recently been widely adopted in IC manufacturing lines.

このボンディング工程において金属リード線、例えば金
線の先端を熔融させて直径80〜110μmの金ボール
を形成することが不可欠であシ、この為金線とスパーク
電極間の電気的なスパーク放電をした金が−ル形成方法
が広〈実施されている。
In this bonding process, it is essential to melt the tip of a metal lead wire, such as a gold wire, to form a gold ball with a diameter of 80-110 μm, and for this purpose an electrical spark discharge between the gold wire and the spark electrode is required. Gold metal forming methods are widely practiced.

この金が−ルはICチップのがンディングバンド部との
熱圧着の為の表面積を大きくする事及びワイヤデンディ
ング時にパッド部への機械的な衝撃によりパッド部にク
ラックが発生することを防止する緩衝物として働く。
This gold metal increases the surface area for thermocompression bonding with the IC chip's bonding band and prevents cracks from occurring in the pad due to mechanical impact during wire ending. Acts as a buffer.

自動ワイヤデンディング装置の1ポンデイングザイクル
は下記の第1〜第3の主要工程からなる。
The 1-pond cycle of automatic wire ending equipment consists of the following first to third main steps.

(1)  ギヤピラリの先端から金線を所定の長さだけ
送出する。(金線送出工程) (2)  スi9−り電極を金線の先端に配置した後、
スパーク放電により金線の先端を溶かし所定径の金ボー
ルを形成す名。(金ボール形成工程) (3)  キャピラリをICチップのパッド部上に配置
した後、パッド部と金ボール部を熱圧着する。
(1) Feed out a specified length of gold wire from the tip of the gear pillar. (Gold wire delivery process) (2) After placing the silicone electrode at the tip of the gold wire,
A term used to melt the tip of a gold wire using spark discharge to form a gold ball of a specified diameter. (Gold ball forming step) (3) After placing the capillary on the pad portion of the IC chip, the pad portion and the gold ball portion are bonded by thermocompression.

(熱圧着工程) 従来のスパーク放電を利用した自動ワイヤボンディング
装置は02〜04秒/ボンディングサイクル程度のボン
ディング速度でボンディング作業を行っているが、キャ
ピラリからの金線の送出量が設定値以上に長く々りすぎ
スパーク電極と金線が短絡し金線の先端に金ボールが形
成されない事がしばしば生じた。
(Thermocompression bonding process) Conventional automatic wire bonding equipment using spark discharge performs bonding work at a bonding speed of about 02 to 04 seconds/bonding cycle, but the amount of gold wire sent out from the capillary exceeds the set value. The spark electrode was too long and the gold wire was short-circuited, and a gold ball was often not formed at the tip of the gold wire.

従来のボンディング装置では金線とスパーク電極の短絡
状態を検出する機能を有し々い為、金線の先端に所定径
の金が−ルが形成され々い状態で熱圧着工程を開始しギ
ヤピラリの先端が直接・ぐラド部を“空打ち″するので
、パッド部にクラックを生じさせながら連続してボンデ
ィング不良のIC部品を製造する問題があった。
Conventional bonding equipment has a function to detect short-circuit conditions between the gold wire and the spark electrode, so the thermocompression bonding process is started before a gold ring of a predetermined diameter is formed at the tip of the gold wire. Since the tip of the pad directly hits the pad part, there is a problem in that IC parts with continuous bonding defects are manufactured while cracking the pad part.

本発明はこれらの欠点を解決する為、金線がスノ9−り
電極に接触すると熱圧着工程を停止させるワイヤボンデ
ィング停止回路を提供するものである。
In order to overcome these drawbacks, the present invention provides a wire bonding stop circuit that stops the thermocompression bonding process when the gold wire comes into contact with the slit electrode.

以下第1〜第3図に示す本発明の実施例に従って詳細に
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed explanation will be given below according to the embodiments of the present invention shown in FIGS. 1 to 3.

本発明の実施例によるワイヤボンディング停止回路は放
電電流検出回路1と、遅延回路2と、信号比較回路3と
、禁止信号発生回路4から構成される。放電電流検出回
路1はス・ぐ−ク放電回路5に流れる電流の有無を検出
しパルス信号に変換する回路である。放電電流回路5は
高圧直流電源(例えば550V)6、スイッチ7、抵抗
8、ワイヤクランプ手段9、金線10、スーf−1電i
1ノから形成される。
The wire bonding stop circuit according to the embodiment of the present invention includes a discharge current detection circuit 1, a delay circuit 2, a signal comparison circuit 3, and an inhibition signal generation circuit 4. The discharge current detection circuit 1 is a circuit that detects the presence or absence of a current flowing through the spark discharge circuit 5 and converts it into a pulse signal. The discharge current circuit 5 includes a high voltage DC power supply (for example, 550 V) 6, a switch 7, a resistor 8, a wire clamping means 9, a gold wire 10,
It is formed from 1 no.

金線10はワイヤリール12から垂直(2軸方向)に送
出されキャピラリ13の針穴に案内される。キャピラリ
13はボンディングアーム14と一体となシ駆動回路1
5の出力信号(K)によりz軸方向に可動される。ワイ
ヤクランプ手段9は駆動回路16によシ時間的に金線1
0をクランプし、又放電回路5のスイッチとして作用す
る。
The gold wire 10 is fed out vertically (biaxially) from the wire reel 12 and guided into the needle hole of the capillary 13. The capillary 13 is integrated with the bonding arm 14 and the drive circuit 1
It is moved in the z-axis direction by the output signal (K) of No. 5. The wire clamping means 9 is connected to the gold wire 1 by the driving circuit 16.
0 and also acts as a switch for the discharge circuit 5.

ス・ぐ−ク電極11は駆動回路17によりz軸を中心と
して回転しキャピラリ13の直下に配置される。このキ
ャピラリ13の先端とスパーク電極11間のキョリt1
は正確に設定値(例えば1.0〜1.2 mm程度)に
決められる。
The spark electrode 11 is rotated about the z-axis by a drive circuit 17 and placed directly below the capillary 13. The gap t1 between the tip of this capillary 13 and the spark electrode 11
can be determined accurately to a set value (for example, about 1.0 to 1.2 mm).

放電電流検出回路lは例えばホトカノラ回路18と波形
整形回路19から構成される。ホトカゾラ回路18は発
光素子20と受光素子2ノを含み、抵抗8間に降下した
電圧によジ発元素子20が発光し受光素子21に入射さ
れる。波形整形回路19は例えばトランジスタ22及び
インー々−タ(5) 23を含み受光素子21から入力された信号を増巾及び
波形整形する。
The discharge current detection circuit 1 includes, for example, a photocanola circuit 18 and a waveform shaping circuit 19. The photocazolar circuit 18 includes a light emitting element 20 and a light receiving element 2. The voltage dropped across the resistor 8 causes the light emitting element 20 to emit light, which is incident on the light receiving element 21. The waveform shaping circuit 19 includes, for example, a transistor 22 and an interface (5) 23, and amplifies and shapes the waveform of the signal input from the light receiving element 21.

遅延回路2は各々時定数回路26.27を有する単安定
マルチバイブレータ回路24.25から形成され、イン
バータ23から出力された信号によりこの出力信号のパ
ルス中に相当する時間Tlを経過後、パルス信号を出力
する。時定数回路26はインバータ23から出力される
出力信号の・ぐルス巾以上の時定数T2を有する。
The delay circuit 2 is formed by monostable multivibrator circuits 24, 25, each having a time constant circuit 26, 27, and which, by the signal output from the inverter 23, generates a pulse signal after a corresponding time Tl during the pulse of this output signal. Output. The time constant circuit 26 has a time constant T2 that is equal to or larger than the width of the output signal output from the inverter 23.

信号比較回路3はインバータ28とAND論理回路29
から構成され、インバータ23から所定のパルス中を有
するパルス信号が出力されるとi+ルス信号を出力する
The signal comparison circuit 3 includes an inverter 28 and an AND logic circuit 29
When the inverter 23 outputs a pulse signal having a predetermined pulse, it outputs an i+ pulse signal.

禁止信号発生回路4はJKフリッゾフロッゾ30と、ゲ
ート回路31と遅延回路32から構成され、比較回路3
の出力信号に応答してキャピラリ13の?ンディング動
作を停止させる禁止信号を出力する。JKフリノプフロ
ッゾ30は遅延回路32を通してタイミング信号発生回
路33からタイミング信号を入力され定期的にb出力端
子を゛HIIレペ(6) ルにリセット祿る。
The prohibition signal generation circuit 4 is composed of a JK Frizzo Frozzo 30, a gate circuit 31, a delay circuit 32, and a comparison circuit 3.
? of capillary 13 in response to the output signal of Outputs a prohibition signal to stop the landing operation. The JK Frinoproflozzo 30 receives a timing signal from the timing signal generation circuit 33 through the delay circuit 32, and periodically resets the b output terminal to the ``HII level (6)''.

次に本発明の実施例による動作を第2図のタイミング図
を参照して説明する。
Next, the operation according to the embodiment of the present invention will be explained with reference to the timing diagram of FIG.

まずタイミング信号発生回路33からタイミング信号(
A)が出力されると駆動回路16によりワイヤクランプ
手段9が金線10をクランプする。
First, a timing signal (
When A) is output, the drive circuit 16 causes the wire clamping means 9 to clamp the gold wire 10.

(第2図(A))次にタイミング信号発生回路33から
タイミング信号(B)が出力されると駆動回路17によ
りスパーク電極11をキャピラリ13の直下に配置する
。(第2図(B))通常ポンディングワイヤは直径20
〜30μmの金線10が使用され、又キャピラリ13の
先端とス・ぐ−ク電極11間t1は例えば1〜2mm1
度に設定される。又放電回路5の直流電源6が550v
程度であると金線10の先端とスiZ−り電極11間の
スパーク間隙t3は例えば015〜0.2 mm程度に
設定される。
(FIG. 2(A)) Next, when the timing signal (B) is output from the timing signal generating circuit 33, the spark electrode 11 is placed directly below the capillary 13 by the drive circuit 17. (Figure 2 (B)) Normally, the diameter of the bonding wire is 20 mm.
~30 μm gold wire 10 is used, and the distance t1 between the tip of the capillary 13 and the spark electrode 11 is, for example, 1~2 mm1.
set at the same time. Also, the DC power supply 6 of the discharge circuit 5 is 550V.
For example, the spark gap t3 between the tip of the gold wire 10 and the sliding electrode 11 is set to about 0.15 to 0.2 mm.

JKフリップフロツノ30は、前ボンディングサイクル
時にタイミング信号発生回路33のタイミング信号(C
)により、リセットされるためQ出力端子は°°H″レ
ベル状態保持されている。又、AND論理回路34の一
方の入力端子は次のタイミング信号が出力されるまでN
 LI+レベル状態に保持されている。
The JK flip-flop 30 receives the timing signal (C) of the timing signal generation circuit 33 during the previous bonding cycle.
), the Q output terminal is held at the °°H'' level state. Also, one input terminal of the AND logic circuit 34 is held at the N level until the next timing signal is output.
It is maintained at LI+ level state.

次にタイミング信号発生回路33よりタイミング信号(
E)が出力されるとスイッチ7が例えば20〜30ミリ
秒間閉じ放電回路5が完成する。
Next, a timing signal (
When E) is output, the switch 7 is closed for, for example, 20 to 30 milliseconds, and the discharge circuit 5 is completed.

これにより間隙t3にスパーク放電が発生し金線10の
先端を熔融させる。熔融した金線はポール10aとなり
表面張力によシスパーク放電が持続し々い高さ72  
(例えば約0.5 rnm )まで上昇して停止する。
This generates spark discharge in the gap t3, melting the tip of the gold wire 10. The molten gold wire becomes the pole 10a at a height of 72 at which the cis-spark discharge is sustained due to surface tension.
(for example, about 0.5 rnm) and then stops.

この様に正常なス・や−ク状態であれば、波形整形回路
19は所定期間TI (例えば25〜30ミリ秒) ”
H”レベルの信号を出力する。(第2図(F)) イン・ぐ−夕23から出力された出力信号は遅延回路2
に入力され、期間Tl より長く、且つスイッチ7の制
御信号(E)より短い期間である時間T2後にパルス信
号(G)を出力する。(第2図(G))このパルス信号
(G)と(F)の状態が比較され、波形整形回路19の
出力信号(F)のノfルス巾が正常のスパーク期間TI
以内であれば”H11レベル信号を出力する。(第2図
(H))  JKフリツゾフロツプ30に゛HIIレベ
ル信号が入力されるとQ出力端子の出力信号(I)は゛
°L゛レベル状態に変化しAND論理回路34に入力さ
れる。(第2図(I))従ってゲート回路34の出力信
号(J)は”L“ルベル9駆動回路15は正常動作でが
ンデイングアーム14を駆動させる。(第2図(J)(
K))従ってパッド部への熱圧着工程が実行される。
In this normal spark state, the waveform shaping circuit 19 operates for a predetermined period TI (for example, 25 to 30 milliseconds).
The output signal from the in/output 23 is outputted from the delay circuit 2. (Fig. 2 (F))
The pulse signal (G) is output after a time T2 which is longer than the period Tl and shorter than the control signal (E) of the switch 7. (Fig. 2 (G)) The states of these pulse signals (G) and (F) are compared, and the spark period TI during which the nof width of the output signal (F) of the waveform shaping circuit 19 is normal
If it is within the range, the H11 level signal is output (Fig. 2 (H)) When the HII level signal is input to the JK fritz flop 30, the output signal (I) of the Q output terminal changes to the L level state. The output signal (J) of the gate circuit 34 is "L" and is input to the AND logic circuit 34 (FIG. 2(I)). (Figure 2 (J) (
K)) Therefore, a thermocompression bonding process to the pad portion is performed.

一方スイッチ信号(E)のH′”レベル中にタイミング
信号発生回路33よシタイミング信号(C)が遅延回路
32に入力され所定の時間経過後JKフリップフロップ
300同出力端子はH”レベルにリセットされる。(第
2図(C) (D))次に金線10がスパーク電極1ノ
に接触した場合を考慮すると、スイッチ7のオン期間中
放電回路5に短絡電流が流れる。従って波形整形回路1
9の出力信号(F)はT1期間以上に”H′ルベル信号
を出力する。(第2図(F)点線波形)遅延回路2は信
号が入力されると常にT2期間後ノリレス(9) 信号を出力する。この為比較回路3はスイッチ信号(E
)が”H”レベル期間中″L++レベル状態に保持され
従ってJKフリッゾフロップ回路30のQ出力端子の状
態も°゛H°”レベルに保持される。
On the other hand, while the switch signal (E) is at H''' level, the timing signal (C) from the timing signal generation circuit 33 is input to the delay circuit 32, and after a predetermined period of time, the output terminal of the JK flip-flop 300 is reset to H' level. be done. (FIGS. 2C and 2D) Next, considering the case where the gold wire 10 comes into contact with the spark electrode 1, a short circuit current flows through the discharge circuit 5 while the switch 7 is on. Therefore, waveform shaping circuit 1
The output signal (F) of 9 outputs a "H" level signal for more than the T1 period. (Figure 2 (F) dotted line waveform) When a signal is input, the delay circuit 2 always outputs a signal after the T2 period (9). Therefore, the comparator circuit 3 outputs the switch signal (E
) is held at the ``L++'' level during the ``H'' level period, and accordingly, the state of the Q output terminal of the JK frizzo flop circuit 30 is also held at the ``H'' level.

次にタイミング信号発生回路33より AND論理回路
34の一方の入力端子にIIHI+レベル信号が入力さ
れるので、AND論理回路34よシ駆動回路15に゛H
IIレベルの禁止信号が出力される。従ってボンディン
グアーム14は動作を停止し、IC部品のi<? ラド
部への熱圧着工程が完全に防止される。駆動回路15は
解除信号(0)が入力されるまで状態を保持する。AN
D論理回路34が禁止信号を出力した後一方の入力端子
は″LITレベル状態になり、再びAND論理回路34
の出力端子はt+Luレベル状態に復帰する。
Next, the timing signal generation circuit 33 inputs the IIHI+ level signal to one input terminal of the AND logic circuit 34, so the AND logic circuit 34 and the drive circuit 15 input the IIHI+ level signal.
A II level prohibition signal is output. Therefore, the bonding arm 14 stops operating, and the i<? The thermocompression bonding process to the radius part is completely prevented. The drive circuit 15 maintains its state until a release signal (0) is input. AN
After the D logic circuit 34 outputs the prohibition signal, one input terminal becomes the "LIT" level state, and the AND logic circuit 34 again
The output terminal returns to the t+Lu level state.

次に金flJ10の先端とスパーク電極11間が22以
上である場合を考慮すると、スイッチ7のオン期間中ス
パーク放電が発生せず放電回路5に放電電流が流れない
。波形整形回路19の出力信号(F’)は″′L″ルベ
ル状態に保持され、遅延回路2の出力(10) 信号(G)も°゛L″L″レベル状態される。従って比
較回路3の出力信号(H)もII LI+レベル状態と
なり、JKフリッゾフロツゾ30のQ信号の6■”ルベ
ル状態を変化させ々い。その後タイミング信号発生回路
33からAND論理回路34の一方の入力端子にタイミ
ング信号(C)が入力されるとAND論理回路34は駆
動回路15に“H11レベルの禁止信号を出力し、ボン
ディングアーム14の動作を停止させる。その後遅延回
路32からリセット信号(D)が出力され更にJKフリ
ップフロッゾ30のQ出力端子を゛°H′ルベルのまま
保持し次のボンディングサイクルにクロック端子CKに
信号が入力されるのを待機する。
Next, considering the case where the distance between the tip of the gold flJ10 and the spark electrode 11 is 22 or more, no spark discharge occurs during the ON period of the switch 7, and no discharge current flows through the discharge circuit 5. The output signal (F') of the waveform shaping circuit 19 is held at the "L" level, and the output signal (10) (G) of the delay circuit 2 is also held at the "L" level. Therefore, the output signal (H) of the comparator circuit 3 also becomes the II LI+ level state, which causes the Q signal of the JK Frizzo 30 to change the 6'' level level.Then, one input from the timing signal generation circuit 33 to the AND logic circuit 34. When the timing signal (C) is input to the terminal, the AND logic circuit 34 outputs an inhibit signal of "H11 level" to the drive circuit 15, and stops the operation of the bonding arm 14. After that, a reset signal (D) is outputted from the delay circuit 32, and the Q output terminal of the JK flip flop 30 is held at the '°H' level, waiting for a signal to be input to the clock terminal CK in the next bonding cycle. .

尚本発明の実施例において各タイミング信号をディジタ
ル回路によるタイミング信号発生回路33を考慮したが
、回転シャフトに取付けられたスリット付の制御円盤と
検出器を有する機械的な手段で発生する事も可能である
In the embodiment of the present invention, each timing signal is generated using a timing signal generation circuit 33 using a digital circuit, but it is also possible to generate each timing signal by mechanical means having a control disk with a slit and a detector attached to a rotating shaft. It is.

以上説明した様に本発明によるワイヤがンデイング停止
回路はキャピラリの先端とスノ4−り電極間での金線短
絡状態及びキャピラリの先端からの金線の送出量が少い
状態を同様に検出してボンディングアーム動作を停止さ
せるので、キャピラリの先端で半導体電子部品のボンデ
ィングパット部ヲ直接°゛空打ち″する事が完全に防止
される。
As explained above, the wire winding stop circuit according to the present invention can similarly detect a gold wire short-circuit condition between the capillary tip and the snowdrop electrode and a condition in which the amount of gold wire delivered from the capillary tip is small. Since the operation of the bonding arm is stopped, it is completely prevented that the tip of the capillary directly hits the bonding pad portion of the semiconductor electronic component.

従って金線の先端に金ボールが形成されない状態で自動
ボンディング動作が実行され、連続して不良品IC部品
が製造される事故が解消される。本発明によるワイヤボ
ンディング停止回路は高速度で動作する完全自動ボンデ
ィング装置に使用して、非常に高い製造歩留でワイヤボ
ンディング作業を可能にするものである。
Therefore, the automatic bonding operation is performed without a gold ball being formed at the tip of the gold wire, and the accident of continuously manufacturing defective IC parts is eliminated. The wire bonding stop circuit according to the invention can be used in fully automatic bonding equipment operating at high speeds to enable wire bonding operations with very high manufacturing yields.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるワイヤボンディング停止回路の実
施例である。第2図は本発明の実施例の為の動作タイミ
ング図である。 1・・・放電電流検出回路、2・・・遅延回路、3・・
・比較回路、4・・・禁止信号発生回路。 手続補正書(睦) 昭和 腎・1・14 日 特許庁長官 殿 1、事件の表示 昭和57年 特 許  願第140962号2、発明の
名称 ワイヤポンディング停止回路 3、補正をする者 事件との関係       特 許 出 願 人任 所
(〒105)  東京都港区虎ノ門1丁目7番12号住
 所(〒105)  東京都港区虎ノ門1丁目7番12
号5、補正の対象 明細書中「発明の詳細な説明」の欄 191−
FIG. 1 is an embodiment of a wire bonding stop circuit according to the present invention. FIG. 2 is an operational timing diagram for an embodiment of the present invention. 1... Discharge current detection circuit, 2... Delay circuit, 3...
- Comparison circuit, 4... prohibition signal generation circuit. Procedural Amendment (Mutsu) Showa Renki January 14th, Director General of the Patent Office, 1, Indication of Case, 1982 Patent Application No. 140962, 2, Title of Invention: Wire Ponting Stop Circuit 3, Person Making Amendment Related Patent Application Personnel Office (105) 1-7-12 Toranomon, Minato-ku, Tokyo Address (105) 1-7-12 Toranomon, Minato-ku, Tokyo
No. 5, “Detailed Description of the Invention” column 191- in the specification subject to amendment

Claims (3)

【特許請求の範囲】[Claims] (1)  ス・ぐ−ク電極とボンディング用金属線間に
放電電流が流れると放電期間に相当する第1の・母ルス
信号を出力する放電電流検出回路と、前記第1パルス信
号の発生時から所定の時間経過後第2のパルス信号を出
力する遅延回路と、前記第1パルス信号のパルス巾と前
記遅延時間を比較する比較回路と、前記比較回路の出力
信号に応答して半導体素子の・ぐラド部と前記ボンディ
ング用金属線よ との熱圧着工程を停止させる信号を出力する禁浴信号発
生回路を含むワイヤポンディング停止回路。
(1) A discharge current detection circuit that outputs a first pulse signal corresponding to the discharge period when a discharge current flows between the spark electrode and the bonding metal wire, and when the first pulse signal is generated. a delay circuit that outputs a second pulse signal after a predetermined period of time has elapsed; a comparison circuit that compares the pulse width of the first pulse signal with the delay time; - A wire bonding stop circuit including a bath prohibition signal generation circuit that outputs a signal to stop the thermocompression bonding process between the grading portion and the bonding metal wire.
(2)  前記遅延回路が複数の単安定マルチバイブレ
ータからなる事を特徴とする特許請求の範囲第1項記載
のワイヤデンディング、停止回路。
(2) The wire ending and stopping circuit according to claim 1, wherein the delay circuit comprises a plurality of monostable multivibrators.
(3)  前記遅延時間が3ミリ秒以上である事を特徴
とする特許請求の範囲第1項記載のワイヤポンディング
停止回路。
(3) The wire pounding stop circuit according to claim 1, wherein the delay time is 3 milliseconds or more.
JP57140962A 1982-08-16 1982-08-16 Wire bonding stopping circuit Granted JPS5931036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57140962A JPS5931036A (en) 1982-08-16 1982-08-16 Wire bonding stopping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57140962A JPS5931036A (en) 1982-08-16 1982-08-16 Wire bonding stopping circuit

Publications (2)

Publication Number Publication Date
JPS5931036A true JPS5931036A (en) 1984-02-18
JPS6361776B2 JPS6361776B2 (en) 1988-11-30

Family

ID=15280860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57140962A Granted JPS5931036A (en) 1982-08-16 1982-08-16 Wire bonding stopping circuit

Country Status (1)

Country Link
JP (1) JPS5931036A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548377Y2 (en) * 1989-09-26 1993-12-24

Also Published As

Publication number Publication date
JPS6361776B2 (en) 1988-11-30

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