JPS5930342B2 - Transmission/reception switching method of transmitting/receiving shared code decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission/reception switching system for a shared code decoder in which a DA converter as a local decoder of an encoder is shared in time division as a DA converter of a decoder. .

A DA converter as a local decoder is used as an encoder for converting an analog signal into a PCM signal 12 and transmitting the signal, and this DA converter is used as a decoder for converting a received PCM signal into an analog signal. A common code decoder for transmission and reception is used as a DA converter.

For example, as shown in FIG.
P3, hold capacitor C to sampling switch 8
Consists of 1 comparator COMP, DA converter DAC,
The analog signal applied to the input terminal AIN is sampled by a sampling switch 8v operated by a sampling lock and stored in a hold capacitor C.

Since the DA converter DAC operates as a local decoder, the terminal on the operational amplifier AMPa side is disconnected, and the terminal on the comparator COMP
The sampled and held value and the DA converter D
The output of the AC is compared with the output of the PC from the output terminal POUT.
M signal is output.

Also, the received PCM signal applied to the input terminal PIN is applied to the DA converter DAC, and at this time, the terminal that operates as a local decoder is disconnected, and the output of the DA converter DAC is applied to the operational amplifier AMP3. , an analog signal is output from the output terminal AOUT.

In such a transmitting/receiving shared code decoder, transmission and reception are switched asynchronously, and therefore, regardless of the sampling state in the sampling and holding circuit, the D
The A converter DAC was used by switching between a local decoder for transmission and an ODA converter for reception.

In such a conventional transmitting/receiving shared code decoder, when switching between transmitting and receiving is performed immediately before the sampling switch 8■ changes from the on state to the off state, that is, immediately before changing from the sampling mode to the hold mode, the operational amplifier At the input terminal of AMP3, a sudden signal change from zero to a signal corresponding to the received PCM or vice versa appears, and this signal change affects the operational amplifiers AMP1 and AMP2 on the transmitting side through the power supply or ground, The hold capacitor C in the hold mode has a drawback that a value different from the sampled value of the input analog signal is held, which causes an error.

The present invention has been made to improve the above-mentioned drawbacks, and its purpose is to prohibit switching between transmission and reception immediately before changing from sampling mode to hold mode, so as to prevent errors from occurring in the encoding of input analog signals. The goal is to

Examples will be described in detail below.

FIG. 2 is a block diagram of an embodiment of the present invention, in which O8C
is an oscillator 1 that generates a basic transmission clock. DVI.

DV2 is a frequency divider, TM is a timing extraction circuit that extracts timing from the received PCM signal, BF is a buffer register that adds the received PCM signal, NSY is an asynchronous absorption circuit,
LST is a logic startup circuit, LM is a memory logic circuit that sequentially accumulates judgment results in cyclic AD conversion and outputs the next comparison signal, SEL is a selector, and DAC is a DA.
Converter, COMP is a comparator, SH is a sample and hold circuit including a sampling switch, a hold capacitor, etc., OAMP is an operational amplifier, PIN is an input terminal for the received PCM signal, POUT is an output terminal for the transmitted PCM signal, AIN
is an analog signal input terminal, and AOUT is an analog signal output terminal.

The frequency divider Dv1 divides the transmission basic clock and outputs a signal PRT.
, SHG, 5HGP, and BCLKSA, and the frequency divider DV2 divides the received basic clock from the timing extraction circuit TM to output signals PRTP and 5TRES.

Outputs 5TRESP.

The signal SHG is a sampling signal, and the asynchronous absorption circuit NS
Y, is added to the logic startup circuit LST and sample hold circuit SH.

Also, the asynchronous absorption circuit NSY receives signals SHG and 5HGP.

Transmission/reception switching signal 5RC by 5TRES and 5TRESP
NT is generated and applied as a switching control signal to the logic startup circuit LST, memory logic circuit LM, selector SEL, and DA converter DAC.

The selector SEL receives the received PCM signal converted into a parallel signal by the buffer register BF and the memory logic circuit LM.
This selects one of the output signals and applies it to the DA converter DAC.

FIGS. 3a and 3b are explanatory diagrams of the operation, in which the signal 5HGP is a signal that precedes the sampling signal SHG by, for example, 1 μs, and similarly the signal 5TRESP is a signal that precedes the signal 5TRES by a time t.

Further, FFI is a signal with a pulse width of time t, and 5RCNT is a transmission/reception switching signal from the asynchronous absorption circuit NSY.

When the sampling signal SHG is at a high level, that is, "1", the sampling switch of the sample-and-hold circuit SH is on and the sampling mode is set; when the sampling signal SHG is at a low level, that is, "0", the sampling switch is off and the sampling mode is set;
Reception when transmission/reception switching signal 5RCNT is 019+, “0”
'', it is determined whether there is a request for switching between transmission and reception within the time t1 from the falling point of the signal 5HGP to the falling point of the sampling signal SHG, that is, the time immediately before changing from the sampling mode to the hold mode. to monitor.

As shown in FIG. 3a, if the signal 5TRESP is "1" and the signal 5TRES is 0" after the fall of the signal 5HGP, it is identified that there is a request for switching between transmitting and receiving within the specified time. Transmission/reception switching by request is prohibited within the specified time, and by setting the logical sum of the signal 5TRES and the signal FFI as the transmission/reception switching signal 5RCNT,
It is possible to switch from transmission to reception while avoiding the time t immediately before changing from sampling mode to hold mode.

Further, as shown in FIG. 3, at the falling edge of the signal 5HGP, the signal 5TRES becomes (Bin, and the signal 5TRESP becomes
'', it is identified that there is a request for transmission/reception switching within the specified time, so by setting the logical sum of the signal 5TRES and the signal FF1 as the transmission/reception switching signal R8CNT, the switching from reception to transmission is performed as a sampling signal. It can be performed simultaneously with the fall of SHG.

FIG. 4 is a block diagram of the main part of the asynchronous absorption circuit NSY, in which the signal 5HGP is connected to the clock terminal CLK of the flip-flop FF, and the sampling signal SHG is connected to the clear terminal CL.
The output of the exclusive OR circuit EXOR of the signal 5TRES and the signal 5TRESP is added to the data terminal of A, and the output of the Q terminal of the flip-flop FF becomes either the signal 5TRES or 5TRESP within a certain period of time. When one is “1” or “0” and the other is “uO” or “1”, the signal FFI shown in FIG. 3a is output, and the signal 5T
The output of the logical sum with RES becomes the transmission/reception switching signal 5RCNT via the logical sum circuit OR.

When the transmission/reception switching signal 5RCNTIJ'-61'' is selected, the selector SEL transfers the signal from the buffer register BF to DA.
In addition to the converter DAC, the DA converter DAC has an operational amplifier O
Since the conversion output is added to AMP, an analog signal obtained by decoding the received PCM signal is output from the output terminal AOUT.

Moreover, when the transmission/reception switching signal 5RCNT is αO'', the selector SET outputs the output of the memory logic circuit LM, or the output of the A converter DAC, as well as the conversion output of the DA converter DAO, to the comparator C.
In addition to OMP, analog signal is used as sampling signal SHG
The comparator COMP compares the sampled and held output of the sample hold circuit SH with the output of the sample hold circuit SH, and the comparison output is made into a PCM signal and is applied to the memory logic circuit LM.

The signal BCLKSA is the clock for the memory logic circuit LM, and this signal is the transmission/reception switching signal 5RCNT.
It is stopped when fJ''-a1'' is reached.

In addition, the logic starting circuit LST receives the transmission/reception switching signal 5RCN.
When T becomes "o", the signal PRT.

An activation signal for the memory logic circuit LM is added using PRTP and SHG to perform initial settings for AD conversion.

Through such operations, the analog signal is converted into a PCM signal and transmitted.

As explained above, the present invention prohibits switching between transmitting and receiving in the transmitting/receiving shared code decoder during a certain period immediately before the sample and hold circuit SH changes from the sampling mode to the hold mode. Therefore, the transmission/reception switching point does not occur immediately before the hold mode (and the sample-and-hold circuit SH is not affected by sudden changes in the signal on the receiving side, making it possible to perform accurate code conversion.

Further, the configuration for this purpose can be realized by adding a simple configuration as shown in FIG. 4, for example.

Therefore, the clock on the transmitting side and the clock on the receiving side are asynchronous, making it possible to eliminate the adverse effects of switching when the DA converter, DA converter, and DAC are used for both transmission and reception in a time-division manner, and improve the reliability of encoding. .

[Brief explanation of drawings]

Fig. 1 is a block diagram of a transmitting/receiving code decoder, Fig. 2 is a block diagram of an embodiment of the present invention, Figs. It is a line diagram. DVl and DV2 are frequency dividers, TM is a timing extraction circuit,
NSY is an asynchronous absorption circuit, LST is a logic startup circuit,
BF is a buffer register, LM is a memory logic circuit,
SEL is a selector, DAC is a DA converter, COMP is a comparator, SH is a sample hold circuit, PIN is a PCM signal input terminal, POUT is a PCM signal output terminal, AI
N is an analog signal input terminal, and AOUT is an analog signal output terminal.

Claims (1)

[Claims] 1. In a transmitting/receiving code decoder in which the transmitting side clock and the receiving side clock are asynchronous and the DA converter is shared in a time division manner as a local decoder for decoding and a local decoder for encoding, the sampling mode of the sample and hold circuit A transmitting/receiving switching method for a transmitting/receiving shared code decoder, characterized in that switching between transmitting and receiving is prohibited during a certain period immediately before changing to a hold mode.