JPS5929867U - sink insert circuit - Google Patents

sink insert circuit

Info

Publication number
JPS5929867U
JPS5929867U JP12456582U JP12456582U JPS5929867U JP S5929867 U JPS5929867 U JP S5929867U JP 12456582 U JP12456582 U JP 12456582U JP 12456582 U JP12456582 U JP 12456582U JP S5929867 U JPS5929867 U JP S5929867U
Authority
JP
Japan
Prior art keywords
count value
gate signal
signal
synchronization signal
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12456582U
Other languages
Japanese (ja)
Inventor
草野 諭
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP12456582U priority Critical patent/JPS5929867U/en
Publication of JPS5929867U publication Critical patent/JPS5929867U/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を示す回路ブロック図、第
2図は、第1図の回路動作を示すタイミングチャートを
示す図、第3図は、本考案の他の実施例を示す回路ブロ
ック図、第4図は、第3図の回路動作を示すタイミング
チャートを示す図である。 主要部分の符号の説明、1,7・・・・・・LPF、 
2・・・・・・立下りエツジ検出回路、3・・・・・・
カウンタ、4・・・・・・RSフリップフロップ、5,
6・・四半安定マルチ、G1. G4. G5・・・・
・・NORゲート、G6・・・・・・ANDゲー ト′
。 ′iL3 図 町’j”)4−  田
FIG. 1 is a circuit block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart showing the circuit operation of FIG. 1, and FIG. 3 is a diagram showing another embodiment of the present invention. The circuit block diagram in FIG. 4 is a timing chart showing the operation of the circuit in FIG. 3. Explanation of symbols of main parts, 1, 7...LPF,
2...Falling edge detection circuit, 3...
Counter, 4...RS flip-flop, 5,
6. Quarter stable multi, G1. G4. G5...
...NOR gate, G6...AND gate'
. 'iL3 Figure town'j'')4- 田

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)記録媒体から再生されたビデオ信号から分離して
得られた少なくとも垂直同期信号に対応する期間に亘っ
て存在するゲート信号を発生するゲート信号発生手段を
含み、前記ゲート信号が存在しないとき基準水平同期信
号に同期した信号を出力するようにしたことを特徴とす
るシンクインサート回路。
(1) Including a gate signal generating means for generating a gate signal that exists over a period corresponding to at least a vertical synchronization signal obtained separately from a video signal reproduced from a recording medium, and when the gate signal does not exist. A sink insert circuit characterized in that it outputs a signal synchronized with a reference horizontal synchronization signal.
(2)前記ゲート信号発生手段は、前記垂直同期信号の
発生時に計数値がリセットされかつ前記基準水平同期信
号によって計数値が変化するカウンターと、前記カウン
タの計数値が第1所定値に達したときセット状態となり
かつ前記カウンタの計数値が第2所定値に達したときリ
セット状態となる記憶手段とからなり、前記記憶手段の
出力を前記ゲート信号として出力することを特徴とする
実用新案登録請求の範囲第1項記載   ゛のシンクイ
ンサート回路。   ”
(2) The gate signal generating means includes a counter whose count value is reset when the vertical synchronization signal is generated and whose count value changes according to the reference horizontal synchronization signal, and a counter whose count value reaches a first predetermined value. a storage means that enters a set state when the count value of the counter reaches a second predetermined value, and a storage means that enters a reset state when the count value of the counter reaches a second predetermined value, and outputs an output of the storage means as the gate signal. Sink insert circuit described in item 1 of the range. ”
JP12456582U 1982-08-18 1982-08-18 sink insert circuit Pending JPS5929867U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12456582U JPS5929867U (en) 1982-08-18 1982-08-18 sink insert circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12456582U JPS5929867U (en) 1982-08-18 1982-08-18 sink insert circuit

Publications (1)

Publication Number Publication Date
JPS5929867U true JPS5929867U (en) 1984-02-24

Family

ID=30283907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12456582U Pending JPS5929867U (en) 1982-08-18 1982-08-18 sink insert circuit

Country Status (1)

Country Link
JP (1) JPS5929867U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137523U (en) * 1985-02-18 1986-08-26

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5498523A (en) * 1978-01-20 1979-08-03 Victor Co Of Japan Ltd Synchronizer between reproduced video signal from video disc and other video signals

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5498523A (en) * 1978-01-20 1979-08-03 Victor Co Of Japan Ltd Synchronizer between reproduced video signal from video disc and other video signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137523U (en) * 1985-02-18 1986-08-26
JPH0312658Y2 (en) * 1985-02-18 1991-03-25

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