JPS5925532A - Charging circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charging circuit using a transistor inverter.

Figure 1 shows a general circuit example of a traditional inverter type charging circuit, which mainly consists of an inverter (2) that supplies AC power (1), and a secondary winding L2 output of this inverter (2) that rectifies the output. A secondary output rectifier circuit (
4), and the inverter (2) is composed of a switch starting circuit (5), a switch section (6), and a power conversion section (7). Also, R1-R4 are for starting shooting, respectively.
Resistors for base current limiting, main transistor Tr1 collector current limiting, and primary winding L1 back electromotive force absorption, 01~
C3 are for power supply smoothing, primary windings 1 and 1 back electromotive force absorption, and base circuit] sigencers, and DID2 is for 1
This is a diode for absorbing back electromotive force in the next winding Ll and for high frequency rectification. The windings L3 are primary to tertiary windings, respectively, and these constitute an oscillation transmission.

Thus, in the conventional example circuit shown in FIG. 1, when the AC power supply (1) is turned on, the base current is supplied to the main transistor Trl through the resistor R1, the main L resistor Tr turns on, and the collector current IcK increases by 1. A voltage of V=L, 7H is generated in the secondary winding L1i, and this is positively fed back to the tertiary winding L3, thereby further turning on the main transistor Trl. Then, when the collector current flows with respect to the base current IB of the main transistor Tr1 until Ic=hyz4B, the current change in the primary winding L1 disappears,
As a result, the polarity of the voltage across the primary winding L1 is instantly reversed, the potential is fed back to the tertiary winding L3, and the main transistor Try is reverse biased and turned off. At this time, the energy of the primary winding L1 is taken out from the secondary winding L2 and rectified by the diode D2 to charge the rechargeable battery. After this, the base potential of the main transistor Tr1 rises across the resistor R1, and when this base potential reaches a predetermined voltage, a base current flows to repeat the above operation and continue the oscillation operation.

FIG. 2 shows the waveforms of various parts of the above-mentioned operation, in which (a) shows the collector-emitter voltage of the main transistor Try, (
(b) shows the collector current, and (C) shows the waveforms of the rectified current by the diode D2.

However, in the conventional circuit as described above, the circuit design is made according to the voltage rating of the current power supply (1), so when the power supply voltage differs from country to country, it is difficult to adapt to the power supply voltage. In addition to the problem that it is difficult to miniaturize the device, there is also the problem that the equipment may be damaged due to incorrect use or switching errors in the case of a switchable power supply voltage type. 00 V and AC2
Assuming two power supply voltages of 40V, in order to satisfy the stress on the main transistor Trl, it is necessary to use a large rated main transistor [r1], and a large and expensive main transistor Tr1 must be used. There has been a problem in that it is difficult to downsize the charger because it is necessary to use a charger.

The present invention has been provided in view of the above-mentioned points, and provides a charging circuit that can be used in common in response to changes in power supply voltage in each country, which always reliably connects the main transistor.
It is an object of the present invention to provide a charging circuit that can limit the collector current to a permissible value or less, thereby eliminating the risk of destroying the main transistor.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 3 shows a circuit according to an embodiment of the present invention, which includes a power supply circuit (8) that rectifies and smoothes the output of the fourth winding L4 of the oscillation trasis, and an inverter (2) that operates with the output of this power supply circuit (8). An oscillation frequency control circuit (9) that synchronizes the oscillation frequency to make the oscillation frequency constant regardless of the power supply voltage, and an oscillation frequency control circuit (9) that is also operated by the output of the power supply circuit (8) and controls the voltage across the resistor R4 and the reference voltage generation circuit flo+ output. In comparison, a collector current control circuit (river) which grounds the base of the main transistor Tr1 is added to the conventional circuit shown in FIG. A peak collector current limiting circuit 02) is added to ground the base of the main transistor Tr1, and in this embodiment circuit of FIG.
The collector current of the transistor Tr1 is detected. Here, the power supply circuit (8) includes the quaternary winding aL4 and the diode D.
3 and a smoothing capacitor C5. The oscillation frequency control circuit (9) is composed of an IC-based oscillator 03), an external resistor R5, and a capacitor C4, and its output turns on and off the transistor Tr3', and the Igo Burke (2) Synchronize. The collector current control circuit (11) is a cosciparator (11) which has one input as the output of the reference voltage generation circuit (10) consisting of a resistor R6 and a Zener diode D6 and the other input as the terminal voltage of the resistor R3.
14), and by turning on the transistor Tr3 with the output of this comparator (14), when the collector current of the main transistor Trl exceeds a predetermined value, the base of the main transistor Trx is grounded. The peak collector current limiting circuit (12) consists of a transistor Trp in which series diodes D4 and D5 are connected in series, and by connecting the base to one end of the resistor R3, the voltage across the resistor R3 is detected by the transistor Tr2. However, the base of the main transistor Trx is grounded.

Thus, the circuit of the embodiment shown in FIG. 3 operates as follows. That is, at time t-=O, when a base current is passed through the resistor R1 to the base of the main transistor Tr1,
This main 1-run resistor Try turns on and the collector current I
C flows into its primary winding L, v ,, :==
L+, 7+□!・・・・・・・・・
(1) This is because the isitactance of the L1 knee winding flows. The power output current IO has an oscillation frequency of F, a -next input of WIN%, a secondary output of WON conversion efficiency of 7, and F−X=1 T toN+ toyy. Therefore, by substituting equation (2) into equation (3), we get, and if Icp is the peak value of Ic(t) at t=TON, then Icp = -ML! -,T. , −・・−・−
(51l.Here, substituting equation (5) into equation (4) results in WIN
= T Ll, Icp, F -161. Also, Wo = 71 WxM %, WO = VOIo
, from 1o=111...
・(7) 0, and substituting equation (6) into equation (7) gives 1o=T,L
t4. Icp2. F, Ki-18) (Ll, ri, VO is c
onst). Thus, according to equation (8), it becomes clear that in order to keep the stain flow 10 constant, it is sufficient to keep the peak collector current ICP and the oscillation frequency F constant. Therefore, in the circuit of the embodiment shown in FIG. 3, the oscillation frequency F is kept constant by the oscillation frequency control circuit (9), and the peak collector current ICP is kept constant by the peak collector current control circuit (11). That is, in the circuit shown in FIG. 3, when the output of the oscillation frequency control circuit (9) is "L", the transistor Tr3' is off, a 1-base current flows through the resistor, and the collector current IO increases according to equation (2). To go. The collector current IC generates a voltage of ICX R3 in the resistor R3, and is compared with the reference voltage Vrof in the peak collector current control circuit (U). is output, the transistor Tr3 is turned on, bypassing the base current of the main transistor Trl, and turning off the main transistor Trl. Here, in the time chart in Figure 4, (
(a) shows the output of the oscillation frequency control circuit (9); (b) shows the collector current r, c; (c) shows the output current l01; and (d) shows the collector voltage VOK of the main transistor 'rr1.

As shown in FIG. 4, after the main transistor Trx is turned off, the voltage induced in the secondary winding L2 is rectified by the diode D2, and an output current IO flows. After the output current IO has finished flowing, the output of the oscillation frequency control circuit (9) becomes IH.
Since the transistor Tr3' is turned on at I, the main transistor Tr3' is turned on while the output of the oscillation frequency control circuit (9) is at IHI.
y remains off.

When the output of the oscillation frequency control circuit (9) becomes L#, the transistor Trys' is turned off and the main transistor T
A base current flows through ry, repeats the previous process, oscillates at a constant pressure, and supplies a constant output current IO. Here, the driving power source of the oscillation frequency control circuit (9) and the peak collector current control circuit (11) is provided with a quaternary winding L4 in the same oscillation trasis, and a primary winding L4 when the main transistor Tr is off. It is obtained by rectifying the induced energy f- from a diode D3 and smoothing it by a cosiphon sensor C6.This feature has the advantage of generating less heat because a low-loss power source can be obtained regardless of the input voltage. However, in order to obtain energy in the quartic winding L4, the main transistor Tr1 is oscillated after the power is turned on, and if energy is not supplied from the primary winding L1, as shown in FIG. )) The rated voltage does not occur. Therefore, during that period, the oscillator 1J
3) and the comparator (14) do not operate, so transistors Tr3' and T'3 are off and the isciverter (2) is in an uncontrolled state. When the main transistor Tr1 is turned on, the peak collector current IOP is calculated according to equation (2). flows until the oscillation trasis is saturated.Then, the input voltage Vll+ is high and the collector current ICP flows through the main transistor Tr1.
The current flows to a level exceeding the rating of , destroying the main transistor Try. To solve this problem, if we use a large-capacity transistor as the main transistor Trx, which has no problem even with the collector current ICP when the input voltage V is high, the shape will become sharper and the current will also rise. This makes it difficult to supply inexpensive small chargers. Therefore, in order to use the transistor during steady operation, the main transistor Trl current collector current tcp during uncontrolled time is
A peak collector current limiting circuit (1
2) is added to the circuit shown in Figure 3. Collector current I
When C flows through resistor R3, xc is applied to both ends of this resistor R3.
Generate the voltage of X R3, and the collector current I at this time
When the maximum value of C is set below the rating of the main transistor Try, OX R3≧VFO)4) 10VFQ)5)
+ Vagcr + 2), the transistor Tr is set at a certain collector current IC.
Since a4f is turned on, the base current of the main transistor Tr1 is bypassed, and the main transistor Trl is turned off, the main transistor Tr1 is not destroyed, and in order to obtain the above operation, the embodiment circuit shown in FIG. Here, a peak collector current limiting circuit 02) is formed by the main transistor Try and diodes D4 and D5. FIG. 5 is an explanatory diagram of the operation of this peak collector current limiting circuit (12), and the collector current re of the main transistor Trl changes as shown in FIG. (12) The same figure during operation (
When the maximum collector current rated value level of the main transistor 'rr1 is (a), the peak collector current during steady operation changes as shown in b), and as shown in Fig. The peak collector current value level when the peak collector current limiting circuit (12) is activated is lower than the respective level (f) as shown in Q'8 in the same figure, while the peak collector current value level when the peak collector current limiting circuit (12) is activated is lower than the respective level (f) in the figure (B), while when no control is applied This results in the generation of a peak collector current value higher than the level mark as shown in Figure 1, and there is a risk of destroying the main transistor Trl. Therefore, as is clear from the explanatory diagram in FIG. Even until the circuit (11) etc. starts operating, the peak collector current Icp remains below the maximum collector current value of the main transistor Tr1. Note that FIG. 6 is an explanatory diagram of the occurrence of an unlimited period,
When the power is turned on at time to, the output voltage of the power supply circuit (8) changes as shown in FIG.
1 is an uncontrolled period, and T2 is a controlled period. During the uncontrolled period Tl, the collector current IC of the main transistor Trx has a high error value as shown in FIG. At T1, the collector current control circuit (IC) starts operating and the peak value of the collector current IC is suppressed.

FIG. 7 shows another embodiment of the present invention, in which the output of the power supply circuit (8) is connected to the base of the main transistor Tr1 via a resistor R7 in the embodiment of FIG.

Thus, in the embodiment of FIG. 7, when the power is turned on, the electric charge of the decisor C5 is 0, so the current from the resistor R1 is 1d.
N-5! The base current of the main transistor Trl is not supplied to the main transistor Trl.Afterwards, when the cosidiser C5 is fully charged, the base current of the main transistor Trl starts to flow, but at the beginning, the amount flowing as the base current is small. This base current is
It gradually increases as the charge of 5 progresses. Therefore, the collector current UO of the main transistor Tr1 is also kept lower than in the case without the resistor R7, and its peak value gradually increases with each cycle. When the current is about to exceed a certain level, the peak current limiting circuit 02 is activated, and as described above, the peak collector current lap is kept below the above-mentioned constant level.

As mentioned above, the present invention is capable of always reliably suppressing the peak collector current of the main transistor to a predetermined value or less, thus eliminating the need to use a large rated main transistor and reducing the size of the main transistor. This also has the effect of making it possible to reduce the cost and easily achieve miniaturization and cost reduction of the entire device, and also has the effect of improving the reliability of the main transistor.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional example, Fig. 2 (a) to (c) are time charts of the same as above, Fig. 3 is an explanatory diagram of occurrence of △ timing in an embodiment of the present invention, and Fig. 7 is a diagram of the present invention. 1 is a circuit diagram of another embodiment of , (1) is an AC power supply, (2) is an inverter, and
rl is the main transistor. Figure 4 Figure 5 Figure 6 Procedural amendment (method) November 1, 1980 Dear Commissioner of the Japan Patent Office 1 Display of the case Charging circuit 3 Person making the amendment Relationship with the case Patent applicant Location Kadoma, Osaka Prefecture Address: 1048 Kadoma City Bold Title (583) Matsushita Electric Works Co., Ltd. Representative Iku Kobayashi 4 Agent postal code 530 8 Contents of amendments [[ on page 14, line 14 of the specification]
Figure 2 (a) - (Correct CIJ to "Figure 2". 179-

Claims (1)

[Claims] +1) In a charging circuit that includes an inverter that operates using a DC output obtained by rectifying an AC power source as a driving power source, and rectifies the high frequency output of a secondary winding provided in an oscillation transformer of this inverter to charge a rechargeable battery, Collector current detecting means for detecting the collector current of the main transistor of the inverter; and peak collector current limiting means operated by the output of the collector current detecting means to ground the bases of the main transistor and the seven transistors. Charging circuit 6 characterized by