JP2781600B2 - Latch-up protection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch-up protection circuit for preventing a latch-up of a CMOS-IC.

[Prior art] Here, "latch-up" is a characteristic of a CMOS-IC. When a voltage lower than the ground is applied between input and output terminals or a voltage higher than the power supply voltage is applied, the IC power supply input is performed. Means that a current flows between the ground and the ground, causing internal short circuit For example, in FIG. 4, when the output terminal of the IC has a potential lower than the ground, a current flows in →, which causes a flow of →, causing an internal short circuit, or when the output terminal has a potential higher than the power supply voltage to the The flow to → causes the flow to →.

FIG. 4 shows a conventional example, and shows a charger as an example. An AC power source AC into a direct current rectified by the rectifier bridge Ref, starts to flow the base current I _B to the base of the transistor to Q ₁ inverter oscillation via the resistor R ₁ for oscillation startup of the inverter block 1 from its power supply. When the base current I _a starts to flow, the beginning collector current I _C flows in the collector of the transistor Q _1, the oscillation primary winding L ₁ of the transformer T
Power supply side to the opposite ends of the collector of the transistor Q ₁ is the voltage polarity is generated. When the voltage is previously wrap a transistor Q ₁ to the base driving winding L ₃ to forward bias the base of transistor Q ₁ is get forward biased by the primary winding L _1, transistor Q ₁ is turned on at once . And, of transistor Q ₁ collector current I
_C increases in accordance with I _C = (V / L ₁ ) t. Note that, V is the input voltage, L ₁ is the primary winding L ₁ inductance, t is the time.

The collector current I _C is flowed to the resistor R ₃ for output current adjustment, the potential across V _R3 of the resistor R ₃ generates a potential of V _R3 = I _C × R _3. When this voltage is the same as the base-emitter voltage V _BEQ2 transistor Q _2, the transistor Q ₂ is turned on, not the base current flowing to the base of the transistor Q ₁ is the flow. Then, there is no increase in the collector current of the transistor Q _1, the voltage polarity of the primary winding L ₁ is reversed. Also reversed Then the potential across winding L _3, will be reverse biased transistor Q _1, and turned off once the transistor Q ₁ is, the potential is induced in the output winding L _2, the through diode D ₁ it Rectify. And that when released via the output winding L ₂ of energy, and the transistor Q ₁ in the same manner as described above is turned on, Charge the battery B by repeating this.

When the storage battery B is charged and charged to 100%, overcharging is performed unless the charging current is limited, and there is a possibility that the capacity of the storage battery B may be deteriorated. Therefore, the voltage, temperature, charging time, etc. of the storage battery B are detected to control the charging. In this case, in order to reduce the size and cost,
A control circuit using an IC having an OS structure is used. FIG. 4 shows an example of timer charging. The input voltage is divided by the resistors R ₅ and R ₆ from the rectified power supply and smoothed by the capacitor C ₃ to create a power supply for the control circuit 2 composed of a timer IC having a CMOS-IC structure.

Since the power is generated at the same time as the AC input is input, the control circuit 2 starts counting with the power. At that time, the output terminal is at the L level of the control circuit 2, the transistor Q ₃ of the inverter control is battery B off continue charging. After a certain time (time set by the resistor R ₇ , the capacitor C ₂ , and the resistor R ₈ ), the control circuit 2 of the timer IC starts the timer, the output terminal goes to the H level, and the transistor Q ₃ turns on. the base current of the transistor Q ₁ is bypassed to the transistor Q _3, the transistor Q ₁ is kept off, charging of battery B is to be stopped.

Further, when there is no capacity of the storage battery B, and you want to use immediately in the AC input may be turn on the switch SW ₁ which is connected to a load motor M, most not charged in this case is a storage battery B, the load Most of the current flows in the direction. Therefore, if the count of the control circuit 2 is not interrupted only during that time, the capacity becomes insufficient even when charging. Furthermore, when switch SW ₁ is turned on while charging is completed and AC input is performed,
Since the inverter has stopped operating, a current flows from the storage battery B to the load. Therefore, although the charging has been completed, the capacity has been reduced by using DC. Therefore, when driving the motor M of the load, in conjunction with the switch SW ₁ to suspend timer operation of the control circuit 2, it is necessary to further release the stop of the inverter. Therefore, the switch SW that is linked to the switch SW _1
2, when the switch SW ₁ is turned off, the switch SW ₂ is the emitter of the transistor Q _3, the switch SW ₁ is in the on switch SW ₂ is set to be connected to the resistor R _8.

[Problems to be Solved] Then, that becomes a problem is when the timer operation of the control circuit 2 is turned on the switch SW ₁ and timer up.
An output terminal of the switch SW ₁ is off the control circuit 2, L level during charging, since charging is completed at the H level, it is not lower than the ground terminal control circuit 2, the control circuit 2 Does not cause latch-up.

However, the switch SW ₁ counting operation by the timer up of the control circuit 2 is on, when the switch SW ₂ moves away from the emitter of the transistor W _3, the output terminal of the control circuit 2, the voltage of the winding L ₃ to be influenced. When transistor Q ₁ is turned on, since the base of the transistor Q ₁ is it has a high potential, the output terminal of the control circuit 2 at the PN junction between the base and the collector of the transistor Q ₃ remains at H level . When the transistor Q ₁ is turned off, the potential across the winding L ₃ becomes opposite, relative to the control circuit 2 terminal becomes lower base of the transistor Q ₁ is best, PN junction between the base and the collector of the transistor Q ₃ is Control circuit 2
Will be lower.

Generally, for CMOS-IC, <0.3V to 0.6V
When the voltage drops, latch-up occurs, and the short circuit occurs between the power supply of the control circuit 2 and the ground. for that reason,
The power supply voltage of the control circuit 2 drops, and the timer is reset. Thus, even though it has already been fully charged, is turned off by turning on the switch SW _1, takes the timer reset control circuit 2, will once again output terminal becomes L level, and re-charging, whereby the storage battery B There is a problem that the capacity and the life are deteriorated.

The present invention has been provided in view of the above points,
An object of the present invention is to provide a latch-up protection circuit which aims to easily and inexpensively prevent latch-up.

[Means for Solving the Problems] In the present invention, a resistor for preventing latch-up is inserted and connected in series between an output terminal of a control circuit and a base of a control transistor.

Further, an anode is connected to the ground side of the control circuit, and a Schottky barrier diode having a low forward drop voltage is connected to the base of the control transistor so as to serve as a cathode.

[Operation] According to the present invention, when a latch-up current flows, a voltage is generated across the resistor by the current, and the potential of the output terminal of the control circuit is raised to suppress the latch-up. I have.

Further, at a low forward drop voltage of the Schottky barrier diode, the potential of the output terminal of the control circuit is clamped lower than the latch-up potential to prevent the occurrence of latch-up.

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a specific circuit diagram. In addition, inverter block 1
Since the configuration and operation of the control circuit 2 are the same as those of the conventional example, the description will be omitted, and the gist will be described in detail. First
As shown in FIG., It is obtained by inserting a resistor R ₉ for preventing latch-up between the base of the output terminal and the transistor Q ₃ of the control circuit 2. When the transistor Q ₁ is off, the current flows in the latch-up through the output terminal of the control circuit 2, when you start the current flows, the potential across the resistor R ₉ by the currents occur, the control circuit 2 The potential of the output terminal is raised to suppress the latch-up. With this configuration, a small-sized charge control circuit with low current consumption can be created.
A small charger can be configured.

Second Embodiment FIG. 2 shows a second embodiment. Latch up is <
To generate potential difference of about 0.3～0.6V, the current latch-up begins to flow, resistance to occur in the R ₉ to lift the output terminal voltage, further clamps the base potential of the transistor Q ₃ by the diode D ₂ Control The output terminal of the circuit 2 is easily lifted.

Third Embodiment FIG. 3 shows a third embodiment. Connect the Schottky barrier diode D ₃ between the output terminal and the ground of the control circuit 2, it intended to clamp the reduction potential of the output terminal by the diode D ₃ in the forward voltage drop Vf of the diode D _3, a Schottky barrier diode in the case of D _3, this V
Since f is low, it can be clamped lower than the latch-up potential, so that latch-up does not occur.

[Effect of the Invention] As described above, according to the present invention, a resistor for preventing latch-up is inserted and connected in series between the output terminal of the control circuit and the base of the control transistor. When the current flows, a voltage is generated at both ends of the resistor by the current, and the potential of the output terminal of the control circuit is raised, so that latch-up can be suppressed.
In addition, since the latch-up can be suppressed only by the resistor, the configuration is simple and easy, and the effect of being inexpensive and compact is achieved.

In addition, since a Schottky barrier diode having a low forward drop voltage is connected so that an anode is connected to the ground side of the control circuit and a cathode is connected to the base of the control transistor, the low forward drop voltage of the Schottky barrier diode is used. Thus, the potential of the output terminal of the control circuit can be clamped lower than the latch-up potential to prevent the occurrence of latch-up.

[Brief description of the drawings]

FIG. 1 is a specific circuit diagram of Embodiment 1 of the present invention, FIG. 2 is a specific circuit diagram of Embodiment 2 of the above, FIG. 3 is a specific circuit diagram of Embodiment 3 of the above, and FIG. It is a specific circuit diagram. 1 is an inverter block, 2 is a control circuit, Q ₁ is an oscillation transistor, Q ₃ is a control transistor, SW ₂ is a switch, R ₉ is a resistor, D ₃ is a Schottky barrier diode,
T is the oscillation transformer, L ₁ is the primary winding, L ₂ is output windings, L
₃ is a base drive winding.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H02M 7/42-7/98 H03K 19/00-19/096 H02M 3/00-3/44 H02J 7 / 00-7/36

Claims (2)

(57) [Claims] An inverter block having an oscillation transistor and an oscillation transformer including a primary winding, an output winding, and a base drive winding of the oscillation transistor is formed, and an oscillation operation of the inverter block is controlled. CMOS
A control circuit having a structure is provided, and a base of a control transistor for turning on and off the oscillation transistor is connected to an output terminal of the control circuit, and a collector of the control transistor is connected to the base driving winding. A switch is connected between the base of the transistor and the emitter of the control transistor and the ground. When the switch is on, the control circuit turns on and off the inverter block by a control circuit. When the switch is off, the control circuit turns off the control circuit. A latch-up protection circuit, wherein a latch-up preventing resistor is inserted and connected in series between an output terminal of the control circuit and a base of the control transistor in the inverter circuit which is made inoperative. 2. A latch-up according to claim 1, wherein an anode is connected to the ground side of the control circuit, and a Schottky barrier diode having a low forward drop voltage is connected to the base of the control transistor so as to serve as a cathode. Protection circuit.