JPS5925529B2 - Automatic switching transmission device for input signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input signal automatic switching transmission device, which allows input signals coming into a plurality of input terminals including one priority input terminal to be switched to the priority input terminal without the user's help. It is an object of the present invention to provide a device that can automatically select and switch input signals using input signals input to input terminals other than the terminal and transmit one input signal.

An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a block system diagram of an embodiment of an automatic switching transmission device for human input signals according to the present invention.

In the figure, 1 is a priority input terminal, 2 and 3 are input terminals, respectively, and input signals 51, 52, and 53, which are automatically switched and transmitted, are respectively input. However, the above input signal 51,
Although the input start times at which input signals 52 and 53 enter the human input terminals 1, 2, and 3 do not coincide with each other, there is a state in which input signals 52 and 53 enter at the same time at a certain point in time.
It is assumed that the number is between 52 and 53. Input signals 51, 52
, 53 are not input, the output terminal T
Only the input terminal 1 is connected to the switch circuit 4 via the switch circuit 4. When an input signal 51 enters the priority input terminal 1 having such characteristics, the input signal 51 is transmitted through the switch circuit 4 and output from the output terminal 7. Furthermore, when the input signal 52 enters the input terminal 2, this input signal S2
is divided into two, one being supplied to the switch circuit 5 and the other being supplied to the binarization circuit 8. Furthermore, when the input signal S3 enters the input terminal 3, this input signal S3 is also divided into two in the same manner as described above, one being supplied to the switch circuit 6 and the other being supplied to the binarization circuit 9. The above-mentioned binarization circuits 8 and 9 are circuits for converting the human input signals S2 and S3 into binary signals of O or 1, and include high gain amplifiers 8a and 9a and band filters 8b and 9.
b. The control circuits 8c and 9c are connected in cascade.

The high gain amplifiers 8a, 9a perform high gain amplification on the input signals S2, S3 so that even minute level noise signals are finally output as binary signals, and output the amplified signals to the next stage bandpass filters 8b, 9b. do. The bandpass filters 8b, 9b filter the input noise signals in the input/output signals S2, S3 and the high gain amplifier 8a,
9a and the internal noise. That is,
For example, when the input signals S2 and S3 are record playback signals or tape playback signals, the band filters 8b and 9b are used not only when reproducing already recorded signals but also when the signal is not recorded between songs. The device is configured to have a passband width (for example, 1 kHz to 5 kHz) for identifying an input noise signal of a specific frequency generated at this time and supplying it to the control circuits 8c and 9c even when the magnetic head is reproducing. Therefore, regardless of the presence or absence of recorded signals, the control circuits 8c and 9c are always stably supplied to the control circuits 8c and 9c during the period when the stylus is tracing the record or during the period when the magnetic head is slidingly scanning the tape. It outputs a signal. The control circuits 8c and 9c output binary signals EA and EB of O or 1 to the storage circuit 10.

This memory circuit 10 has three output terminals, stores the input order of the input signals S2 and S3, and outputs a control signal C for switching control of the switch circuits 4, 5, and 6 from the output terminal.
Outputs Sl, CS2, and CS3. However, memory circuit 1
0 always outputs one of these control signals CS, CS2, and CS3, and is configured not to output two or more control signals at the same time. Next, this memory circuit 1
The configuration and operation of 0 will be explained in detail with reference to FIGS. 2 and 3 A to 3.

First, when no input signal is input to any of the input terminals 1 to 3, the outputs of the AND gates 13 and 14 in the memory circuit 10 shown in FIG. 2 are both at low level. The output of the NOR gate 15 which performs the NOR of the outputs of is at a high level. This Noah Gamer 15
The high level output of is applied to the switch circuit 4 as a control signal CS1 for turning on (closing) the switch circuit 4. On the other hand, the output terminals of the AND gates 13 and 14 are connected to the switching control signal input terminals of the switch circuits 5 and 6, but these are both at low level, and the switch circuits 5 and 6 are both off (open). ) has been done. Therefore, when none of the input signals S1 to S3 are received, only the switch circuit 4 is closed, and only the input signal S1 input to the input terminal 1 is selectively transmitted. There is. That is, input terminal 1 is a priority input terminal. Now, the input signal S1 enters the input terminal 1 continuously from time t1 to T7 as shown in FIG. 3A,
The input signal S2 continues to enter the input terminal 2 from time T2 to T4 as shown in FIG. It is assumed that the signal comes into input terminal 3.

Therefore, only the input signal S1 comes in between time t1 and T2, but since there is no change in the input signal of the storage circuit 10 during this period, it is assumed that none of the input signals S1 to S3 are input. Similarly, only the control signal CS1 is output, so the input signal S1 passes through the switch circuit 4 and is transmitted to the output terminal 7. FIG. 3J shows the waveform of the control signal CS. Next, when input signal S2 comes in at time T2,
The binarization circuit 8 outputs the data from time T2 to T4 as shown in FIG. 3D.
A binary signal EA that is at a high level is output until then, and this binary signal EA is differentiated by a differentiating circuit consisting of a capacitor C1 and a resistor R2 in the memory circuit 10, and is converted into a differentiated pulse e as shown in FIG. 3F. On the other hand, the signal E is converted into a signal E which rises sharply at time T2 and gradually falls after time T4, as shown in FIG. 3D, by a first hold circuit comprising a diode D1, a capacitor C2 and a resistor R3.

In other words, the first hold circuit 2 at time T2
Since the output binary signal EA of the value converting circuit 8 becomes high level, the capacitor C2 is rapidly charged without being affected by the resistor R3 by turning on the diode D1, and on the other hand, the binary signal EA is output at time T4. becomes a low level, the diode D1 is turned off, and the charge in the capacitor C2 is gradually released through the resistor R3 and the output resistor R1 of the binarization circuit 8. The above voltage E is output.

The positive pulse of the differential pulse e is applied to the set input terminal of flip-flop 11 to set it, while it is applied to the set input terminal of flip-flop 12 to keep it in the set state.

As a result, the AND gate 1 is transferred from the flip-flop 11.
The Q output applied to one input terminal of the flip-flop 12 is at a high level, and the AND gate 14 is output from the flip-flop 12.
The Q output applied to one of the input terminals continues to maintain a low level state. Since the signal E from the first hold circuit is applied to the other input terminal of the AND gate 13, the AND gate 13 outputs a high level control signal CS2 after time a T2, and as shown in FIG. The switch circuit 5 shown is closed and the input signal S2 is transmitted to the output terminal 7.

At the same time, the output control signal CSl of the NOR gate 15
goes from a high level to a low level, opening the switch circuit 4, and the control signal CS3, which is the output signal of the AND gate 14, continues to be at a low level, keeping the switch circuit 6 open. Therefore, the input signal transmitted to the output terminal 7 switches from S1 to S2 at time T2. In the above state, when the input signal S3 enters the input terminal 3 at time T3, the output binary signal EB of the binarization circuit 9 becomes high level as shown in FIG. 3G. This binary signal EB is at a high level during the period when the input signal S3 is received (T3 to T), and is converted into a differentiated pulse E6 as shown in FIG. , and at the same time, it is converted into a pulse as shown in FIG. The second hold circuit has the same configuration as the first hold circuit and performs the same operation. The differential pulse E6 is applied to the set input terminal of flip-flop 12, and its positive polarity brings it into the set state, while it is applied to the reset input terminal of flip-flop 11, switching it from the set state to the reset state.

As a result, the Q output of flip-flop 12 changes at time T3.
Thereafter, it becomes high level, and the Q output of flip-flop 11 changes from high level to low level at time T3. Therefore, the control signal CS3 taken out from the output of the AND gate 14 becomes high level as shown in FIG. 3L at time T3, thereby closing the reswitch circuit 6. At the same time, the output control signal C of the AND game port 3, which had been at a high level until now,
S2 changes to a low level as shown in FIG. 3K at time T3 due to the reset of the flip-flop 11. Therefore, the switch circuit 5 shown in FIG. 1 is opened at time T3. Further, the output control signal CS1 of the NOR gate 15 continues to be at a low level, and the switch circuit 4 is maintained in an open state. Therefore, after time T3, only the control signal CS3 is output from the memory circuit 10, and the input signal transmitted to the output terminal 7 is switched from S2 to S3. Next, at time T5, the input signal S3 stops coming in, and only the input signal S1 enters the input terminal 1.

Here, due to the stop of input signal S3, the binarization circuit 9
The output binary signal EB becomes a low level as shown in FIG. First, since the charge in the capacitor C4 is discharged via the resistor R6 and the output resistor R4 of the binarization circuit 9 (discharge time constant C4·(R4+R6)), the charge is gradually discharged after time T5 as shown in FIG. 3H. It is converted into a falling signal Eb and applied to the other input terminal of the AND gate 14. Since the high-level Q output of the flip-flop 12 indicating that the input signal S3 was inputted immediately before is applied to one input terminal of the AND gate 14, the output of the AND gate 4 is After T5, the signal Eb remains at a high level for a period of time (for example, about several seconds from time T5 to T6) until it becomes lower than the threshold level of the AND gate 14, and becomes a low level at time T6. Therefore, the high level control signal output from the memory circuit 10 is transmitted from time T3 to time T6.
During this period, CS3 is shown in FIG. 3L, but since the input signal S3 is not input during the period from time T5 to T, the input signal S1 is not input to the output terminal 7 during this period. Despite the inflow, nothing is taken out and there is no signal.

Then, at time T6, when the output of the AND gate 14 becomes low level, both of the two inputs of the NOR gate 15 become low level, so that the NOR gate 15 outputs a high level control signal CS1.

Therefore, the switch circuit 4 is closed again at time T6, and the input signal S1 is transmitted to the output terminal 7 until time T7 when the input signal S1 stops. In this way, at least one priority input terminal is connected to the output terminal 7 via the switch circuit 4 when there is no input signal to the other input terminals, and one of the other input terminals 2 and 3 is connected to the output terminal 7 via the switch circuit 4. When an input signal comes into one input terminal, that input signal is transmitted to output terminal 7 via the switch circuit, and when two or more input signals come in, only the input signal that comes in the latest is transmitted. Since it is selectively transmitted, for example, if the present invention is applied to a function switch provided at the input section of an integrated amplifier, it will be automated and the operability will be greatly improved. Further, since a binarization circuit for the input signal of the priority input terminal is not required, the circuit configuration becomes simple. Furthermore, the first and second hold circuits transmit the input signal S1 of the priority input terminal 1 after a predetermined fixed period of time has passed after the input signal to the other input terminal 2 or 3 has stopped. For example, when applied to a function switch of a pre-main amplifier, it is possible to eliminate the sense of discomfort caused by immediate switching of the playback program source. Although the above practical example describes an automatic switching transmission device provided with three input terminals, the present invention is not limited to this.

However, in this case, if the number of human input terminals is n, the number of binary circuits can be n-1 by providing one priority input terminal, and the number of flip-flops, AND gates, and diodes in the primary circuit described above can be reduced to n-1. The number may be n-1, and although it is necessary to increase the number of input terminals of the NOR gate, the circuit configuration is simpler than when n binarization circuits or the like are provided. Note that the switch circuits 4, 5 and 6 receive the above control signals CSl, CS2 and CS.
Any device whose opening/closing can be controlled electrically by 3 may be used, such as an analog switch, a photocoupler, a photocell, a bipolar transistor, a field effect transistor,
This can be realized using semiconductor elements such as diodes or electromagnetic relays.

As described above, the input signal automatic switching transmission device according to the present invention is configured such that n input signals having different input start times from n input terminals (n is an integer of 2 or more) are individually supplied. The input signals that enter the n switch circuits and the input terminals other than the predetermined input terminal among the n input terminals are separately supplied, and the supplied signals are adjusted according to the level of the signal. n-1 binarization circuits that convert into binary signals and output them; and n-1 binarization circuits that convert the n-1 binarization circuits so that each output signal of the n-1 binarization circuits is supplied separately. n-1 are provided corresponding to each of the circuits, and when an output signal of a corresponding one of the n-1 binary circuits is supplied, a first binary signal is generated. is held as an output, and the remaining 2 of the n-1 binarization circuits excluding the corresponding one binarization circuit are
a signal generation circuit that outputs and holds a second binary signal when an output signal from either of the value converting circuits is supplied;
n-1 signal generation circuits are provided corresponding to the corresponding one of the binarization circuits, and the output signal of the corresponding one of the binarization circuits and the output signal of the one of the signal generation circuits are supplied to the signal generation circuits. Therefore, during the period when the first binary signal is supplied, the corresponding one of the n-1 switch circuits to which the same input signal as the n-1 binary circuit is supplied, At the same time, during the period when the second binary signal is being supplied from the signal generation circuit, the switching control is performed so as to allow the input signal to pass through (and the first switch is controlled so as to block the passage of the input signal to the switch circuit). and the gate circuit of n-
The output signal of one first gate circuit is supplied to the n-1
A second switch circuit generates and outputs a signal for controlling one switch circuit connected to the predetermined one input terminal to pass the human input signal during a period when all of the switch circuits are in a signal cut-off state. Since it consists of a gate circuit, it is possible to greatly improve the operability of a device that selectively switches and transmits any one of the input signals manually, and at the same time, it is possible to significantly improve the operability of the device that selectively switches and transmits any one of the input signals. The number of constituent elements can be reduced, and the memory circuit is provided with a hold function, so that the predetermined signal is input from the time when no input signal enters any of the other input terminals except for the predetermined one input terminal. After being in a state where no signal is output for a certain period of time, the switch circuit can be returned to a state where input signals can be transmitted to the predetermined one input terminal. Therefore, when applied to a fantasy switch of audio equipment, for example, The input audio signal coming into one predetermined input terminal is not switched and transmitted at the moment when the input of the human input audio signal coming into the other input terminal stops, and the input audio signal is not transmitted for the predetermined fixed time period. Since it is transmitted after the signal is placed, it eliminates any audible discomfort, and from the above, it is possible to automatically switch between audio and video signals, and furthermore, it can be used in various electronic devices such as communication equipment and measuring equipment. It has features such as being able to automatically select and switch input signals.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an example of the device of the present invention;
FIG. 2 is a circuit system diagram showing an example of the main part of FIG. 1, and FIGS. 3A to 3L are signal waveform diagrams for explaining the operation of FIG. 2, respectively. 1, 2, 3... Input terminal, 4, 5, 6...
...Switch circuit, 7...Output terminal, 8,9...
... Binarization circuit, 10 ... Memory circuit, 1
1, 12...Flip flop, 13, 14...
...And Gate, 15...Noah Gate.

Claims (1)

[Claims] 1. n switch circuits to which n input signals having different input start times from n input terminals (n is an integer of 2 or more) are respectively supplied; Input signals that enter the other input terminals except for one input terminal are supplied separately, and the supplied signal is converted into a binary signal according to the level of that signal and outputted as n-1 binary signals. n-1 binarization circuits are provided corresponding to each of the n-1 binarization circuits so that each output signal of the n-1 binarization circuits is supplied separately, When the output signal of a corresponding one of the n-1 binarization circuits is supplied, the first binary signal is output and held; Of these, the remaining 2 excluding the corresponding 1 binarization circuit
a signal generation circuit that outputs and holds a second binary signal when an output signal from one of the value converting circuits is supplied, and the n-1
n-1 signal generation circuits are provided corresponding to the corresponding one of the binarization circuits, and the output signal of the corresponding one of the binarization circuits and the output signal of the one of the signal generation circuits are supplied to the signal generation circuits. Therefore, during the period when the first binary signal is supplied, the corresponding one of the n-1 switch circuits to which the same input signal as the n-1 binary circuit is supplied, A first controller that performs switching control to allow the input signal to pass, and also performs switching control to block passage of the input signal to the switch circuit during a period when the second binary signal is supplied from the signal generation circuit. a gate circuit and the n-1
During a period when the output signal of the first gate circuit is supplied and all of the n-1 switch circuits are in a signal cut-off state, the switch circuit connected to the predetermined one input terminal is An automatic switching transmission device for an input signal, comprising a second gate circuit that generates and outputs a signal for controlling switching so that the input signal passes through.