JPS5925528B2 - Automatic switching transmission device for input signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic switching transmission device for input signals, which automatically selects input signals coming into multiple input terminals using the input signals without the user's help. It is an object of the present invention to provide a device that can transmit one input signal by switching, and can also disable automatic switching as necessary to prevent malfunction and transmit one desired input signal.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an input signal automatic switching transmission device according to the present invention, and FIG. 2 is a circuit diagram of the main parts of FIG. 1.

In FIG. 1, reference numerals 1, 2 and 3 are input terminals, into which automatically switched input signals 51, 52 and 53 are input, respectively. However, although the input start times at which the above input signals 51, 52, and 53 enter input terminals 1, 2, and 3 do not coincide with each other, there is a state in which they enter at the same time at a certain point in time. is between the input signals 51 and 5253. The input signals 51, S2, and S3 are supplied to normally open switch circuits 4, 5, and 6, while some are branched and supplied to binarization circuits 7, 8, and 9. The above-mentioned binarization circuits 7, 8, and 9 are circuits for converting the input signals Sl, S2, and S3 into binary signals of O or 1, and the high gain amplifiers Al,
A2, A3. Band filters Fl, F2, F3 and control circuits Cl, C2, C3 are connected in cascade.

High gain amplifiers Al, A2, and A3 have small ′j? In order to operate even with high level noise signals, the input signals Sl, S2, S3 are amplified with high gain, and the next stage bandpass filters Fl,
Output to F3. The bandpass filters Fl, F2, F3 distinguish between the input noise signals in the input signals Sl, S2, S3 and the internal noise of the high gain amplifiers Al, A2, A3. That is, when the input signals Sl, S2, and S3 are record playback signals or tape playback signals, the band filters F, F2, and F3 are used not only during playback of already recorded signals but also between songs. Even when the needle or magnetic head is reproducing the unrecorded portion of the signal, the control circuits Cl, C2, and C3 identify the input noise signal of a specific frequency that occurs at this time.
(e.g. 1KHz to 5K1
Therefore, regardless of the presence or absence of recorded signals, it is always stable during the period when the stylus is tracing the record or during the period when the magnetic head is slidingly scanning the tape. It outputs signals to control circuits Cl, C2, and C3. Control circuits Cl, C2, and C3 are zero or one.
Value signals El, E2, and E3 are output to the storage circuit 10. This memory circuit 10 has three output terminals, including input terminals 1 to 1.
When there is an input signal to at least one of the input terminals in 3, the control signal at a predetermined level is always output from only one of the output terminals, and the control signals from the other two output terminals are set to zero and are not transmitted. It is said to be composed of Regarding the configuration and operation of this memory circuit 10, FIGS. 2 and 3A
-M will be explained in detail.

The memory circuit 10 has a memory operation fixing circuit section 12 that fixes a memory motion, and this memory operation fixing circuit section 12 has a second memory operation fixing circuit section 12.
As shown in the figure, the switch SW is always open, and the Android game 3~
15, diode H~D6, 2 from binarization circuits 7~9
NPN for switching to pass or block value signals respectively
It consists of transistors Trl to Tr3. Now, suppose that the input signal S1 continuously enters the input terminal 1 from time t1 to time T5 as shown in FIG. 3A, and is supplied to the binarization circuit 7. The obtained binary signal E1 becomes high level from time t1 to time T5 as shown in FIG. 3D.

This binary signal E1 is applied to one input terminal of the AND gate 13 in the memory operation fixed circuit section 12, and the transistor Trl.
are supplied to the respective collectors. Here, at time t1, 2
The input signals S2 and S3 are not supplied to the digitization circuits 8 and 9, so the output signals of the binarization circuits 8 and 9 are zero (low level), and the switch SW is open. Then, the outputs of the AND gates 14 and 15 are both at a low level, so the transistor Trl is turned off. Therefore, the output binary signal E1 of the binarization circuit 7 is at time t.
1, passes through the memory operation fixed circuit section 12, and is supplied to the differentiating circuit 16 consisting of the capacitor C1 and the resistor R1, and at the same time is applied to one input terminal of the 2-input AND gate 25, and is applied from time t1 to time T5. Open this for a while. The output signal E of the differentiating circuit 16 becomes as shown in FIG. Ru.

The flip-flop 22 is a flip-flop 2 which will be described later.
Similar to 3 and 24, R-S operates at the rising edge of the input pulse.
Since it is a flip-flop, the differential pulse e1 that rises at time t1 is applied to the set input terminal, and the Q output becomes high level after time t1, and the flip-flop 2
Q output of each of 3 and 24 is at time t? It becomes Mairo level. Since the Q outputs of the flip-flops 22, 23, and 24 are applied to the other input terminals of the AND gates 25, 26, and 27, after time t1, the Q outputs of the AND gates 25 go high as shown in FIG. 3J. The control signal CS1 at a low level is output, and the outputs of the AND gates 26 and 27 are at a low level, and the control signals CS2 and CS3 are not output. The control signal CSl is applied as an output signal of the storage circuit 10 to the switch circuit 4 shown in FIG. Therefore, only switch circuit 4 is closed (turned on), and input terminal 1
The input signal S1 that comes in at time t1 passes through the switch circuit 4 and is output to the output terminal 11.

Next, at time T3 while the above-mentioned input signal S1 continues to come in, supply of the input signal S2 to the input terminal 2 as shown in FIG. 3B is started, and this continues until time T6. Then, as shown in FIG. 3E, the binarization circuit 8 outputs a high-level binary signal E2 from time T3 to time T6.
is output.

This binary signal E2 is supplied to one input terminal of the AND gate 4 and the collector of the transistor Tr2, and since the transistor Tr2 is off when the switch SW is open, the binary signal E2 is supplied to the differentiating circuit 17 consisting of the capacitor C2 and the resistor R2. At the same time, it is supplied to one input terminal of the AND gate 26. Output signal E2 of differentiating circuit 17
is the input start time T3 of the input signal S2 as shown in FIG. 3H.
This is applied to the set input terminal of the flip-flop 23 to set it, and the differential pulse E2 that rises at time T3 passes through the OR game ports 9 and 21 to the set input terminal of the flip-flops 22 and 24. It is applied to the input terminals to put them in the reset state. Therefore, the Q output of flip-flop 23 is at time T3.
Thereafter, the level becomes high, the Q output of the flip-flop 24 remains at the low level as before, and the Q output of the flip-flop 22 changes from high level to low level.
This causes the flip-flop 2 to pass through the AND gate 26, which is set to an "open" state by the binary signal E2.
The high-level Q output from the control signal CS after time T3
2 (shown in FIG. 3K) and applied to the switch circuit 5 shown in FIG. 1 to close it.

At the same time, the transmission of the control signal CSl that had been output from the AND gate 25 is stopped, and the output of the AND gate 27 remains at the low level as before.
S3 is not sent. Therefore, in the above case where the input signal S2 is received at time T3 while the input signal S is being received, the switch circuit 4, which has been closed until now, is opened and the transmission of the input signal S1 is interrupted. At the same time, the switch circuit 5 is closed and only the input signal S2 that has arrived later is given priority and is output from the output terminal 11 via the switch circuit 5. Next, at time T4 between time T3 and time T5 when input signal S1 is input to input terminal 1 and input signal S2 is input to input terminal 2, input signal is input to input terminal 3. Assuming that S3 has arrived, the input signal S
3 is supplied to the switch circuit 6 and at the same time, it is supplied to the binarization circuit 9.
The signal is supplied to a binary signal E3.

This binary signal E3 has the above input signal S3 at the above time T4.
Assuming that the entry continues from to time T8, the third
As shown in FIG.
is open, the voltage is supplied to the differentiating circuit 18 consisting of the capacitor C3 and the resistor R3, while the AND gate 2
is supplied to one input terminal of 7. Therefore, the differential circuit 1
8, a differential pulse E3 which becomes positive at time T4 and becomes negative at time T8 as shown in FIG.
At the same time, flip-flop 22 is brought into the set state.
, 23 are both set.

As a result, after time T4, the Q output of the flip-flop 24 changes from a low level to a high level, the Q output of the flip-flop 22 is maintained at a low level, and the Q output of the flip-flop 23 changes from a high level to a low level.
Therefore, the high level Q output of the flip-flop 24 is outputted from the AND gate 27 as a control signal CS3 as shown in FIG. 3L to close the switch circuit 6 shown in FIG. , 26 do not output the control signals CS1, CS2 as shown in FIGS. 3J and 3K, so the switch circuits 4 and 5 shown in FIG. 1 are both opened. Therefore, at time T4 when input signals S,, S2 are being input to input terminals 1 and 2, input signal S3 is input to input terminal 3.
, the transmission of the input signal S1 continues to be stopped by the switch circuit 4 after time T4, and the input signal S2 that had been transmitted until then is cut off by the opening of the switch circuit 5. Only the input signal S3 that has come in will be outputted from the output terminal 11 with priority. Further, at time T7 when only the input signal S3 is received, the input signal S is again input to the input terminal 1.
Assuming that 1 has arrived, 2 will be created by the same operation as above.
The control signal CS1 is outputted by the value converting circuit 7 and the storage circuit 10, and at the same time, the output of the control signal CS3 is stopped, so that the switch circuit 6 is opened and only the switch circuit 4 is closed.

Therefore, the input signal output from the output terminal 11 at time T7 is automatically switched from S3 to S1.
As described above, according to this embodiment, when an input signal enters any one of the input terminals 1 to 3, this one input signal is transmitted, and any two or When human input signals arrive at all input terminals, only the input signal that arrives the latest is preferentially transmitted. However, depending on the location where the automatic input signal switching transmission device is used, there is a possibility that an interfering signal may accidentally jump directly into the circuit and cause the memory circuit 10 to malfunction.

In this embodiment, in such a case, the switch SW shown in FIG.
is closed to stop memory operation. For example, since time t1, the input signal S1 has been continuously input to the input terminal 1, and the other input terminals 2 and 3 have input signals Sl, S2.
In a state in which none of the above is input, the binary signal E1 is output from only the binary circuit 7 among the binary circuits 7, 8, and 9.
is output and applied to one input terminal of the AND gate 13.

In this state, at time T2, the memory operation fixing circuit section 12
When the switch SW inside is closed, the positive DC power supply voltage Vcc is applied to the other input terminal of the AND gate 3, so that the output of the AND gate 13 changes from low level to high level. The output of this AND gate 13 is a diode D
The voltage is applied to the base of the transistor Tr2 via the diode D5, and to the base of the transistor Tr3 via the diode D5, but since it becomes high level at the above time T2, the transistors Tr2 and Tr3 are turned on, and their collector potentials are is forced to low level. As a result, even if a disturbance signal enters the input terminal 2 or 3 after the switching operation time T2 of the switch SW, as long as the switch SW continues to be closed, the output terminals of the binarization circuits 8 and 9 will be Since the signal is forcibly held at a low level, the binary signals E2 and E3 cannot be obtained.

Therefore, when the input signal S, is input, the storage circuit 1
0 does not store the interference signal that enters the human input terminals 2 and 3 after time T2, and the storage operation is fixed, and the control signal CSI as shown in FIG. 3M is taken out from the AND gate 25. Therefore, the input signal S entering the input terminal 1
1 is transmitted from the incoming start time t1 to the end time T5 without being interrupted, and is output from the output terminal 11. Also, between times T5 and T8, input signals S2 and S3
Since the input continues, the operation of the memory circuit 10 is fixed by the input signals S2 and S3.

Therefore, even if the input signal S1 is input again at time T7, the control signal C remains unchanged until the other input signals S2 and S3 stop inputting.
S'1 is not sent, and the control signal CSI is output from the AND gate 25 at times T8 to T9 as shown in FIG. 3M. The switch circuits 4, 5, and 6 may be of any type as long as they are electrically controlled to open and close by the above control signals CSl, CS2, and CS3, such as analog switches, photocouplers, photocells, bipolar transistors, and field effect switches. This can be realized using semiconductor elements such as transistors and diodes, or electromagnetic relays.

Further, in the above embodiment, there are three input terminals for convenience of explanation, but it is also possible to use two or more input terminals. It is obvious that a differentiating circuit, an AND gate, an OR gate, a flip-flop, an NPN transistor, a diode, and a switch circuit may be provided.

As described above, the medical device for automatically switching input signals according to the present invention includes a plurality of switch circuits to which a plurality of input signals having different input start times from a plurality of input terminals are separately supplied; A plurality of binarization circuits to which signals are supplied separately, convert the supplied signals into binary signals according to the levels of the signals, and output the binary signals, and a plurality of binarization circuits corresponding to each of the plurality of binarization circuits. When the output signal of a corresponding one of the plurality of binary conversion circuits is supplied, the first binary signal is output and held, and the first binary signal is output and held. When an output signal is supplied from any of the remaining binarization circuits excluding the corresponding one binarization circuit, the second two
A plurality of signal generation circuits are provided corresponding to the plurality of binary conversion circuits and the plurality of signal generation circuits for outputting and holding the value signal, and the output signal of the corresponding one of the binary conversion circuits and the plurality of signal generation circuits are provided. During the period when the first binary signal is supplied from the signal generating circuit, the output signal of the binary converting circuit is gate-outputted to the plurality of signal generating circuits. Switching control is performed so that a corresponding one of the switch circuits passes an input signal supplied to the corresponding one switch circuit, and the second binary signal is supplied from the signal generation circuit. During this period, a first gate circuit performs switching control to block passage of an input signal supplied to a corresponding one of the switch circuits, and each output signal of the plurality of binarization circuits is separately controlled from one of a plurality of second gate circuits supplied to the input terminals; a switch that commonly applies a constant voltage to the other input terminal of the plurality of second gate circuits; By the output of the gate circuit of 2, all of the 2 value conversion circuits except the 2 value conversion circuit that is outputting the output signal among the plurality of binary conversion circuits.
The corresponding signal generating circuit and the first
transmission control means for blocking signal transmission to each of the gate circuits, and when an input signal enters only one of the input terminals of the plurality of input terminals, regardless of whether the switch is opened or closed, When the switch is closed while an input signal is being transmitted and input signals are being received at two or more input terminals among the plurality of input terminals, one input signal being transmitted at the time the switch is closed. continues to be transmitted as is, regardless of the input signal that arrives later,
When the above-mentioned switch is opened, when input signals arrive at two or more of the above-mentioned plurality of human-powered terminals, only the input signal that arrives the latest is transmitted first, so that the device is not used. In response to interference signals that may accidentally enter other input terminals depending on the location, closing the above switch allows only the desired input signal to be accurately transmitted without malfunction. In addition, it is possible to greatly improve the operability of a device that selectively switches and transmits any one of a plurality of input signals. It has features such as being able to be applied to audio switches, switching audio signals, switching video signals, and automatically selecting and switching input signals in various electronic devices such as communication equipment and measuring equipment. It is something.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of the device of the present invention;
FIG. 2 is a circuit system diagram showing an embodiment of the main part of FIG. 1, and FIGS. 3A to 3M are signal waveform diagrams for explaining the operation of FIG. 2, respectively. 1, 2, 3... Input terminal, 4, 5, 6...
... Switch circuit, 7, 8, 9 ... Binarization circuit, 10 ... Memory circuit, 11 ... Output terminal, 12 ... Memory operation Fixed circuit section, SW...
...Switch.

Claims (1)

[Claims] 1 A plurality of switch circuits to which a plurality of input signals having different input start times from a plurality of input terminals are respectively supplied, and a plurality of switch circuits to which the plurality of input signals are respectively supplied and the supplied signals are adjusted to the level of the signal. A plurality of binarization circuits are provided corresponding to each of the plurality of binarization circuits, and a corresponding one of the plurality of binarization circuits is provided. When the output signal of one binarization circuit is supplied, the first binary signal is output and held, and the remaining binary signals excluding the corresponding one of the plurality of binarization circuits are When an output signal is supplied from one of the converter circuits, the second
A plurality of signal generation circuits are provided corresponding to the plurality of binary conversion circuits and the plurality of signal generation circuits for outputting and holding the value signal, and the output signal of the corresponding one of the binary conversion circuits and the plurality of signal generation circuits are provided. The output signals of the one signal generation circuit are respectively supplied, and during the period when the first binary signal is supplied from the signal generation circuit, the output signal of the binarization circuit is gate-outputted to the plurality of Switching control is performed on a corresponding one of the switch circuits so as to pass an input signal supplied to the corresponding one switch circuit, and the second binary signal is supplied from the signal generation circuit. a first gate circuit that performs switching control to block passage of an input signal supplied to the corresponding one of the switch circuits during the period;
a plurality of second gate circuits to which each output signal of the plurality of binarization circuits is individually supplied to one input terminal thereof; and a constant voltage is applied to the other input terminal of the plurality of second gate circuits, respectively. When the switch is closed, the output of the plurality of second gate circuits is used to output all the binary values of the plurality of binary conversion circuits except the one that is outputting the output signal. 1. An automatic switching transmission device for input signals, comprising transmission control means for respectively cutting off signal transmission from an output end of the switching circuit to the corresponding signal generating circuit and the first gate circuit.