JP2692404B2 - Read circuit for magnetic head - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic head read circuit, and more particularly to a magnetic head read circuit to which a high voltage is applied during recording.

[0002]

2. Description of the Related Art Conventionally, as a device for recording information on a magnetic medium via a magnetic head and reading the recorded information by using the same magnetic head, a tape recorder, a VT, etc.
There are many types such as R, magnetic storage cameras, magnetic tapes and magnetic disks for computers. The magnetic head used in these devices is applied with a high voltage of several V to several tens of V during recording,
At the time of reading, a weak signal of 1 mV order or less is output. Therefore, the read circuit connected to the magnetic head is required to be not only a low noise circuit, but also not to be destroyed by a high voltage generated at the time of recording and not to interfere with the high voltage at the time of recording.

FIG. 6 is a read circuit diagram for a magnetic head showing a conventional example. As shown in FIG. 6, the magnetic head read circuit 3A is used to explain a malfunction of the read circuit. The magnetic head read circuit 3A is connected in parallel to the magnetic head 1 connected to the recording circuit 2, and its first stage is a transistor. The circuit is composed of Q3, Q4, current source I2, and load resistors R1, R2. The next stage circuit 4 is connected to the collectors of the transistors Q3 and Q4. On the other hand, the final stage of the recording circuit 2 is composed of a differential amplifier including transistors Q1 and Q2 and a current source I1. The magnetic head 1 is biased by the power supply 5. In the read circuit 3A, since the output currents of the transistors Q1 and Q2 forming the differential amplifier are applied to the magnetic head 1 during recording, the inductance of the magnetic head 1 causes a voltage of several V to several tens of V which is a differential waveform. Occurs at both ends of the head. However, since the middle point of the head is connected to the power source 5, one end of the head is higher than the power source 5 and the other end is lower than the power source 5.

When the read circuit 3A is connected to the head, several V to several tens of V generated in the head are generated although the current source I2 is set to zero and the operation is stopped during recording.
Voltage via the junction between the base and collector of the transistor Q3 and the resistor R1 or the base of the transistor Q4.
A current flows in a side path to the power source 5 via the collector-to-collector junction and the resistor R2, which affects the recording operation.

On the other hand, in the read operation, the current source I1 of the recording circuit 2 is set to zero to make it inoperative, and the minute voltage generated in the head 1 is amplified by the differential transistors Q3 and Q4 of the read circuit 3A, and the next stage circuit 4 is used. Have been derived to. Here, the transistor Q
3 and Q4 need to be low noise transistors. Also, the bias voltage of their bases is equal to the power supply 5,
The collector voltage is supplied to the power source 5 via the resistors R1 and R2, respectively.
Since it is given more, the collector-emitter voltage VCE is set to about 0.2 to 0.5 V, which is lower than the base-emitter voltage (VBE≈0.7 V). Even if the resulting VCE is 0.2 to 0.5 V, the amplification operation can be performed within the range that does not enter the saturation region.

FIG. 7 is a magnetic head read circuit diagram showing another conventional example. As shown in FIG. 7, this circuit is an improvement of the problem of FIG. 6, and in particular, a backflow prevention diode D1, level shift diodes D4 and D5, and current sources I3 and I4 are added. The read circuit 3A is a circuit for additionally amplifying the voltage generated in the head 1 to the differential transistors Q3 and Q4 via the level shift diodes D4 and D5. The current sources I3 and I4 are diodes D4 and D4.
5 is to be biased.

First, at the time of recording, a voltage of several V to several tens of V is generated in the head 1, but the diode D1 is reversed in the side path to the power source 5 via the diode D4, the base-collector junction of the transistor Q3, and the resistor R1. It is blocked by becoming a via. Also, the diode D5 and the transistor Q4
The same applies to the side path reaching the power source 5 via the base-collector junction and the resistor R2. Therefore, the reading circuit 3A does not affect the recording.

Next, during reproduction (reading), the diode D
1, the collector bias voltage of the transistors Q3 and Q4 is lower than the power source 5 by about 0.9V to 1.2V, which is 0.7V plus a drop in the resistance R1 or R2. Therefore, the base bias voltage of the transistors Q3 and Q4 is set to the diode 1 rather than the circuit of FIG.
Diodes D4 and D to reduce the voltage by about 0.7V
5 and current sources I3 and I4 are provided.

FIG. 8 is a magnetic head read circuit diagram showing another conventional example. As shown in FIG. 8, the read circuit 3A
Is a circuit in which diodes D2, D3, D6, transistors Q15, Q16 and current sources I6, I7 are added to the circuit shown in FIG. First, at the time of reading, the read current from the head 1 is the diodes D4 and D5 and the current source I.
An emitter follower circuit which is amplified by a differential amplifier composed of transistors Q3 and Q4, a current source I2 and resistors R1 and R2 via a level shift circuit composed of I3 and I4, and is composed of transistors Q15 and Q16, diodes D2 and D3 and current sources I6 and I7. And is led to the next stage circuit 4.

On the other hand, when the output current of the recording circuit 2 flows across the head 1 during recording, the value of the voltage differentiated by its inductance may reach several V to several tens of V. This voltage is higher than that of the power source 5 because the middle point of the head 1 is connected to the power source 5.
At this time, although the read circuit 3A is not operating, the diode D4, the transistor Q
A backflow prevention diode D1 is inserted in order to prevent a current from flowing in the path reaching the power source 5 via the base-collector junction of 3 and the resistor R1. Similarly, in order to disconnect the path to the diode D4, the base-collector junction of the transistor Q3, the base-collector junction of the transistor Q15, and the power supply 5, the backflow prevention diode D6 is inserted. Furthermore, since there is a path to the next-stage circuit 4 via the diode D4, the base-collector junction of the transistor Q3, the base-collector junction of the transistor Q15, and the diode D2, it is assumed that the next-stage circuit 4 is a differential amplifier including NPN transistors. In the case of the emitter follower circuit, a current flows through the base-collector junction of this NPN transistor (through a load, if any) to the power supply 5, which distorts the voltage waveform during recording.

[0011]

In the above-mentioned conventional magnetic head read circuit, a high voltage generated in the head during recording is disturbed or a minute voltage generated in the head during reading causes the diodes (D4, D5) to act. Because it is amplified through
There is a drawback that noise (mainly shot noise and thermal noise) generated from this diode is added to deteriorate the S / N ratio. In addition, since current flows from the current source (I3, I4) from the power source (5) through the magnetic head, the current must be set to an extremely minute current that does not affect the recorded magnetic medium. Therefore, there is a drawback that the bias current that optimizes the S / N ratio of the diodes (D4, D5) cannot be set. Further, in the conventional read circuit, it is necessary to insert backflow prevention circuits (diodes D2 and D3) to the final stage one after another, which leads to an increase in the number of elements and reduces the power supply voltage utilization rate of the next stage circuit. There is. That is, it is necessary to devise the next-stage circuit to be composed of PNP transistors or to insert a backflow prevention diode in the signal line, but both of them cause deterioration of the frequency characteristics of the signal and are not preferable.

It is an object of the present invention to prevent such interference to the recording circuit and to maximize the S / N ratio of the differential pair transistor.
It is an object of the present invention to provide a read circuit for a magnetic head capable of realizing a ratio, preventing erroneous writing, etc., improving the power supply utilization ratio in the subsequent stages and preventing deterioration of signal frequency characteristics.

[0013]

In the magnetic head read circuit of the present invention, a power source is connected to the midpoint of the magnetic head which generates a voltage sufficient to forward bias the junction by the recording current and is connected in parallel to the recording circuit. In a read circuit for a magnetic head, a differential pair transistor having bases connected to the magnetic head, a current source for supplying a constant current to a common emitter of the differential pair transistor, and a collector of the differential pair transistor are provided. One end is connected and the other end is MO
First and second connection to the power source via an S transistor
Load resistance, impedance means connected between the gate of the MOS transistor and the other ends of the first and second load resistors, and control for closing the gate of the MOS transistor during operation and opening it during non-operation And a control means for performing. The read circuit for a magnetic head according to the present invention is a read circuit for a magnetic head, in which a power source is connected to a midpoint of the magnetic head which generates a voltage sufficient to forward bias the junction by a recording current and is connected in parallel to the recording circuit. , A first pair of first and second emitter followers having bases connected to the magnetic head, a differential pair transistor having bases connected to respective emitters of the first and second emitter followers, and a common pair of differential pair transistors A current source for supplying a constant current to the emitter, and an MO connected between the collectors of the first and second emitter followers and the power source.
S-transistor, impedance means connected between the gate of the MOS transistor and the collectors of the transistors forming the first and second emitter followers, and control for closing the gate of the MOS transistor when operating and opening when not operating And a control means for performing. The read circuit for a magnetic head according to the present invention is a read circuit for a magnetic head, in which a power source is connected to a midpoint of the magnetic head which generates a voltage sufficient to forward bias the junction by a recording current and is connected in parallel to the recording circuit. A differential pair transistor whose base is connected to the magnetic head, a current source for supplying a constant current to a common emitter of the differential pair transistor, and a cascode-connected first collector of the differential pair transistor. A first and a second bipolar transistor, and is configured to take an output current from each collector of the first and the second bipolar transistor. Further, the magnetic head read circuit of the present invention has a magnetic head read circuit in which a power source is connected to a midpoint of the magnetic head which generates a voltage sufficient to forward bias the junction by a recording current and which is connected in parallel to the recording circuit. A differential pair transistor whose base is connected to the magnetic head, a current source for supplying a constant current to a common emitter of the differential pair transistor, and a cascode-connected first collector of the differential pair transistor. A first and a second MOS transistor, and is configured to take an output current from the respective drains of the first and the second MOS transistors.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a read circuit diagram for a magnetic head showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, the magnetic head 1 has transistors Q1 and Q at the final stage.
2 and the current source I1, the recording circuit 2, the differential pair transistors Q3 and Q4, the current source I2 and the load resistors R1 and R2.
A P-channel transistor Q5, a resistor R3, a transistor Q6 and a read circuit 3 having a next stage circuit 4 are connected in parallel, and a power source 5 is connected to the midpoint of the magnetic head 1. In particular, the read circuit 3 is provided with a P-channel transistor Q5 between the load resistances R1 and R2 and the power source 5, the gate of the read-out circuit 3 is connected to a common connection point of the load resistances R1 and R2, and the gate controls the base. Transistor Q
6 collectors are connected.

At the time of recording, the base currents of the current source I2 and the transistor Q6 of the read circuit 3 are set to zero, but as described above, the voltage of several V to several tens of V generated in the head 1 causes the base of the transistor Q3. Transistor Q5 via collector junction and resistor R1 or base / collector junction of transistor Q4 and resistor R2
There is a path that produces a voltage at the drain of. In this case, the transistor Q5 operates as a source on the side connected to the resistors R1 and R2 and a drain on the side connected to the power supply 5, but the transistor Q6 is off, and the gate of the transistor Q5 is connected to the source via the resistor R3. Since they are connected to each other, the voltage between the gate and the source becomes 0 V, and if the transistor Q5 is an enhanced type, it is turned off. That is, it does not serve as a bypass for the voltage generated in the magnetic head 1.

On the other hand, at the time of reading, since the current source I1 of the recording circuit 2 becomes zero, a minute voltage generated in the head 1 is directly applied to the bases of the transistors Q3 and Q4, and as a result, differential amplification is performed. It can be led to the circuit 4.
At this time, the transistor Q6 turns on and the transistor Q6
The gate of No. 5 is set to almost the ground potential. However, in the transistor Q5, the power source 5 side operates as a source, and the resistor R
The 1 and R2 sides operate as drains and are turned on.
The drain potential becomes a voltage slightly lower (about 0.1 V) than the power supply 5. On the other hand, the base bias voltages of the transistors Q3 and Q4 are equal to those of the power source 5, but the load resistances R1 and R4 are
If the voltage drop of 2 is set to 0.4 V or less, the collector-emitter voltage of the transistors Q3 and Q4 can be secured to 0.2 V or more, and the amplification operation can be performed without entering the saturation region. You can

FIG. 2 is a read circuit diagram for a magnetic head showing a second embodiment of the present invention. As shown in FIG. 2, in this embodiment, the same numbers and symbols are assigned to the same circuits and elements as those of the above-described first embodiment or the conventional example of FIGS. 6 to 8, and the description thereof will be omitted. The recording circuit 2 is also omitted. The read circuit 3 of this embodiment includes an emitter follower circuit including transistors Q8 and Q9 and current sources I3 and I4, a differential amplifier circuit including transistors Q3 and Q4, a current source I2 and resistors R1 and R2, and the emitter follower circuit. P-channel transistor Q connected
5, Q7, a backflow prevention circuit, P-channel transistors Q10, Q11 connected to the differential amplifier circuit, and a N-channel transistor Q12, Q6.
The control circuit is composed of A and controls the backflow prevention circuit of the transistors Q5, Q10, Q11, and the next stage circuit 4.

In the read circuit 3, when a high voltage is generated in the head 1 during recording, the transistors Q8 and Q9 are used.
For the path to the power supply 5 via the base-collector junction of, the backflow prevention circuit composed of the transistors Q5 and Q7 operates effectively. Here, in the transistor Q5, the transistors Q8 and Q9 side operate as a source, and the power supply 5 side operates as a drain. Since the transistor Q6A is off, the gate of the transistor Q5 is
No current flows through 12. If the collectors of the transistors Q8 and Q9 are slightly higher than the power supply 5, the source and drain are set to the same potential via the transistor Q7, and the transistor Q5 is turned off. On the other hand, for the path from the head 1, the base-emitter junction of the transistor Q8, the base-collector junction of the transistor Q4, the source / drain of the transistor Q11, and the resistor R2 to the power supply 5, the transistor Q11 is connected to the transistor Q4. Although the side operates as a source and the resistance R2 side operates as a drain, the gate of the transistor Q11 is turned off due to the collector potential of the transistor Q8, which is slightly higher than the source, via the transistor Q7, and cuts off the path. The same applies to the path on the side of the head 1 and the transistor Q9. The transistor Q12 is placed in a cascode in order to protect the withstand voltage of the transistor Q6A when the drain side thereof has a voltage higher than that of the power supply 5. In this way, the reading circuit 3 does not interfere during writing.

At the time of reading, the transistor Q6A is turned on, and the transistor Q12 is turned on via the transistor Q12.
Since the gates of Q5, Q10, and Q11 are set to substantially the ground potential and all of them are turned on, they operate as a normal emitter follower circuit and a differential amplifier. The transistor Q7
Since the gate is connected to the power supply 5, it has a higher potential than the source and is turned off.

In this embodiment, since the emitter follower circuit is provided in front, it is possible to improve the input impedance and reduce the bias current flowing in the head. However, the noise generated in the emitter follower stage may deteriorate the S / N ratio, but optimization is possible by setting the current sources I3 and I4 to the point where the noise generated by the transistors Q8 and Q9 is minimized. Is. That is, it is far more advantageous than the fact that the values of the current sources I3 and I4 of FIG. Further, the transistors Q10 and Q11 in the present embodiment can be realized in the same manner even if they are brought to the other ends of the resistors R1 and R2, that is, the power source 5 side. In this case, a high voltage generated in the collectors from the head 1 during writing between the bases and emitters of the transistors Q8 and Q9 and between the bases and collectors of the transistors Q3 and Q4 is disturbed in the next stage circuit 4. You need to be careful.

FIG. 3 is a read circuit diagram for a magnetic head showing a third embodiment of the present invention. As shown in FIG. 3, this embodiment is a modification of the first embodiment described above, and in particular, the P-channel transistor Q5 of FIG. 1 is replaced by the PNP transistor Q5A.
And a circuit in which the NPN transistor Q6 is replaced with the current source I5. Since other configurations are the same, the operation during recording and reading will be described below.

During recording, the current sources I2 and I5
Is set to zero, but as described above, the voltage of several V to several tens of V generated in the head 1 causes the base-collector junction of the transistor Q3 and the resistor R1 to pass or the transistor Q3.
There is a path for producing a voltage in the collector of the transistor Q5A through the base-collector junction of 4 and the resistor R2. In this case, the transistor Q5A operates as a reverse transistor because the collector has a higher voltage than the emitter, but the current source I5 is zero and the transistor Q5
Since the base-collector of A, that is, the emitter-base of the reverse transistor is connected via the resistor R3, the base-emitter of the reverse transistor has the same potential and is turned off. That is, the magnetic head 1
It does not become a bypass of the voltage generated at.

On the other hand, at the time of reading, since the current source I1 of the recording circuit 2 becomes zero, the minute voltage generated in the head 1 is directly applied to the bases of the transistors Q3 and Q4, and as a result, differential amplification is performed. It can be led to the circuit 4.
At this time, a current flows between the base and emitter of the transistor Q5A by the current source I5, and the transistor Q5A is saturated. Therefore, the transistor Q5A
Has a collector voltage slightly lower than the power supply 5 (about 0.1 V). On the other hand, the base bias voltage of the transistors Q3 and Q4 is equal to that of the power source 5, but the load resistances R1 and R4 are
By setting the voltage drop of 2 to 0.4 V or less, the collector-emitter voltage of the transistors Q3 and Q4 can be secured at 0.2 V or more, and the amplification operation can be accurately performed without entering the saturation region. Can be done.

FIG. 4 is a read circuit diagram for a magnetic head showing a fourth embodiment of the present invention. As shown in FIG. 4, the read circuit 3 of this embodiment includes a first emitter follower circuit including transistors Q8 and Q9 and current sources I3 and I4, transistors Q3 and Q4, a current source I2, and resistors R1 and R2.
Differential amplifier circuit consisting of transistors Q15 and Q16
And a diode D2, D3 and current sources I6, I7, a second emitter follower circuit, a transistor Q5A and a resistor R3 and a backflow prevention circuit for the first emitter follower circuit, and a diode D1 and a backflow for a differential amplifier circuit. Prevention circuit and transistor Q1
3 and a backflow prevention circuit for the second emitter follower circuit, a control circuit including a transistor Q14 and a current source I8 for controlling the three backflow prevention circuits, and a next-stage circuit 4. When a high voltage is generated in the head 1 during recording, for the path to the power source 5 via the base-collector junction of the transistors Q8 and Q9,
The backflow prevention circuit composed of the transistor Q5A, the resistor R3 and the current source I8 (however, 0) operates effectively. Here, a voltage equal to the collector voltage is applied to the base of the transistor Q5A via the resistor R3. next,
From the head 1 to the base-emitter junction of the transistor Q9, the base-collector junction of the transistor Q3, the resistor R1, or from the head 1 to the transistor Q8.
The diode D1 functions as a backflow prevention for the base-emitter junction, the base-collector junction of the transistor Q4, and the path to the power source 5 through the resistor R2. In addition to the resistors R1 and R2, the collectors of the transistors Q3 and Q4 are connected to the transistors Q15 and Q1 respectively.
The PNP transistor Q13 serves the backflow prevention function for the path reaching the power supply 5 through the base-collector junction 6 of FIG. As described above, the base of the PNP transistor Q13 is applied with a voltage lower by one junction (0.7 V) than the high voltage of the head 1 through the resistor R3, while the collector of the transistor Q13 has a voltage of three junctions (2.1 V).
V) By applying a low voltage, the transistor Q
Reference numeral 13 is a reverse transistor, which is reverse biased by two junctions and is non-conductive. Furthermore, the PNP transistor Q14 also operates as a reverse transistor, but since it is a short circuit (0 V) between the base and collector as a reverse transistor, it is non-conductive. Therefore, at the time of recording, the reading circuit 3
Does not interfere.

At the time of reproduction, since the first emitter follower circuit is placed in front, the input impedance is improved and the bias current flowing in the head 1 is reduced. However, although the S / N ratio of the noise generated in the first emitter follower stage may be deteriorated, it is optimized by setting the current sources I3 and I4 to the point where the noise generated by the transistors Q8 and Q9 is minimized. Is possible. This is far more advantageous than the fact that the values of the current sources I3 and I4 in the case of FIG.

As a modification of the above-described fourth embodiment, the transistor Q15, which constitutes the second emitter follower circuit,
It is also possible to realize a diode between the common collector of Q16 and the power supply 5 instead of the PNP transistor Q13, or a load between the load resistors R1 and R2 of the differential amplifier circuit and the power supply 5 by a PNP transistor similar to the transistor Q13. is there. Furthermore, instead of connecting the diode D1 to the common connection point of the load resistors R1 and R2, the transistor Q5A
It is also possible to connect to the collector of. Alternatively, the second emitter follower circuit may be similarly connected to the backflow prevention circuit at the preceding stage or the preceding stage.

FIG. 5 is a read circuit diagram for a magnetic head showing a fifth embodiment of the present invention. As shown in FIG. 5, this embodiment is a modification of FIG. 8 described above, and in reading, a DC level shift circuit including diodes D4 and D5 and current sources I3 and I4, and transistors Q3 and Q4.
And a differential amplifier composed of a current source I2, cascode-connected transistors Q10A and Q11A, and load resistors R1 and R2, and a transistor Q1.
5, Q16, diodes D2, D3 and current source I6
An emitter follower circuit composed of I7 is connected to the head 1. Transistors Q3, Q4, Q10A at this time,
Considering the DC bias level of Q11A, since the midpoint of the head 1 is connected to the power supply 5, the bases of the transistors Q3 and Q4 are about 0.7V lower than the power supply 5,
Also, their collectors are transistors Q10A and Q11.
Power supply 5 only for the base-emitter voltage of A (about 0.7V)
It is lower. Therefore, the transistors Q3 and Q4
The collector-emitter voltage of is about 0.7 V, and it can operate as a differential amplifier. On the other hand, transistor Q1
Regarding 0A and Q11A, since the base is connected to the power supply 5, the collector becomes lower by the voltage drop of the load resistors R1 and R2. This lowered value is 0.1-0.4V
If it is set to a degree, a collector-emitter voltage of 0.3 V or more can be secured and operation is possible. The transistor Q1
The bases of 0A and Q11A are not the power source 5, but a bias voltage source slightly lower (about 0.1 to 0.4V) than the power source 5 is provided and connected thereto, so that output amplification is performed more than in the fifth embodiment. You can increase.

The operation of the reading circuit 3 at the time of recording, that is, the operation for the high voltage generated in the head 1 will be described. For example, the route of head 1, diode D1, base-collector junction of transistor Q3, emitter-base junction of transistor Q10A, power supply 5 can be considered, but since the emitter-base junction of transistor Q10A is in the opposite direction, No current flows. Therefore, since this transistor Q10A does not operate, no high voltage is transmitted to its collector.

[0030]

As described above, the read circuit for a magnetic head of the present invention does not interfere with the high voltage generated in the head during recording, while supplying a weak output voltage of the head directly to the differential pair transistor during reproduction. In addition, since there is little or no diode means as a noise source, there is an effect that the maximum S / N ratio of the differential pair transistor can be obtained. Further, in the present invention, since the base current of the transistor only slightly flows through the head during reproduction, it is sufficiently small compared to the current sources, especially I3 and I4, which may cause erroneous writing. There is an effect that there is no. Furthermore, even when the backflow prevention diodes (D2, D3) are used in the present invention, only the first stage is needed and the subsequent stages are unnecessary, so that the number of elements can be reduced and the power supply utilization factor and signal frequency characteristic of the next stage can be reduced. The effect is that it does not deteriorate. Moreover, the present invention is based on the transistor Q.
Since Q5 and Q6 are cascode connection, transistor Q
There is also an effect that the influence of the mirror capacitance of Q3 and Q4 is reduced to reduce the input capacitance and the frequency characteristic can be improved.

[Brief description of the drawings]

FIG. 1 is a read circuit diagram for a magnetic head showing a first embodiment of the present invention.

FIG. 2 is a read circuit diagram for a magnetic head showing a second embodiment of the present invention.

FIG. 3 is a read circuit diagram for a magnetic head showing a third embodiment of the present invention.

FIG. 4 is a read circuit diagram for a magnetic head showing a fourth embodiment of the present invention.

FIG. 5 is a read circuit diagram for a magnetic head showing a fifth embodiment of the present invention.

FIG. 6 is a read circuit diagram for a magnetic head showing a conventional example.

FIG. 7 is a read circuit diagram for a magnetic head showing another conventional example.

FIG. 8 is a read circuit diagram for a magnetic head showing another conventional example.

[Explanation of symbols]

 1 Magnetic Head 2 Recording Circuit 3 Reading Circuit 4 Next Stage Circuit 5 Power Supply Q1 to Q16 Transistors I1 to I8 Current Sources R1 to R3 Resistors D1 to D5 Diodes

Claims (4)

(57) [Claims] 1. A recording current by reading circuit for a magnetic head which is connected in parallel to and recording circuitry connecting the power supply to the midpoint of the magnetic head produces a sufficient voltage to the junction Ru forward via soot, the magnetic A differential pair transistor whose bases are connected to the heads and a common pair of the differential pair transistor.
A current source that supplies a constant current to the mitter and the differential pair transformer.
One end is connected to the collector of the transistor and the other end is connected.
First and first connection to the power source through a MOS transistor
The second load resistor, the gate of the MOS transistor, and
And impedance means connected between the other ends of the first and second load resistors and the MOS transistor during operation.
Close the gate, read circuit for a magnetic head is characterized in that a control unit that performs control to open during periods of inactivity. 2. A method for forward biasing a junction by a recording current.
Connect the power supply to the midpoint of the magnetic head that produces a sufficient voltage and
Read circuit for a magnetic head connected in parallel to one recording circuit
In addition, each of the magnetic heads connected to the base
The first and second emitter followers and the first and second emitters.
Differential with the base connected to each of the Tafollower emitters
Common transistor of the paired transistor and the differential paired transistor
Current source for supplying a constant current to the inverter, and the first and second energy sources.
MO connected between the collector of the Mittafollower and the power supply
S-transistor and gate of the MOS transistor
And a transistor forming the first and second emitter followers.
The impedance means connected between the collectors of the
The gate of the MOS transistor is closed during operation
A read circuit for a magnetic head, characterized in that it has a control means for performing a control for opening at times . 3. A method for forward biasing a junction by a recording current.
Connect the power supply to the midpoint of the magnetic head that produces a sufficient voltage and
Read circuit for a magnetic head connected in parallel to one recording circuit
In addition, the difference between connecting the bases to the magnetic heads
Common pair of the differential pair transistor and the differential pair transistor.
A current source that supplies a constant current to the mitter and the differential pair transformer.
A cascode-connected first to each collector of the transistor
1, and a second bipolar transistor, said first
Each of the first and second bipolar transistors
A read circuit for a magnetic head, which is characterized in that an output current is taken out from a magnetic head. 4. A method for forward biasing a junction by a recording current.
Connect the power supply to the midpoint of the magnetic head that produces a sufficient voltage and
Read circuit for a magnetic head connected in parallel to one recording circuit
In addition, the difference between connecting the bases to the magnetic heads
Common pair of the differential pair transistor and the differential pair transistor.
A current source that supplies a constant current to the mitter and the differential pair transformer.
A cascode-connected first to each collector of the transistor
1, and a second MOS transistor, said first, second
Output from each drain of 2 MOS transistors
A read circuit for a magnetic head, characterized in that a current is taken out .