JPH05211415A - Semiconductor device - Google Patents

Abstract

PURPOSE:To quicken a processing by a magnetic disk or the like including plural read amplifiers and to enhance the high performance of a computer system such as a computer system including the magnetic disk. CONSTITUTION:An output section such as plural read amplifiers RA1 or the like provided on a magnetic disk, etc., is constituted of a couple of output emitter follower circuits including output transistors(TRs) 5, 6, TRs 7, 8 provided as emitter loads, and resistors R7, R8 and the base DC potential of the output TRs 5, 6 and 7, 8 is set lower when the relevant read amplifier RA1 is not selected to selectively turn off the TRs. Since a so-called tri-state output circuit is adopted for the output section of the read amplifier RA1, the read amplifier is realized, in which its output terminal is wired-OR-connected without increasing the parasitic capacitance of a coupling node.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when used for a read amplifier or the like included in a magnetic head drive integrated circuit of a magnetic disk device.

[0002]

2. Description of the Related Art There is a magnetic disk device (magnetic disk storage device) using a magnetic disk as a storage medium. This magnetic disk device includes a plurality of magnetic disks, a plurality of read and write magnetic heads provided corresponding to these magnetic disks, and a read current provided corresponding to the read magnetic heads and amplifying a read current thereof. And a plurality of magnetic head drive integrated circuits each provided with a read amplifier and a write magnetic head, each of which includes a write amplifier that supplies a predetermined write current to the write magnetic head.

A magnetic head driving integrated circuit including a read amplifier is described in, for example, Japanese Patent Application Laid-Open No. 60-201105.

[0004]

In a magnetic disk device having a plurality of magnetic disks, a read amplifier of a magnetic head drive integrated circuit provided corresponding to the magnetic disks responds to a predetermined selection control signal, that is, a predetermined address signal. It is brought into an operating state selectively, whereby the storage area of the corresponding magnetic disk is selectively designated. Therefore, in the conventional magnetic disk device, as illustrated in FIG. 9, for example, the non-inverting output terminal CO and the inverting output terminal COB of the eight read amplifiers RA1 to RA8 (here, when this is enabled). A so-called inverted signal that is selectively set to a low level and a corresponding inverted output terminal, etc. are represented by adding B to the end of the name. The same applies hereinafter) is a connection logic as a non-inverting coupling node RCO or an inverting coupling node RCOB. The main amplifier MA, which is summed (wired or) coupled and provided in each read amplifier, has open collector type differential transistors T15 and T16 as a basic configuration, as illustrated in FIG. The non-inverting coupling node RCO and the inverting coupling node RCOB are connected to the termination resistor R26 or R27.
Is coupled to the high-potential-side power supply voltage V ⁺ via.

However, as the performance of computer systems and the like has advanced and the demand for higher speed of magnetic disk devices has increased, the above-mentioned conventional magnetic disk devices have the following problems. It became clear by the person etc. That is, in the above magnetic disk device, the output terminals of the read amplifiers RA1 to RA8 are logically connected and connected outside the magnetic head drive integrated circuits, and the main amplifier MA of each read amplifier is formed at these connection nodes. Differential transistors T15 and T
16 collectors are directly coupled. Therefore, the non-inverting coupling node RCO and the inverting coupling node RCOB have a distributed resistance and a distributed capacitance of the coupling wiring and the differential transistor T
As a result, relatively large collector capacitances such as 15 and T16 are coupled, and the speedup of the magnetic disk device is restricted by the time constants of these distributed resistances and termination resistors R26 and R27 and the distributed capacitances and collector capacitances. Moreover,
The terminating resistors R26 and R27 need to be matched with the characteristic impedance of the wiring and the resistance value cannot be reduced, and the parasitic capacitance such as distributed capacitance and collector capacitance tends to increase with the increase in size of the magnetic disk device. It is in.

An object of the present invention is to provide a read amplifier capable of logically and logically connecting its output terminals without increasing the parasitic capacitance of the coupling node. Another object of the present invention is to increase the speed of a magnetic disk device including a plurality of read amplifiers and the like, and to improve the performance of a computer system including the magnetic disk device.

[0007]

An output portion of a plurality of read amplifiers provided in a magnetic disk device or the like is provided with an output transistor and a current source including a first transistor provided as an emitter load of the output transistor and an emitter resistance thereof. And an output emitter follower circuit including the above, and selectively lowers the DC potential at the bases of the output transistor and the first transistor when the corresponding read amplifier is in the non-selected state, and selectively selects these transistors. Turn off.

[0008]

According to the above means, the output portion of the read amplifier can be a so-called tri-state type output circuit, so that the output terminal of the read amplifier can be connected by logical OR combination without increasing the parasitic capacitance of the connection node. Can realize an amplifier. As a result, it is possible to increase the speed of a magnetic disk device including a plurality of read amplifiers and to improve the performance of a computer system including a magnetic disk device.

[0009]

1 shows a partial block diagram of an embodiment of a read system circuit of a magnetic disk device MDE to which the present invention is applied, and FIG. 2 shows this magnetic disk device MDE.
A circuit block diagram of an embodiment of the read amplifier RA1 included in the DE is shown. Further, FIG. 3 shows a read amplifier controller R included in the read amplifier RA1 of FIG.
A circuit diagram of one embodiment of AC2 is shown, and a signal waveform diagram of that one embodiment is shown in FIG. Based on these drawings, an outline of the configuration and operation of the magnetic disk device and the read amplifier of this embodiment and their features will be described.
The magnetic disk device MDE of this embodiment is not particularly limited, but is included in a high speed computer system and constitutes its main storage device. In the following description, bipolar transistors not otherwise specified are NPN type transistors.

In FIG. 1, a magnetic disk device MDE
Includes, but is not particularly limited to, eight magnetic disks having a relatively large storage capacity. Then, eight read magnetic heads MH1 to MH8 provided corresponding to these magnetic disks and eight other write magnetic heads not shown are provided, and further provided corresponding to these magnetic heads. A magnetic head drive integrated circuit is provided. The magnetic head drive integrated circuit may drive a plurality of magnetic heads.

In this embodiment, each of the magnetic head driving integrated circuits has a read magnetic head MH1 to MH.
No. 8 read amplifiers RA1 to RA8
And a write amplifier (not shown) provided corresponding to the write magnetic head, respectively, and each is formed on one semiconductor substrate made of, for example, single crystal silicon. The following description will be focused on the read amplifiers RA1 to RA8 mounted in each magnetic head drive integrated circuit, and the write amplifier will be omitted because it is not directly related to the present invention. However, in the following description, the read amplifier R
Consider A1-RA8 as a magnetic head drive integrated circuit.

The read magnetic heads MH1 to MH8 are
Complementary input terminals I of corresponding read amplifiers RA1 to RA8
* (Here, for example, non-inverting input terminal I and inverting input terminal I
Together with B, it is shown by adding * like complementary input terminal I *. Hereinafter, the same applies to complementary signals, complementary signal lines, complementary input terminals, complementary output terminals, etc.). The read amplifiers RA1 to RA8 are supplied with corresponding selection control signals AS1 to A from a control unit (not shown) of the magnetic disk device MDE.
S8 is supplied respectively. These selection control signals are
Although not particularly limited, it is normally set to low level and alternatively set to high level according to an address signal of a predetermined bit.

Each of the read amplifiers RA1 to RA8, as represented by the read amplifier RA1 in FIG. 2, has a preamplifier PRA whose complementary input terminal is coupled to a complementary input terminal I * of the corresponding read amplifier, The preamplifier P has the differential transistors T2 and T3 as a basic configuration.
Main amplifier MA receiving complementary output signal RI * of RA. The read amplifiers RA1 to RA8 will be specifically described below by taking the read amplifier RA1 as an example.

Preamplifier PRA of read amplifier RA1
Is selectively activated in accordance with the internal control signal VC1 (first internal control signal) supplied from the read amplifier controller RAC1 and is read from the corresponding magnetic head MH1 or the like via the complementary input terminal I *. Amplifies the signal to a predetermined level.

Next, the main amplifier MA includes drive transistors T1 (second transistor) and T4 (fourth transistor) provided on the collector side and the emitter side of the differential transistors T2 and T3, respectively. Of these, the collector of the transistor T1 is coupled to the high-potential-side power supply voltage V ⁺ and its emitter, that is, the internal node n1.
Is coupled to the collectors of the differential transistors T2 and T3 via the resistor R2 and the diode D1 or the resistor R3 and the diode D2 which are formed in series. The read amplifier controller RAC is provided at the base of the transistor T1.
2 supplies an internal control signal VC2 (second internal control signal), and a resistor R1 is provided between its base and emitter. On the other hand, the collector of the transistor T4 is connected to the resistor R4.
Alternatively, it is coupled to the emitters of the differential transistors T2 and T3 via R5, and the emitter is coupled to the low-potential-side power supply voltage V ⁻ via the resistor R6. Transistor T2
The non-inverted output signal RI of the preamplifier PRA is supplied to the base of the, and its inverted output signal RIB is supplied to the base of the transistor T3. The anode of the diode D1 is the inverting output node of the main amplifier MA, that is, the internal node n2, and the anode of the diode D2 is the non-inverting output node of the main amplifier MA, that is, the internal node n3.
It is said that.

Read amplifier RA1 further includes a pair of output emitter follower circuits centered on output transistors T5 and T6. The collectors of output transistors T5 and T6 are coupled to the power supply voltage V ⁺ . Further, the base of the output transistor T5 is coupled to the non-inverting output node of the main amplifier MA, that is, the internal node n3, and the emitter thereof is coupled to the non-inverting output terminal O of the circuit via the diode D3 serving as the level shift means. .. Similarly, the base of the output transistor T6 is coupled to the inverting output node of the main amplifier MA, that is, the internal node n2, and the emitter thereof is coupled to the inverting output terminal OB of the circuit via the diode D2 serving as the level shift means. A transistor T7 (first transistor) and its emitter resistance R7 are provided between the non-inverting output terminal O of the circuit and the power supply voltage V ^−.
Is provided, and a current source including a transistor T8 (first transistor) and its emitter resistance R8 is provided between the inverting output terminal OB of the circuit and the power supply voltage V ⁻ . The internal control signal VC1 is supplied from the read amplifier controller RAC1 to the bases of the transistors T7 and T8.

Here, the read amplifier controller RAC
1 is an internal control signal VC1 according to the selection control signal AS1 and the like supplied from the control unit of the magnetic disk device MDE.
Select the level of. As a result, the internal control signal VC1 is at a low level like the power supply voltage V ⁻ when the corresponding read amplifier RA1 is in the non-selected state and the selection control signal AS1 is at the low level, as shown in FIG. When the corresponding read amplifier RA1 is set to the selected state and the selection control signal AS1 is set to the high level, the read amplifier RA1 is set to a predetermined high level.

Next, the read amplifier controller RAC2
Includes a transistor T9 receiving internal control signal VC1 as shown in FIG. The collector of the transistor T9 has a PNP transistor T31 and a resistor R1.
0 to the power supply voltage V ⁺ and its emitter to the power supply voltage V ⁻ via a resistor R12. The base of the transistor T31 is a PNP transistor T32.
Is also coupled to the circuit ground potential through the PNP transistor T33.
The base of transistor T33 is coupled to the collector of transistor T31. Further, the emitter of the transistor T32 is coupled to the power supply voltage V ⁺ via the resistor R11, and the collector thereof is coupled to the ground potential of the circuit via the n diodes DS1 to DSn arranged in series. These diodes DS1 to DSn have a resistor R9
Are provided in a parallel configuration. As a result, the transistor T
31 and T32 have a so-called current mirror form. The collector potential of the transistor T32, that is, the anode potential of the diode DS1 is used as the output signal of the read amplifier controller RAC2, that is, the internal control signal VC2. The diodes DS1 to DSn are composed of bipolar transistors and have a forward voltage corresponding to their base-emitter voltage VBE.

The corresponding read amplifier RA1 internal control signal VC1 is the unselected source voltage V ^- when it is a low level, such as, the transistor T9 are turned off, the collector current I1 does not flow. Therefore, the transistors T31 and T32 are also cut off, and the internal control signal VC2 is at a low level such as the ground potential (GND) of the circuit as shown in FIG. on the other hand,
When the corresponding read amplifier RA1 is selected and the internal control signal VC1 is set to a predetermined high level, the transistor T9 is turned on and a predetermined collector current I1 flows. This collector current I1 is transmitted through the transistor T31 in the current mirror form to the transistor T32.
Becomes the collector current of the
flows into the ground potential of the circuit via n. As a result, as shown in FIG. 4, the internal control signal VC2 is set to a high level higher than the ground potential of the circuit by the total forward voltage of the diodes DS1 to DSn, that is, nVBE.

The internal control signals VC1 and VC2 are a ground potential or the power supply voltage V of the circuit ^- when it is a low level, such as, the read amplifier RA1, transistors T1 and T
4 is turned off, and the main amplifier MA is deactivated. At this time, the low level of the internal control signal VC2 is transmitted to the internal nodes n1 and n2 and n3 via the resistor R1 acting as a bleeder resistance, and these internal nodes are set to the low level like the ground potential of the circuit. .. Therefore, the output transistors T5 and T6 forming the output emitter follower circuit are turned off, and the transistors T7 and T8 forming the current source are turned off in response to the low level of the internal control signal VC1. As a result, the non-inverting output terminal O and the inverting output terminal OB of the read amplifier RA1 are both in a high impedance state. The diodes D1 and D2 are
The differential amplifiers T2 and T3 are provided so that the collector levels of the differential transistors T2 and T3 are floating when the main amplifier MA is deactivated.
Has a function of preventing the differential potential of these differential transistors from being mistakenly turned on due to the base potential of the differential amplifier rising above its collector potential.

On the other hand, when the internal control signals VC1 and VC2 are set to a predetermined high level, in the read amplifier RA1, the transistors T1 and T4 are turned on and the main amplifier MA is activated. At this time, the non-inverting output node n3 and the inverting output node n of the main amplifier MA are
A predetermined bias voltage is applied to 2 and an amplified signal of a read signal input from the corresponding magnetic head MH1 via the preamplifier PRA is transmitted. Further, by applying a predetermined bias voltage to the non-inverting output node n3 and the inverting output node n2 of the main amplifier MA, the output transistors T5 and T6 are turned on,
When the internal control signal VC1 is set to the high level, the transistors T7 and T8 forming the current source are turned on. Therefore, the read signal amplified by the main amplifier MA has a direct current level of the output transistor T5.
And after being lowered by the base-emitter voltage of T6,
The signal is transmitted to the complementary output terminal O * of the read amplifier RA1.

That is, the read amplifier RA1 of this embodiment
Etc., the read signal of the magnetic head MH1 or the like amplified by the main amplifier MA is output to the complementary output terminal O * via a pair of output emitter follower circuits centered on the output transistors T5 and T6, and The output transistors T5 and T6 and T7 and T8 forming the output emitter follower circuit are selectively turned off by selectively lowering the DC potential at their bases according to the internal control signals VC1 and VC2, that is, the corresponding selection control signal AS1. To be in a state. Therefore, the read amplifier RA1 and the like have a so-called tri-state type output section, and as shown in FIG. 1, their complementary output terminals O * can be directly connected by logical OR. As is well known, the emitter follower circuit has a relatively large input impedance and a relatively small output impedance. However, the read amplifier RA1
A relatively large collector capacitance of the differential transistor forming each read amplifier is not coupled to the complementary coupling node RO * to which the complementary output terminal O * of -RA8 is coupled, but substantially only the distributed capacitance of the coupling wiring. appear. For this reason, the CR time constant at the complementary coupling node RO * becomes so small that it can be ignored, whereby the read amplifiers RA1 to RA1.
The high frequency characteristic of RA8 is improved. As a result, the speed of the magnetic disk device MDE including a plurality of read amplifiers can be increased, and the performance of the computer system including the magnetic disk device MDE can be improved.

The diodes D3 and D4 provided in the output emitter follower circuit of the read amplifier RA1 are
It acts as a so-called level shift means, which can increase the cutoff potential of the output transistors T5 and T6 to expand the operation margin of the read amplifier RA1 and expand the output signal amplitude thereof, and at the same time, to output transistors T5 and T6.
The breakdown voltage margin of 6 is expanded, and the complementary coupling node R
It has the effect of substantially reducing the collector capacitance seen from O * by half.

The read signals of the magnetic disks output from the magnetic heads MH1 to MH8 are selected by the corresponding read amplifiers RA1 to RA8 when the corresponding selection control signals AS1 to AS8 are alternatively set to the high level. And is selectively transmitted to the complementary coupling node RO *. The read signal transmitted to the complementary coupling node RO * is amplified by the postamplifier POA and then further transmitted to a not-shown subsequent stage circuit of the magnetic disk device MDE.

As shown in the above-mentioned embodiment, by applying the present invention to the read amplifier included in the magnetic head drive integrated circuit of the magnetic disk device, the following operational effects can be obtained. That is, (1) an output emitter including an output portion of a plurality of read amplifiers provided in a magnetic disk device or the like, the output transistor including an output transistor and a current source composed of a first transistor and an emitter resistance thereof provided as an emitter load of the output transistor. By using a follower circuit, the direct current potentials at the bases of the output transistor and the first transistor are lowered when the corresponding read amplifier is in the non-selected state, and these transistors are selectively turned off. The effect that the output part of the read amplifier can be a so-called tri-state output circuit is obtained. (2) According to the above item (1), it is possible to realize a read amplifier capable of performing logical OR connection of its output terminals without increasing the parasitic capacitance of the coupling node. (3) According to the above items (1) and (2), the high frequency characteristic of the read amplifier can be improved. (4) According to the above items (1) to (3), it is possible to obtain an effect that the speed of a magnetic disk device including a plurality of read amplifiers can be increased and the performance of a computer system including the magnetic disk device can be improved. Be done.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the number of magnetic heads, that is, magnetic disks, that is, read amplifiers provided in the magnetic disk device MDE can be set arbitrarily. Further, the magnetic head drive integrated circuit does not have to be equipped with the read amplifier and the write amplifier at the same time, and conversely can be equipped with a plurality of read amplifiers and write amplifiers.

In FIG. 2, the diodes D1 and D2 provided in the main amplifier MA need not be provided when the base potentials of the differential transistors T2 and T3 in the non-operating state are lower than their collector potentials. Also,
Diodes D3 and D4 provided as level shift means in the pair of output emitter follower circuits forming the read amplifier RA1 are transistors (second transistor) which are Darlington-coupled together with the output transistors T5 and T6, as illustrated in FIG. ) T10 and T12
Can be replaced with In this case, the transistor T
As the emitter loads of 10 and T12, it is necessary to provide, for example, the transistors T11 and T13 that are selectively turned off according to the internal control signal VC1, but by adopting Darlington coupling, the input impedance of the output emitter follower circuit is further increased. However, the output impedance thereof can be further lowered, and the same effects as those of the diodes D3 and D4 can be obtained with respect to the expansion of the operation margin and the withstand voltage margin and the reduction of the storage capacity.

On the other hand, the differential transistors T2 and T3 and the drive transistor T1 which compose the main amplifier MA of the read amplifier RA1 are, for example, as shown in FIG. 6, PNP type transistors T35 and T36 and T.
34, respectively. In this case, the corresponding non-inverting output node n4 and the inverting output node n of the main amplifier MA when the corresponding read amplifier RA1 is in the non-selected state and the internal control signal VC3 is at the high level.
Since the level of 5 drops to the power supply voltage V ⁻ , one of the read amplifier controllers becomes unnecessary.

In FIG. 3, the transistors T31 to T33 of the read amplifier controller RAC2 are shown in FIG.
Can be replaced with a PNP transistor T37 that is selectively turned on. In this case, when the corresponding read amplifier RA1 or the like is in the selected state and the internal control signal VC1 is at the high level, the transistor T37 causes the collector current I2 of the transistor T14.
Is turned on in the saturation region by a predetermined collector current I3. At this time, the collector potential of the transistor T37, that is, the internal control signal VC2 is VC2 = V ⁺ -VCE _SAT37, that is, the level obtained by subtracting the collector-emitter voltage VCE _SAT37 at the time of saturation of the transistor T37 from the power supply voltage V ⁺ , which is a high potential. It is set with reference to the side power supply voltage V ⁺ . Needless to say, the corresponding read amplifier RA1 is deselected and the internal control signal V1
When C1 is set to the low level, the transistors T14 and T37 are cut off, and the internal control signal VC2
Is at a low level like the ground potential of the circuit.

Further, the block configuration of the magnetic disk device MDE shown in FIG. 1 and the read amplifier RA1 and the read amplifier controller RAC shown in FIGS.
Various circuit configurations such as 2 and the like, the logic levels of the internal control signal and the selection control signals AS1 to AS8, the polarity of the power supply voltage, the conductivity type of the transistor, and the like can take various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the read amplifier included in the magnetic head drive integrated circuit of the magnetic disk device which is the background field of application has been described. For example, the magnetic head may be a read / write shared one, or a read amplifier or similar amplification included in various storage devices such as a magnetic tape device or a magnetic floppy device having a magnetic head. It can also be applied to various digital systems including circuits. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor device including a plurality of amplifier circuits whose output terminals are connected by logical OR, or a device or system including such a semiconductor device.

[0032]

The output section of a plurality of read amplifiers provided in a magnetic disk device or the like includes an output transistor and an output emitter including a first transistor provided as an emitter load of the output transistor and a current source composed of the emitter resistance of the first transistor. A follower circuit is used, and the DC potentials at the bases of the output transistor and the first transistor are selectively lowered when the corresponding read amplifier is in the non-selected state, and these transistors are selectively turned off. .. As a result, the output part of the read amplifier can be a so-called tri-state type output circuit, so that it is possible to realize a read amplifier which can perform logical OR connection of its output terminals without increasing the parasitic capacitance of the coupling node. it can. As a result, it is possible to increase the speed of a magnetic disk device including a plurality of read amplifiers and to improve the performance of a computer system including a magnetic disk device.

[Brief description of drawings]

FIG. 1 is a partial block diagram showing an embodiment of a read system circuit of a magnetic disk device to which the present invention is applied.

FIG. 2 is a circuit block diagram showing a first embodiment of a read amplifier included in the magnetic disk device of FIG.

FIG. 3 is a circuit diagram showing a first embodiment of a read amplifier controller included in the read amplifier shown in FIG.

FIG. 4 is a signal waveform diagram showing an embodiment of the read amplifier of FIG.

5 is a partial circuit diagram showing a second embodiment of the read amplifier included in the magnetic disk device of FIG.

FIG. 6 is a partial circuit block diagram showing a third embodiment of the read amplifier included in the magnetic disk device of FIG.

FIG. 7 is a circuit diagram showing a second embodiment of the read amplifier controller included in the read amplifier of FIG.

FIG. 8 is a partial circuit block diagram showing an example of a read amplifier included in a conventional magnetic disk device.

FIG. 9 is a partial block diagram showing an example of a read system circuit of a conventional magnetic disk device.

[Explanation of Codes] MDE ... Magnetic disk device, RA1-RA8 ...
Read amplifier, MH1 to MH8 ... Read magnetic head, POA ... Post amplifier. PRA: preamplifier, MA: main amplifier, R
AC1 to RAC3 ... Read amplifier controller. T1 to T17 ... NPN type bipolar transistor,
T31 to T37 ... PNP type bipolar transistor, D1 to D4, DS1 to DSn ... Diode, R
1 to R27 ... Resistance.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Kameyama 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd.

Claims (8)

[Claims] 1. An output emitter, the output terminal of which is connectable-ORable by including an output transistor which transmits an analog signal and is selectively turned off by selectively changing a direct-current potential at its base. A semiconductor device comprising a follower circuit. 2. The first output emitter follower circuit is provided as an emitter load of the output transistor, and is selectively turned off together with the output transistor.
2. The semiconductor device according to claim 1, further comprising a current source composed of the transistor and the emitter resistance thereof. 3. The semiconductor device according to claim 1, wherein an emitter of the output transistor is coupled to the output node and a current source via a predetermined level shift means. 4. The semiconductor device according to claim 3, wherein the level shift means comprises a diode. 5. The semiconductor device according to claim 3, wherein the level shift means comprises a second transistor Darlington-coupled with the output transistor. 6. The output emitter follower circuit is included in a read amplifier of a magnetic head drive integrated circuit of a magnetic disk device, claim 1, claim 2, claim 3, claim 4. Alternatively, the semiconductor device according to claim 5. 7. The read amplifier includes a pair of differential transistors, and a third transistor provided as a current source on the emitter side of the differential transistor and selectively turned on according to a first internal control signal. , A main amplifier including a fourth transistor provided on the collector side of the differential transistor and selectively turned on in accordance with a second internal control signal, and non-inverted and inverted output signals of the main amplifier are transmitted. 7. A device comprising a pair of the output emitter follower circuits.
Semiconductor device. 8. The magnetic disk device comprises a plurality of the read amplifiers, the output nodes of which are connected by logical OR to each other and are selectively brought into an operating state according to a predetermined selection control signal. 8. The semiconductor device according to claim 7, wherein the first and second internal control signals are selectively validated when the corresponding read amplifier is activated.