JPS5925418B2 - Public telephone pole reversal signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a polarity reversal signal detection circuit in a public telephone in which a diode bridge circuit is connected between first and second office lines on the input side of a speech circuit.

In general, when connecting a telephone to a central office line, it is not necessary to pay attention to polarity in the case of general subscriber telephones with rotary dials, and a diode bridge is inserted even in the case of general subscriber telephones with push-button dialing. Because it has been
No need to pay attention.

On the other hand, in public telephones, polarity reversal pulses arrive when a called party responds or when a billing signal is sent, so in order to detect this, it is necessary to connect the telephone with a predetermined polarity relative to the office line polarity.

However, in other countries, the above-mentioned public telephones do not have polarity indications, so they may be connected to the office line with the wrong polarity, or even if they are connected with the correct polarity, the polarity may be reversed due to work at relay points, etc. There were so many lines that the phone was unable to perform its normal functions as a public telephone.

Furthermore, in such a case, it is necessary to change the wiring to invert the polarity on the public telephone side each time, and maintenance is extremely complicated. For this reason,
The applicant of this invention has recently discovered that when a telephone is hooked off, a current direction detection means such as a magnetic latching relay is connected to the central office line L1.
The paper proposes an automatic station line polarity correction circuit that connects between L2 and corrects the station line polarity by changing the switch means when the current direction detecting means is affected. This requires a separate means for detecting a polarity reversal signal after the correction circuit.

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to repeatedly detect periodically arriving polarity reversal signals regardless of the connection polarity. In addition, it is possible to make the device smaller and lighter, and it also solves the problem of public telephones not working or malfunctioning due to polarity differences, and eliminates the need for maintenance work such as changing the wiring. Eliminates the need to consider polarity when connecting to the office line, eliminates the need for separate protection diodes and bidirectional current paths, and
It is an object of the present invention to provide a polarity reversal signal detection circuit for a public telephone that does not require an automatic correction circuit for station line polarity.

In order to achieve such an object, the present invention provides a diode bridge circuit connected between the first and second office lines on the input side of a communication circuit when the first office line is at a positive potential and when the second office line is at a positive potential. A first and second photocoupler each inserted into the bridge side that forms a DC loop with the station when the potential is positive, a plurality of RS flip-flop circuits each using the output of each of these photocoupler as the setting power, and each of these RS flip-flop circuits. It consists of an AND circuit that matches the outputs of the flip-flops, and a timer counter that is unset by the output of the AND circuit and generates various control outputs, and uses the final control output as the reset input of the RS flip-flop circuit. The output of the AND circuit is repeatedly sent out each time a polarity inversion signal arrives.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

The figure is a circuit diagram showing an embodiment of a polarity reversal signal detection circuit for a public telephone according to the present invention. This is an example of an application.

In the figure, Ll and L2 are office line terminals (
(hereinafter referred to as the office line), BEL is a bell circuit consisting of a capacitor C1 and a bell Bell, and is connected between the office lines Ll and L2 via a switch contact HSl. D
B is a diode bridge circuit connected between the office lines Ll and L2 on the input side of the communication circuit TC, and the bridge-connected diodes D1 to D4 are connected in series with the diode D1 to form a first photocoupler PCl. Light emitting element P
dl and a resistor R1, a series circuit of a light emitting element Pd2 and a resistor R2 connected in series with a varistor V1 and a diode D3 connected in parallel to this series circuit, and forming a second photocoupler PC2, and this series circuit. and a varistor V2 connected in parallel to the varistor V2. Here, the first and second photocoupler PCs
l, PC2 is the station line L1 of the diode bridge circuit DB (
+) and the station line L2 (+), respectively, are inserted at the bridge sides that form a DC loop with the station. POW is a power supply circuit connected to the output side of the diode bridge circuit DB, which includes a Zener diode ZD, a diode D6 connected in parallel with this Zener diode ZD, and a capacitor C2.
It consists of a series circuit with. CCC is a forced disconnection circuit that is controlled by the output of a one-shot circuit, which will be described later, and forcibly disconnects the communication circuit TC.
~Tr4, resistors R3 to R6, and a diode D7 connected in parallel with the transistor Trl. Di is the dial impulse contact, Ds is the off-normal contact of the dial, R7 and C3 are a series circuit connected in parallel with the dial impulse contact Di, and this resistor R7
- and the capacitor C3 are provided to eliminate sparks at the dial impulse contact Di. Pt
l, pt2 are the first and second photocouplers PCl, P
The first and second light-receiving elements, R8 and R, constituting C2 are resistors connected to the emitters of the light-receiving elements Ptl and pt2, respectively, and NACl and NAC2 are the first and second light-receiving elements Ptl,
This is a noise absorption circuit that inputs the respective outputs of pt2 via inverters INl and IN2, and includes resistors RlO and Rll connected in series, and their resistors RlO and Rl.
It consists of a capacitor C4, resistors Rl2, R, 3, and a capacitor C5 connected between the connection point of l and ground,
The noise absorbing circuits NACl and NAC2 are provided to prevent malfunctions by absorbing noise such as incoming signals.

Fl and F2 are first and second flip-flops that are set by the outputs of the light receiving elements Ptl and pt2 of the first and second photocouplers PCl and PC2, respectively, and are reset by the output of a reset circuit, which will be described later. , this first flip-flop F1 is an RS latch that remembers that it is the office line L1 (+), and the second flip-flop F2 is an R latch that remembers that it is the office line L2 (+).
These latches constitute a memory circuit that stores the outputs of the first and second photocouplers PC1 and PC2, respectively.

ANDl is the Q output of the first flip-flop F1 and the second
This first AND gate AND1 constitutes a matching circuit that matches the outputs of the respective storage circuits. The output of the first AND gate ANDl is configured to reset a counter, which will be described later, via an inverter IN4. DIF is the first AND gate A
A third flip-flop F3 receives the output of NDl as an input.
This trigger differential circuit is composed of a series circuit of a capacitor C6 and a resistor Rl4, and a resistor Rl5 connected between the connection point of the capacitor C6 and the resistor Rl4 and the ground, and its output terminal is connected to a third terminal via an inverter IN3. It is connected to the set terminal S of the flip-flop F3. here,
This third flip-flop F3 is an RS latch that stores the arrival of the polarization signal, and its Q output is connected to the inverter IN5 and the bases of transistors Tr5 and Tr6 via resistors Rl7 and Rl8, respectively, and further, Inverter IN6 and respective resistor Rl
, and connected to the bases of transistors Tr7 and Tr8 via resistors R2O, respectively. F4 is a fourth flip-flop (
RS latch), F5 is a fifth flip-flop (RS latch) which sends out an output for thread tension monitoring. P is a magnetic holding type coin storage relay, and transistors Tr5,
It operates when Tr8 is turned on, and has a function of recovering when transistors Tr6 and Tr7 are turned on.

This coin handling relay P includes transistors Tr5,
Collector common connection point of Tr6 and transistors Tr7 and T
The emitters of transistors Tr5 and Tr7 are connected in common, and the connection point is connected to the power supply circuit POW via a resistor Rl6.
The emitters of transistors Tr6 and Tr8 are commonly connected, and their connection point is grounded. 0SC is an oscillation circuit,
It consists of a resistor R2l, a series circuit of a resistor R22 and a variable resistor VRl, and a capacitor C7.

CT is released from the set by the output of the first AND gate ANDl and generates various control outputs, and the final control output is sent to the first and second flip-flop circuits F.
1 and F2 are reset inputs to a timer counter, which is configured to be unset when a polarity reversal signal arrives and to be reset after 1280 ms. NANDl is a first NAND gate which receives the output Q8 and the output Ql2 of the timer counter CT, and its output terminal is connected to the output terminal via a second AND gate AND2 which takes a logical product with the output of the inverter INl6 of the resetting circuit RT. 3rd to 5th flip-flop F
3 to F5 are connected to the set terminal R. and,
The output Q8 of the timer counter CT is connected to the set terminal S of the fourth flip-flop F4 via an inverter IN7, and the output 12 of the timer counter CT is connected to the set terminal S of the fifth flip-flop F via an inverter IN. It is connected. AND3 is timer counter CT
A third AND gate which logically ANDs the output Q6 of the inverter IN8 and the output Q7 of the timer counter CT, the output terminal of which is connected to one of the input terminals of the second NAND gate NAND2, Third Nand Gate N
Connected to one of the input terminals of AND3. AND4 is a fourth AND gate which logically ANDs the Q output of the third flip-flop F3 and the Q output of the fourth flip-flop F4 via the inverter INlO, and its output terminal is connected to the input terminal of the third NAND gate NAND3. and one input terminal of the NOR gate NOR. The Q output of the fifth flip-flop F5 is connected to one of the input terminals of the second NAND gate NAND2, and the Q output of the fifth flip-flop F5 and the output of the fourth AND gate AND4 are input. The output terminal of the NOR gate NOR is connected to the base of the transistor Tr through the inverter 1N11 and the resistor R23 in series. R24 is a resistor connected between the transistor Tr~earth and ground. Here, the second NAND gate NAND2 constitutes an output gate for monitoring thread tension, and the third NAND gate NAND3 constitutes an output gate for monitoring the presence or absence of coins when a polarity change signal arrives. PT and PL are light emitting and light receiving elements that monitor the presence or absence of coins in the storage position.The anode side of the light emitting element PT is connected to the power supply +5, and the cathode side is connected to the transistor Tr via a resistor R25.
, is connected to the collector of .

Further, the collector side of the light receiving element PL is connected to one of the input terminals of the third NAND gate NAND3, and the resistor R
26 to the power supply +5, and further connected to the inverter I
It is connected to one of the input terminals of the second NAND gate NAND2 via Nl2, and its emitter side is grounded. H.O.
D is the hook-on detection circuit, and the hook switch contact HS2
The capacitor C8 is connected in series to the movable terminal of the capacitor C8, and the diode D8 and resistor R27 are connected in parallel with the capacitor C8.

NAND4 connects the output of the hook-on detection circuit HOD to the resistor R.
28 and the second and third NAND gates NA
A fourth NAND gate receives the outputs of ND2 and NAND3 as input, and this fourth NAND gate NAND4 constitutes a forced disconnection signal output gate, and its output is connected to the inverter IN,
3 to the one-shot circuit 0ST. This one-shot circuit 0ST is a circuit that sends a one-shot output that is at least longer than the falling time on the exchange side to the forced disconnection circuit CCC, and is connected to the inverter 1N13.
and the connection point between the fifth NAND gate NAND5, the capacitor C, the resistor R2, and the sixth NAND gate NAND6, and the connection point of the capacitor C, and the resistor R29, and ground. It consists of a resistor R3O and a variable resistor VR2 connected in series.

RT is a reset circuit that resets the entire circuit system at the time of forced disconnection, and is the sixth NAND gate N of the one-shot circuit 0ST.
The output of AND6 is input to the base through the inverter INl4 and the resistor R3l in series, the collector is connected to the power supply circuit POW through the resistor R33, the resistor R34, and the diode D in series, and the emitter is connected to the transistor TrlO which is grounded. , a resistor R32, a capacitor ClO, and inverters INl5 and INl6 connected in series. Next, the operation of the embodiment shown in this figure will be explained. First, when the hook switch contacts HSl and HS2 are switched by the hook-off, if the station line L1 is connected to (+), the first photocoupler PCl inserted into the bridge side of the diode bridge circuit DB The light emitting element Pd emits light, and this light emission is received by the light receiving element Ptl of the first photocoupler PCl, and after being converted into an electrical signal, the output is sent to the set of the first flip-flop F1 through the first noise absorption circuit NACl. It is applied to terminal S, and the first flip-flop F stores it. At this time, a logic "1" signal is given to the single power terminal of the fourth NAND gate NAND4 from the hook-on detection circuit HOD.Next, after inserting a coin and dialing, when the called party answers, a polarity reversal pulse is sent from the station. arrives and becomes the station line L2(+), the light emitting element Pd2 of the second photocoupler PC2 detects this and emits light, and this light emission is received by the light receiving element Pt2 of the second photocoupler PC2 and converted into an electrical signal. After that, the output is applied to the set terminal S of the second flip-flop F2 through the second noise absorbing circuit NAC2, and the second flip-flop F2 stores it. and the respective outputs Q of the second flip-flops F, , F2 are matched, and a matching output which is a polarity reversal signal detection output is sent out.Here, if the station line L2 (
+), first the second flip-flop F2 stores the output of the second photocoupler PC2, and in response to the called party the first flip-flop F1 stores the output of the first photocoupler PC1. , the output of the first AND gate ANDl is the same regardless of the polarity of the station line. The output of the first AND gate ANDl solves the reset of the timer counter CT, and also outputs the differential circuit D.
The differential output of the differentiating circuit DIF applied to IF and differentiating the output of the first AND gate ANDl causes the third flip-flop F3 to latch.

The output of the third flip-flop F3 operates the coin storage relay P and also operates the fourth AND gate AN.
The transistor Tr is turned on via D4, the NOR gate NOR, the inverter INll, and the resistor R23. When the transistor Tr is turned on, the light projecting element PT emits light. If a coin exists in the storage position, the light receiving element PL is turned on, so that logic "O" is applied to one input terminal of the third NAND gate NAND3.

Then, after the start of the timer counter CT, the third
Even if the output "1" of the AND gate AND3 is input, the third
The output of the NAND gate NAND3 is still logic [1
", and no signal for forced disconnection is sent from the fourth NAND gate NAND4. On the other hand, if there is no coin in the storage position, all three inputs of the third NAND gate NAND3 are set to logic "
1'', and the third NAND gate NAND3 sends out a logic 0 signal to the fourth NAND gate NAND4.

Therefore, the output of the fourth NAND gate NAND4 becomes logic "1" and the output of the inverter INl3 becomes logic "0", and the output triggers the one-shot circuit 0ST to perform forced disconnection as there is no coin. Then, when 20ms have passed after the start of the timer counter CT, the fourth
The flip-flop F4 latches, and the output of the fourth AND gate AND4 is set to logic "0", and the transistor Tr
9 is turned off, and the light emitting element PT stops emitting light.

At the same time, the third AND gate AND3 is closed. Furthermore, after the timer counter CT starts, 320
After ms has elapsed, the fifth flip-flop F5 latches, and its output causes the light projecting element PT to emit light again. At this timing, the coins already in the storage position should have been stored, and if there are coins due to unauthorized use such as threading, the third AND gate AND3
At the timing of monitoring the output of the second NAND gate NAN
All three inputs of D2 are set to logic "1", the output of this second NAND gate NAND2 is set to logic "O", and the output of the fourth NAND gate NAND4 is set to logic "1" to perform forced disconnection.

After the start of the subsequent timer counter CT, 340m
After s has elapsed, the output of the first NAND gate NANDl becomes logic "O" with the output of the timer counter CT, and the logic "O" of the second AND gate AND2 whose output is the input.
The third to fifth flip-flops F3 to F5, which were reset by the output, are reset. This allows the third
The logic "O" output of the flip-flop F3 closes the gate of the fourth AND gate AND4 and restores the coin storage relay P. Then, after 1280 ms, the Ql4 output of the timer counter CT resets the inverter INl7, the first and second flip-flops Fl and F2 are reset via the fifth AND gate AND5, and the counter is reset by the output of the first AND gate ANDl. Reset the CT,
All circuits are restored to their initial state.

It is assumed that the polarity reversal pulse has been restored before the output of the timer counter CTf)Ql4.

On the other hand, when a signal is input to the input terminal of the fourth NAND gate NAND4 at the time of forced cutting, that is, when the thread is suspended, there is no coin, and the hook is on, the output of the one-shot circuit 0ST is also sent to the reset circuit RT, turning on the transistor TrlO. The charge on the capacitor ClO is discharged.

As a result, the first to fifth flip-flops F1 to
F5 is set and the first AND gate ANDl
The timer counter CT is reset by the output of , and is restored to its initial state. In the above embodiment, a multi-office, forward-loop public telephone has been described, but any public telephone may be used as long as it receives polarity reversal signals periodically arriving from the central office.

As is clear from the above description, according to the present invention, periodically arriving polarity reversal signals can be repeatedly detected regardless of the connection polarity. Since flip-flops are used as a component, the device is smaller and lighter, and
It has the advantage of not requiring any timer circuit that takes into account the operating time of the relay, and can reliably prevent public telephones from malfunctioning or non-operating due to polarity differences, and also eliminates the need for maintenance work such as wiring changes due to polarity differences. Since the photocoupler is inserted into the diode bridge position, it is protected by the diodes that make up the photocoupler, which has the advantage of not requiring a separate protective diode. Since the bidirectional current is detected within the tube, a separate bidirectional current path is not required, so the practical effect is extremely large.

Further, when connecting a public telephone to a central office line, there is no need to consider polarity, and any number of people can connect it, and it is extremely effective in that it does not require a circuit for correcting the polarity of the central office line.

[Brief explanation of drawings]

The figure is a circuit diagram showing an embodiment of a polarity reversal signal detection circuit for a public telephone according to the present invention. Ll, L2... Office line, DB... Diode bridge circuit, TC... Call circuit, PCl
, PC2...Photocoupler, Pdl, Pd2・
... Light emitting element, Ptl, pt2 ... Light receiving element, F,, F2 ... Flip-flop, AN
Dl...And gate, CT...Timer counter.

Claims (1)

[Claims] 1. In a public telephone in which a diode bridge circuit is connected between the first and second office lines on the input side of the speech circuit, when the first office line of the diode bridge circuit has a positive potential and the second office line
first and second photocouplers each inserted into a bridge side that forms a DC loop with the station when the station line has a positive potential, and a plurality of RS flip-flop circuits each using the output of each of these photocouplers as a set input; Each of these R
an AND circuit that matches the outputs of the S flip-flops;
The output of this AND circuit releases the reset, generates various control outputs, and sends the final control output to the RS.
1. A polarity reversal signal detection circuit for a public telephone, comprising a timer counter used as a reset input of a flip-flop circuit, and repeatedly transmitting the output of the AND circuit each time a polarity reversal signal arrives.