JPS5838678Y2 - Specific number call prevention phone - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a telephone set in which calling a specific number is prohibited.

Some public telephones, private telephones, etc. prohibit calls from specific numbers such as toll numbers. Sometimes this is detected and the loop circuit is forcibly disconnected to prevent transmission.

However, depending on the user's fraudulent operations, it may be impossible to detect even if a specific number is called, and even if a more advanced specific number detection function is added, it cannot be said to be an absolute guarantee. When long distance calls are made using public telephones, only local call charges are collected, which has the drawback of causing unexpected damage to the installer.

The purpose of this invention is to fundamentally eliminate the drawbacks of the conventional methods, by emitting a predetermined identification tone to the central office line from the time the dial is dialed until a predetermined period of time has elapsed after the called party answers. A telephone that prevents calls to specific numbers, which is equipped with an extremely reliable feature that prevents calls from specific numbers, allowing the operator to listen to the call or detect it at the switchboard to confirm that the telephone in question is prohibited from making calls to specific numbers. It provides:

Hereinafter, the present invention will be explained in detail with reference to figures showing embodiments.

FIG. 1 is a circuit diagram showing the entire configuration of the telephone, with line terminals L1. L2 is connected to the exchange via the central line, and power is normally applied from the exchange with the line terminal L1 as the positive terminal. When the hook switch H5 is switched due to hook-off, a loop circuit is formed via the call line device. , a loop current flows through the route of diode D1 - Zener diode ZD - communication circuit device - diode D4, so a Zener voltage is generated in the Zener diode ZD, which charges the capacitor C via the diode D5, and its terminal voltage becomes the power supply VDD. The signal is given to the control unit CT as a signal.

In addition, in this case, a dial call is made based on the dial operation in the call line device, and when the called party answers through the exchange connection of the exchange, the exchange receives a response signal from the line terminal, and reverses the polarity of the power supply to L2. Since the line terminal L2 side is set as the positive electrode, the loop current flows through the route of diode D2 - Zener diode ZD - communication circuit - diode D3.

Therefore, the relay M as a response signal detection circuit operates due to the reversal of the power supply polarity of the exchange and opens its contact m, so that this is applied to the control unit CT as a detection force.

As will be described later, the control unit CT houses a signal generation circuit that generates a predetermined identification sound.
The upcoming identification tone is applied across resistor R1, which causes the identification tone to be applied to line terminal Ll.

It is sent from L2 to the central office line.

In addition, when hook-on, hook switch H3
The bell BEL is connected to the line terminal L1. It is connected to L2 and is used to notify of incoming calls.

FIG. 2 is a circuit diagram similar to FIG. 1 showing another embodiment, in which a light-emitting element LD such as a light-emitting diode and a light-receiving element PT such as a light-receiving transistor are used as a response signal detection circuit. Since a loop current is passed to the light emitting element LD through the resistor R71 due to the reversal of the power supply polarity and the light emitting element LD emits light, this emitted light is received by the light receiving element PT, and a detection force due to the reduction in its internal impedance is given to the control unit CT.

Note that the varistor VR is for keeping the current flowing through the light emitting element LD constant.

FIG. 3 is a block diagram of the control unit CT corresponding to FIG. 1, in which a voltage is applied to the terminal t1 via the contact m in FIG. 1, and the terminals t2, . From t3 onwards, an identification sound is sent out as described later.

In addition, a separate initial reset circuit is provided, which detects the Zener voltage generation of the Zener diode ZD due to hook-off and generates H (high level) and L (low level) pulses, which are the initial reset circuit. Used as a reset signal IR.

Note that from FIG. 2 onward, numbers are assigned to the outputs of each gate, and when explaining the signal path, these numbers are also written together with changes in signal levels.

In addition, a dial pulse detection circuit (not shown in the figure) is provided, which detects intermittent loop currents by detecting changes in the terminal voltage of a resistor separately inserted into the loop circuit, and detects each time a dial pulse for each digit is generated. Since the detection force PD is generated and given to the decimal counter 18N, the counter 18N counts according to the number of digits of the dial pulse.

First, when the hook-off is performed, an initial reset signal IR is generated, which causes the flip-flop circuits (hereinafter referred to as FF) 24N, 24N2 and the counter 18N
is reset, and in response to this, the clock counter 23
N, counter 26 N, FF 24 N3. FF 2
4 N4 also enters the reset state.

Next, when a dial call is made and a dial pulse for the third digit is generated, the counter 18N sets the output Q3 to H and supplies this to the NAND gate 27N1. At this time, however, since the relay M in FIG. 1 is still recovering, The Zener voltage of Zener diode ZD is applied to terminal t1 through contact m, and diode D2 and resistor Rso in FIG.
After that, the NAND gate 27N2 is set to H.

Note that an integrating circuit is constituted by resistors R49, R50 and capacitor C18, and absorbs chattering at contact m.

Therefore, the NAND gate 27N3 changes to L, thereby setting the FF24N1, and setting its output Q to H, thereby inverting the inverter 31N11H-31NIOL.
→Clock counter 23N, RL and OR gate 34
N2'L=34N3L→Counters 26N and RL release the clock counter 23N and counter 26N from the reset state, and they become operational.

However, the clock counter 23N is connected to the resistor R59°R.
6o, consists of an oscillator whose frequency is determined by a variable resistor Rv3 and a capacitor C25, and a binary counter, and after counting the output of the oscillator, the frequency IK
The output Q4 is set to H with a cycle of 256 Hz.
Since the output Q13 is set to H depending on the period of m5ec, the pulse obtained by inverting the output Q13 by the inverter 31N is counted by the decimal counter 26N.
Counter 26N after 1024 m5ec from start of operation
The output Q2 becomes H.

This is as shown in the time chart in FIG. 5 showing the waveforms of each part of the counter 26N and its peripheral circuits. When the output Q2 of the counter 26N becomes H, it is applied to the AND gate 33N13, and is also given H from terminal t1)
The output 33N11 also becomes H, and the OR gate 34N
13 H-34N 11 H-+NAND gate 27
N8 H-27N10 Set FF22N4 by L, and set its output Q to H.

Then, FF24N4Q H-+OR gate 34N1H
-34N3H gives H to the reset input R of the counter 26N, the counter 26N is reset and stops operating, and only the output QO is set to H, so the counter 26N
When the clock pulse CK becomes H, the NAN
FF24N4 is reset by D gate 27N12.13 H-27N11 L, and its output Q becomes L.
By returning to , the counter 26N resumes its operation and repeats these operations until the terminal t1 becomes L due to the arrival of the response signal as shown in FIG.

Therefore, the clock pulse input CK of the counter 26N
When and output QO become H at the same time, compound game) 3O
Since the inputs A and B of N become H and the output K becomes L, this is inverted by the inverter 31N (AND gate) 33N9 becomes H, and by keeping the same gate 33N in the ON state only during this time, the clock counter The IKHz signal from the 23N output Q4 is applied through resistor R28 to the base of transistor Q5.
and is amplified by resistor R24 and transformer T
2 to terminal t2. It is sent to t3, and this becomes the identification sound.

However, since the counter 26N repeats operation and stop as described above, the identification tone is intermittent as shown in FIG. 5, and is transmitted at an intermittent period of a mark 256 m SeC and a space 768 m sec.

This identification tone is sent to the central office line as described above, and if the dialing number is a specific number such as a prohibited long-distance number and is connected to a toll relay stand etc., then
Since the operator can hear the identification tone and confirm that the call is from a telephone that is prohibited from making calls such as toll numbers, the operator can prevent further connections.

Incidentally, cases in which an operator responds include a toll relay stand, an international relay stand, a port switchboard, etc., and by listening to the above-mentioned identification tone, it is possible to block all calls via these.

Furthermore, the same applies to a system in which an identification tone detection circuit and a dial number discrimination circuit are provided in the exchange, the identification tone is detected as well as the identification of a specific number, and the exchange is forcibly restored when the two match.

However, depending on the type of relay stand or switchboard, the polarity of the power supply to the central office line is reversed as a response signal by the operator's response operation. Since listening becomes impossible, even if a response signal is detected on the telephone side, the identification tone continues to be transmitted until a predetermined period of time has elapsed.

That is, by the response of the attendant or switchboard, or by 1. When the polarity of the central office line is reversed due to the called party's response to a call made from a number other than a specific number, the relay M shown in Figure 1 is activated.
In order to open contact m, capacitor C1s in Fig. 2 discharges, its terminal voltage becomes L, and accordingly, AND
Gate 33N12 L-33N11L, OR gate 3
4N13 L-34N11 L→NAND gate 2
FF24N4 by 7N8 L-27N10 H
is prevented from being set, its output Q is kept at L, and the operation of the counter 26N is continued.

Note that at this time, the output Q8 of the counter 26N is L because the count has not reached this point, and the output Q8 of the counter 26N is L.
N12 is also set to L.

When the counter 26N continues to operate and the output Q5, which is omitted in FIG. 2, becomes H, the carry output CA changes to L, setting the FF 24N2 and outputting
is set to H, and the reset state of FF24N3 is released.

However, FF 24 N3 is irrelevant until the counter 26N starts operating after it once stops operating.

Next, when the output Q8 of the counter 26N becomes H, O
R gate 34N12 H-34N11 H→NAN
D gate 27N8 H-27N10 F by L
In order to set F 24 N4 and set its output Q to H, the counter 26N stops operating and sets only the output QO to H, so that the coincidence output with the H of the clock pulse input CK is output from the NAND gate 27N11. When it occurs as L, the FF 24N4 is reset and the counter 26N starts operating.

When the output Q3 becomes H after the counter 26N starts operating, the carry output CA is also H at this time, and the FF 24N3, which was previously released from the reset state, is set by the NAND gates 27N5, 6H-27N4L. , its output Q is set to H, and the inverter 31
In addition to being inverted by N, the NAND game l-27N9
L-27N10H prohibits FF24N4 from being set.

Therefore, the counter 26N continues to operate, and when the output Q9 becomes H, it is applied to the clock enable manual CKE to stop the counting operation, and the OR gate 34N9 H-34N10 H→inverter 31
NI H-31N2 L resets FF 24N1, changes its output Q to L, and inverter 31N1
1 L-31N10 H→Clock counter 23N
, RH and OR gate 34N2H34N3H→counter 26N, RH sets each counter 23N, 26N to the reset 1 state and completely stops the operation.

Therefore, during this period, the clock pulse CK of the counter 26N and the output Q O, Q 2. Q4. Q6. Q
When any of 8 becomes H at the same time, the composite gate 3ON inputs A, B-C, D-E, FG, H-i, J
In order to set the output J to L due to input matching in each village, the identification sound is sent out intermittently as shown in Figure 5, and after the response signal is detected, the identification sound mark period is sent out 8 times. After a predetermined period of time has elapsed, the transmission of the identification tone is stopped, and if the call is from a number other than the specific number, the call becomes possible.

In addition, as a compound game) 3ON, it is an AND gate.

An AND-OR inverter gate is used, which is a combination of an OR gate and an inverter.

FIG. 4 is a block diagram of the control unit CT in FIG. 2, which is almost the same as FIG. 3 and performs the same operation as shown in FIG.
In FIG. 4, inverters 36N to 32N are provided instead of resistors R2 to R50.

That is, until the response signal arrives, the light receiving element PT in FIG. 2 is in the off state, the terminal t1 is grounded by the resistor R66 and is in the L level, and the FF37N is in the reset state, so the output Q is in the L level. (Inverted by inverter 32N, NAND gate 27N2, AND gate) 33N
12 is set to H, but when the light emitting element LD emits light due to the arrival of the response signal, the light receiving element PT turns on, and the terminal t
By setting 1 to H, inverter 36N9 becomes L, and resistors R67 and R6s inserted for noise removal
and FF3 through the integration circuit of capacitor C26.
7N and change the output Q to H to inverter 3.
Let 2N4 be L.

Therefore, the same operation as in FIG. 3 is performed.

As described above, the clock counter 23N in FIGS. 3 and 4 is used as a signal generation circuit, and the others are used as control circuits.
Although the identification sound is transmitted, a single oscillator may be provided as the signal generating circuit, and any configuration may be selected depending on the conditions of the control circuit.

Furthermore, as the response signal detection circuit, one suitable for the nature of the response signal may be used, and for AC signals etc., a filter or a counter or the like may be used to detect a specific frequency.

Note that the frequency of the identification signal, the continuation status, etc. are also selective, and the embodiment can be modified in various ways.

As is clear from the above explanation, according to the present invention, it is possible to reliably identify an incoming call from a telephone that is prohibited from making calls to a specific number by using the identification tone, and the identification tone remains unchanged for a predetermined period of time even after the response signal is sent. Since the transmission continues, it is easy to confirm, and it is possible to completely prevent calls from specific numbers at the relay board, switchboard, or exchange side, making it impossible to make calls to specific numbers based on unauthorized operations, and causing a large amount of damage to various telephones. It exhibits the effect of

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, Figures 1 and 2 are circuit diagrams showing the entire configuration of the telephone, Figure 3 is a block diagram of the control section in Figure 1, and Figure 4 is the control unit in Figure 2. FIG. 5 is a time chart showing the operating status of FIGS. 3 and 4. Ll, L2...Line terminal, R3...Hook switch, R1...Resistor, D1-D5.
...Diode, ZD ... Zener diode, C ... Capacitor, M ... Relay (response signal detection circuit), m ... Contact, L.D.
......Light emitting element (response signal detection circuit), 4 units...
...Light receiving element, 0 pieces...Control unit, placement...
...Telephone circuit, 23N...Clock counter (signal generation circuit), T2...Transformer, Q5...
...Transistor, 33N...AND gate, 18N. 26N...Counter, 3ON...Compound game 1~. 24N.

Claims (1)

[Scope of utility model registration request] A telephone set that prohibits dialing a specific number has a signal generation circuit that generates a predetermined identification tone, a response signal detection circuit that detects a response signal sent from the exchange in response to a callee's response, and a telephone set that prohibits dialing. 1. A specific number call prevention telephone set, comprising: a control circuit that transmits the accompanying identification tone to a central office line and stops the transmission of the identification tone after a predetermined time has elapsed from the detection of the response signal.