JPS5924554B2 - Structure of solar cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solar cell that uses a thin film as a material to simplify connections between elements and to reduce the thickness of the solar cell.

In recent years, solar cells have attracted a lot of attention from the perspective of using clean energy.

The scope of use is wide ranging from power for artificial sanitation and lighthouses to consumer electronics such as calculators, radios, and watches. However, since the electromotive force of the solar cells themselves is small, in both cases, multiple solar cells are connected in series. Most conventional solar cells are solar cells using single crystal silicon, and their connection methods are shown in FIGS. 1 and 2.

FIG. 1 shows a method of connecting solar cells in which one electrode is on the surface and the other electrode is on the surface.

In the figure, 101 is an insulating substrate, 102a to 102d are wirings taken out from the surface electrodes, 103a to 103d are P type regions, 104a to 104d are N type regions, 105a to 105
c is a connection wiring between solar cells. Wire bonding is generally used for connection wiring in small consumer devices. Further, the output from the array in which a plurality of solar cells are connected is carried out from 106 and the IOT. FIG. 2 is an example of a method of connecting a solar cell in which both positive and negative electrodes are on the back side.

In the figure, 201 is an insulating substrate such as a printed circuit board. 202a to 202d are metal wiring formed on an insulating substrate, 203a to 203c are P-type regions of a solar cell,
204a to 204c are N-type regions, and 205a to 205c are adhesives between the N-type regions and metal wiring, and since conduction is required, solder or conductive adhesive is used.

Naturally, if the N-type region and the P-type region are reversed in FIGS. 1 and 2, the polarity of the external output will simply be reversed.

The conventional connection method shown in FIGS. 1 and 2 has the following drawbacks when used as an energy source.

1. The connection method is complicated and the manufacturing cost is high.

2. The array becomes thick, making it difficult to apply to watches, calculators, etc.

Therefore, the scope of use is limited. Looking at the connection method, in the method shown in FIG. 1, the wire punches are punched one stage at a time, so the connection time is proportional to the number of elements. Therefore, an array consisting of a large number of elements increases the cost. Similarly, in the method shown in FIG. 2, the time for bonding with a conductive adhesive or the time for fern is proportional to the number of elements. Furthermore, in both Figures 1 and 2, it takes a considerable amount of time to align the solar cells to the substrate. Conventional connection methods like these require a lot of assembly time for arrays with a large number of elements. has become a factor in increasing costs. Next, regarding the thickness, since a single crystal solar cell is conventionally used, the thickness of the solar cell itself is at least about 300 μm.

When using wire bonding as in the method shown in Figure 1,
The thickness of the board is approximately 100μm due to wire bending, etc., and if a board with a thickness that can withstand bonding is used, the thickness of the board is 500μm to 6μm.
00 μm, and the thickness of the array is approximately 1Tf1Jt. In the case of Figure 2, the substrate is required to be strong, and considering the thickness of the adhesive, the thickness of the entire array is approximately 1V! It becomes 1.

For consumer devices such as wristwatches, calculators, radios, and measuring instruments, there are strict limits on thickness, and in some cases, thickness is 50 to 1.
They even compete for 00μm.

For the above-mentioned reasons, a thick array as in the conventional connection method will narrow the range of applications in the future. The present invention eliminates these drawbacks and aims to 1) simplify the connection method and 2) reduce the thickness of the solar cell array.

The present invention will be explained below using examples. An embodiment of the solar cell of the present invention is shown in FIG. N-type amorphous semiconductors 303a, 303b, 303c, intrinsic amorphous semiconductors 304a, 304b, 304c, . P-type amorphous semiconductors 305a, 305b, and 305c are formed in this order. After that, lead wiring 302 is provided in the amorphous semiconductor at both ends. In this case, what is important is the relationship between the shape and height of the step in the substrate 301 having the step and the thickness of the thin film deposited thereon. In the present invention, each thin film deposited on the entire surface due to the step is cut at the step, and among the cut thin films, the lower N-type amorphous semiconductors 303a and 303b are thin films. , 303c, and P-type amorphous semiconductors 305a, 305b, 30 which are upper thin films.
5c are required to be connected by being located at approximately the same height. To achieve this, the shape of the step must be approximately at right angles (80 degrees or more) or overhang, and the ratio of the height of the step to the thickness of each thin film must be approximately twice or more. There must be. In addition, the current characteristics when the N-type amorphous semiconductors 303a, 303b, 303c and the 5P-type amorphous semiconductors 305a, 305b, 305c are connected are, as is well known, because they are amorphous. Because there are many levels in the bandgap, no junctions are formed and it has the same characteristics as when semiconductors are connected with a conductive material.

Because of these properties, even if the N-type amorphous semiconductors 303a, 303b, 303c and the P-type amorphous semiconductors 305a, 305b, 305c are in close contact with each other as in the present invention, they are not in a normal conductive state. be. Next, the manufacturing method of this example will be explained in detail.

When creating three steps of 1 μm on a Sl substrate, photolithography, which is commonly used in semiconductor manufacturing, is used.
Use reactive ion etching.

First, as shown in 1a of FIG. 4, a resist is formed in a desired pattern, and the portions without the resist are etched by 1 .mu.m by reactive ion etching. next,
By forming a resist with a desired pattern so as to cover the formed step and etching it by 1 μm in the same way,
Form the second step. Thereafter, three steps are formed on the Si substrate using the same method. The shape of the step can be made to have an angle close to a right angle depending on the conditions of reactive ion etching. Note that a predetermined pattern can be formed on a substrate other than a Si substrate, such as a glass substrate, by changing the conditions of reactive ion etching.

Note that a substrate of the same shape can also be obtained by wrapping a substrate with a desired level difference in advance, without using photoetching. Further, an amorphous male silicon thin film is produced under the following conditions. a- for making solar cells
The reaction conditions for Si were as follows using the plasma CVD method.

The size of the substrate &ζ is 10XlOCfIL. RF
l3.56MHZPOwer2OW Reaction temperature 25'C Pressure 0.8/TOrr Gas 100% SiH4 1. In the case of forming a P-type amorphous semiconductor, the gas flow rate of the above gas is as follows.

2. When forming an intrinsic amorphous semiconductor Gas flow rate of the above gas! Lice as below.

3. When forming an N-type amorphous semiconductor The gas flow rates for the above gases are as follows.

The device can be used as a solar cell for a calculator at 1C in a three-stage structure.
TrL x 4cm square one, 10? XlO? 18 pieces were made from this board.

The thickness of the device was made approximately 100 μm by wrapping the substrate before cracking. The number of stages in the device is 3, and the height difference between each substrate is 1 μm. The thickness of the solar cells formed at each stage is 1.2 μm, and the thickness of the solar cell thin film in all stages is 3.2 μm. . As mentioned above, since the present invention has a step structure using a thin film, the thickness of the substrate can be completely reduced! Usually, about 400 Si wafers, which are used in semiconductor structures, are processed by wrapping.
μm, so the thickness of the array is 0.4u.

Furthermore, like solar cells for watches, the area of the array is 1?
When it comes to X1 thickness, it can be made even thinner in terms of strength, and it has the effect of being able to be made thinner to about 100 μm after processing the array substrate.

[Brief explanation of drawings]

Figures 1 and 2 are explanations of conventional solar cells;
The figure is an illustration of the solar cell of the invention. FIG. 4 is a process diagram of a method for forming a step. 10
1... Insulator substrate, 102a to 102d...
...Extracting wiring, 103a to 103d...
P-type region, 104a to 104d...N-type region,
105a to 105c...Connection wiring, 201...
...Insulator substrate, 202a to 202d...
Metal wiring, 203a to 203c...P type region,
204a-204c...N-type region, 205a-
205c...Adhesion level L between N-type region and metal wiring
3Ol...Substrate with steps, 302...
・・Output wiring, 303a to 303c・・・・・・N
type amorphous semiconductor, 304a to 304c...basic amorphous semiconductor, 305a to 305c...p type amorphous semiconductor.

Claims (1)

[Claims] 1. A substrate having a plurality of planes having mutual steps, a first conductivity type first amorphous semiconductor thin film formed on the planes, and an intrinsic second non-crystalline semiconductor thin film formed on the first thin film. It consists of a crystalline semiconductor thin film and a third amorphous semiconductor thin film of a second conductivity type formed on the second thin film, and the first thin film is substantially the same as the third thin film on an adjacent plane. A structure of a solar cell characterized by having a height and being directly connected.