JPS592410B2 - automatic equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer, and particularly to a line automatic equalization circuit for correcting waveform distortion due to line frequency loss characteristics.

Conventional devices of this type can be broadly divided into the following two types.

1 Slope AGC circuit.

...As shown in Fig. 1, a variable line equalization circuit 1 which has an approximate frequency characteristic inverse to the line frequency characteristic loss, and a peak detection circuit 2 for detecting the peak voltage of the output waveform. This method takes advantage of the fact that the amount of line operation attenuation at the Nyquist frequency is proportional to the peak voltage of the received waveform.

This method has the advantage of simplifying the circuit configuration, and is an effective method for lines whose line characteristics are known in advance. However, in the case of subscriber lines, there are 5 types of wire diameters and 9 types of wires, and when different types of core wires are connected, there are always differences in the line operation attenuation at the Nyquist frequency and the peak of the received waveform. The peak value voltage may not be proportional to the current value, and optimal line equalization is not necessarily performed. 3 Transversal equalization circuit.

. . . As shown in FIG. 2, a transversal filter 3, an intersymbol interference detection circuit 4, and a tap control circuit 5 for adjusting the weighting of the transversal filter based on the output of the circuit 4 are used. The transversal weighting tap amount formed by the delay circuit is controlled so that the intersymbol interference becomes zero.

This method enables nearly optimal line equalization for lines with any frequency characteristics. However, on the other hand, the number of circuit elements increases, resulting in poor economic efficiency. In order to solve these drawbacks, the present invention adds a function for bringing the amount of intersymbol interference close to zero to the gradient AGC circuit system, and will be described in detail below with reference to the drawings.

FIG. 3 shows a block diagram of the present invention.

In the figure, numeral 6 is an input terminal, 1 is a variable line equalization circuit that is predetermined to have an approximate frequency characteristic that is opposite to the loss characteristic that is considered to be the average line frequency characteristic, and 7 is a stream wave. 2 is a peak detection circuit for detecting the peak value of the output waveform of the waveform generator 7, and 8 is a crotch extraction circuit for the waveform generator 7. 9 is an intersymbol interference detection circuit for detecting intersymbol interference in the output waveform from the waveform generator 7 using the clock. represents something. Reference numeral 10 denotes a peak value change judgment circuit, which includes a storage circuit 11 that temporarily stores the output voltage value of the peak detection circuit 2 and outputs the output voltage value of the peak detection circuit 2 after a certain period of time; a subtraction circuit 11' that subtracts the output value of the circuit 2 and the output value of the storage circuit 11; and the subtraction circuit 11'.
The switch drive circuit 11'' operates a switch 12 described later when the output value approaches zero. 12 is a switch which has a circuit configuration of only a slope AGC method and a mechanism for bringing the amount of intersymbol interference close to zero. 13 is an adder for adding the output signal of the intersymbol interference amount detection circuit 9, the output signal of the storage circuit 11, and the output signal of the peak detection circuit 2. ing.

A) General operation explanation.

If the switch 12 is set to the state shown in the figure, when an input waveform distorted due to line frequency loss characteristics is inserted into the input terminal 6, the variable line equalization circuit 1, the waveform generator 7, and the peak detection circuit 2 , passes through the loop of adder 13.

This is exactly the same as the conventional slope AGC method. It is obvious that a certain degree of eye opening can be obtained by this tilted AGC method. FIG. 4 shows an example in which the eye opening ratio (equity) in this case is expressed with the distance as the horizontal axis. However, if only the slope AGC method is applied to the subscriber line cable, the core wire type (0.32,
It is not possible to cover all five types (0.4, 0.5, 0.65, 0.9), and in the case of subscriber line cables, dissimilar core wires are connected in most cases, so the list is slanted. It is necessary to adjust the AGC method by adding a function that brings the amount of intersymbol interference closer to zero.

In order to know the information when the operation has finished in the slope AGC method, the output voltage value of the peak detection circuit 2 is temporarily inserted into the memory circuit 11, and after a certain period of time, the output voltage value obtained by reading the memory circuit 11 and the peak at that time are By taking the difference from the output voltage value of detection circuit 2, when this difference approaches zero, switch 1 is activated.
2, the function of bringing the amount of intersymbol interference closer to zero is activated, and the memory contents of the memory circuit 11 are retained. The circuit configuration when the function of bringing the amount of intersymbol interference close to zero is activated will be described below. That is, variable line equalization circuit 1, wave wave generator 7
, an intersymbol interference detection circuit 9, a clock extraction circuit 8, a storage circuit 11, a switch 12, and an adder 13. By using the slope AGC method, the amount of intersymbol interference is brought to zero by the peak voltage value held in the storage circuit 11 and the output 15 of the intersymbol interference amount detection circuit 9. The details of this intersymbol interference amount detection circuit 9 will be described later, but this intersymbol interference amount detection circuit 9 has a configuration as shown in FIG. 7 and will be described later. good. That is, (1) the threshold level Ethl (% of peak voltage) for detecting "1" or "O" in the code sequence is
As shown in the figure, the absolute value of the waveform voltage 1pI is equal to the absolute value 1Et of the above threshold level.
The circuit section 19- sets it to "0" if it becomes lower than h11.
1, 19-2 (11) In order to keep the amount of intersymbol interference below the allowable amount, the absolute value of the threshold level is set to 1E as shown in Figure 8.
th21 is set as 1Eth21+0Cv] to 1Eth1, and the wave voltage 1Vp1 is set to the above threshold level 1E.
The circuit section 19 sets it to "O" if it becomes lower than th21.
-3, 19-4, (111) By the output from each of the above circuit sections 19,
(a) When Vp≧Ethl... In this case, the intersymbol interference amount detection circuit 9 does not operate.

In other words, since the eye is initially opened to some extent by the above-mentioned slope AGC circuit, it is processed as a series of [1's]. (b) In the case of 1p1<1Eth11...
...In this case, the intersymbol interference amount detection circuit 9 operates, and 1
Regarding the waveform 'voltage Vp' at the time after the time slot, ' (b-1) If 1Vp1≧1Eth21, the eye opening ratio will be poor (the amount of intersymbol interference is large), so to prevent this, 'Vp≦ - When Eth2, the up/down counter (DOw in Figure 7 20)
One pulse is input to the n input, one pulse is input to the Up input of the up/down counter when 'p≧Eth2, and (b-2) Vp<Eth2l
In this case, since the eye opening ratio is within the specified level Eth2, the eye opening ratio is less than the satisfied value, so the configuration is such that no pulse is given to the input of the up/down counter, and 0ψ D/A from the output of the up/down counter above
The converter is configured to output an analog output 15.

As shown in FIG.
and is added to the control input of the variable line equalization circuit 1. In other words, in the case of only peak detection, only a type of predictive equalization is performed, and line equalization is not performed by directly detecting the eye aperture ratio (amount of intersymbol interference).
Therefore, if only peak detection is used, the amount of intersymbol interference increases when multiple line types exist, but as mentioned above,
After performing peak detection and once opening the eye, this peak detection level is then stored in a storage circuit, intersymbol interference is detected, converted to a voltage level, and added to the contents of the storage circuit. The variable line equalization circuit 1 is controlled using the variable line equalization circuit 1. For this reason, the peak detection voltage does not have a one-to-one correspondence in advance to the line approximation characteristic gain, which is opposite to the line frequency characteristic loss. It is possible to reduce the In the case of a preset type automatic equalizer with a fixed pattern,
Although it is possible to remove the circuit configuration using only the slope AGC method, since the code sequences that are normally transmitted are uncorrelated with each other, after opening the eye aperture to some extent with the circuit configuration using only the slope AGC method, the amount of intersymbol interference can be determined. It is better to switch to a circuit configuration that has a function to bring the value closer to zero, and has the advantage of shortening the loop convergence time. B) Each circuit function and a specific example.

1) Variable line equalizer 1.

FIG. 5 shows an embodiment of a variable line equalizer 1 using an FET (field effect transistor) 17.

As is known, a field effect transistor has a characteristic that the resistance value between the drain and the source changes by changing the gate voltage c. From this, by changing the gate voltage Vc, it is possible to change the gain characteristics of the primary RC as shown in FIG. Note that it is possible to use not only the transistor FET but also a diode or other photocoupler. 11) Intersymbol interference amount detection circuit 9.

FIG. 7 shows an embodiment of the intersymbol interference detection circuit 9, and FIGS. 8A to 8D show operation time charts.

Input waveform 16 is converted to logic levels by comparator group 19. Note that the reference voltages Ethl and Et of the comparator group 19
h2, -Ethl, -Eth2 are inputted from the output voltage of the peak detection circuit 2. In FIG. 8, waveform 4 represents an under-equalized waveform, waveform 3 represents an appropriate waveform, and waveforms 6 and 9 represent over-equalized waveforms, and are shown as having one positive pulse input at timing TO. . In the case of under-equalized waveform 4. As shown in the time chart of FIG. A pulse is generated only on the output side of the gate, and one pulse is input to the Up pulse input of the up-down counter 20.Here, the condition for generating one pulse is A) above.
As explained in terms (1) and (4), the input waveform 16 obtained in relation to the threshold level in the intersymbol interference amount detection circuit
This is a case where the data signal changes from a logic 1 to a logic 0, or a case where the data signal changes from a logic 1 to a logic 0 and the logic 0 continues.
Therefore, the up-down counter 20 counts up the value "1".

In response, the output voltage of the DA converter increases from the previous state by the voltage corresponding to count 1, and the memory circuit 11
The control voltage of the variable line equalizer 1 is obtained by adding it to the output voltage of the variable line equalizer 1. For over-equalized waveform 6.

(The difference from the case of waveform 9 can be considered as follows. In other words, when there are three or more points passing through threshold Eth2 within one time slot, it is waveform 9, and when there are two points, it is waveform 6.) . As shown in the time chart in Figure 8C, the D-type FF (
Ho, he, ho', ~, 卜, 卜○, AND, OR gate (nu, nu', ru, o, wa, force), AND gate (force)
A pulse is generated only on the output side of the up-down counter 2.
One pulse is input to the 0 DOwn pulse input.
For over-equalized waveform 9.

As shown in the time chart in Figure 8D, D-type FF and AN
For the D and OR gates, all shown in Figure 7 are used, and D type FF is used.
By (ch, chi', r), -E within one time slot
Determine whether there are 3 or more points that pass the th2 threshold,
In some cases, a pulse is generated only on the output side of the AND gate (power) by the AND/OR gate (W, V), and the pulse is input to the DOwn pulse input of the up/down counter 20. Based on the above operation, the up-down counter accumulates a memory amount and converts this amount into analog, thereby making it possible to bring the amount of intersymbol interference on the waveform close to zero.

111) Clock extraction circuit 8.

The extraction circuit extracts the clock included in the input waveform component that has passed through the wave generator 7, and may be a general-purpose one.

As an example, a DPLL or the like can be used. ! ) Storage circuit 110 In the case of analog memory, CCD (ChargecOup
leddevice), etc. can be used.

v) Peak detection circuit 2. The peak value of the output waveform of the waveform generator 7 is detected and a reference voltage is supplied to the intersymbol interference detection circuit 9.

As explained above, the circuit configuration is such that after setting the amount of intersymbol interference to a certain value using the gradient AGC circuit, the amount of intersymbol interference is controlled to be close to zero, so there are the following advantages.
(1) Operates regardless of the receiving human power pattern.

(2) Compared to the transversal type, which keeps the amount of intersymbol interference close to zero, the number of hardware elements is extremely small.

(3) Although the tilted AGC circuit is effective for one type of core wire, the amount of intersymbol interference remains when there are many types of cables such as subscriber lines or line characteristics such as connections between different core wires. This can be prevented if the

[Brief explanation of drawings]

Figure 1 is a conventional slope AGC circuit, Figure 2 is a conventional transversal automatic equalization circuit, Figure 3 is an operational block diagram of the present invention, Figure 4 is the eye opening ratio of the slope AGC circuit, and Figure 5 is FIG. 3 shows an embodiment of the variable line equalization circuit 1, FIG. 6 shows the frequency characteristics with respect to the control voltage Vc shown in FIG. D
is the operation time chart of FIG. DESCRIPTION OF SYMBOLS 1...Variable line equalization circuit, 2...Peak detection circuit, 3...Transversal filter, 4...Intersymbol interference detection circuit, 5...・・・・・・
Tap control circuit, 6... Input terminal, 7...
...Sawa wave device, 8...Clock extraction circuit, 9...
. . . Intersymbol interference amount detection circuit, 10 . . . Peak value change judgment circuit, 11 . . . Memory circuit, 1V.
... Subtraction circuit, 111 ... Switch 5 drive circuit, 12 ... Switch, 13 ... Adder, 14 ... Output terminal, 15 ... ... Output of undersufficiency/sufficient equalization detection circuit, 16... Input of 9, 17... Variable resistor (FET), 18...
... Output of clock extraction circuit, 19, 19-1, 19
-2, 19-3, 19-4... Comparator, 20.
...Up-down counter, 21...D
A converter.

Claims (1)

[Claims] 1. In an automatic equalizer that compensates for waveform distortion due to line frequency characteristic distortion, a variable line equalization circuit that has a line approximation frequency characteristic gain that is opposite to the line frequency characteristic loss, a filter for band limitation or waveform shaping, A peak detection circuit that detects the peak value of the output waveform of the filter, a clock extraction circuit that extracts the clock included in the input waveform component from the filter, and an output waveform from the filter using the clock of the clock extraction circuit. an intersymbol interference detection circuit for detecting intersymbol interference; a storage circuit for temporarily holding the output voltage value of the peak detection circuit; and subtraction of the output value of the peak detection circuit and the output value of the storage circuit. A peak value change judgment circuit judges the change in the output of the peak detection circuit when the result of subtraction approaches zero, and after detecting that the peak value approaches a constant level from the output of the peak value change judgment circuit, the contents held in the storage circuit are A switch for switching from the output of the peak detection circuit to the output of the intersymbol interference amount detection circuit and the output of the storage circuit, and for adding the output signal of the intersymbol interference amount detection circuit, the output signal of the storage circuit, and the output signal of the peak detection circuit. When the peak value is not constant, the output signal of the peak detection circuit is fed back to the variable line equalization circuit, and the peak value is detected from the output of the peak value change judgment circuit. The state in which the value becomes constant is characterized in that the summed output signal of the output signal of the intersymbol interference amount detection circuit and the output signal of the storage circuit is fed back to the variable line equalization circuit to perform line equalization. Automatic equalizer.