JPS592391B2 - Josephson junction device and its manufacturing method - Google Patents

Josephson junction device and its manufacturing method

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Publication number
JPS592391B2
JPS592391B2 JP55181046A JP18104680A JPS592391B2 JP S592391 B2 JPS592391 B2 JP S592391B2 JP 55181046 A JP55181046 A JP 55181046A JP 18104680 A JP18104680 A JP 18104680A JP S592391 B2 JPS592391 B2 JP S592391B2
Authority
JP
Japan
Prior art keywords
thin film
superconductor thin
belt
shaped
shaped superconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55181046A
Other languages
Japanese (ja)
Other versions
JPS57104282A (en
Inventor
浩 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RIKEN Institute of Physical and Chemical Research
Original Assignee
RIKEN Institute of Physical and Chemical Research
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RIKEN Institute of Physical and Chemical Research filed Critical RIKEN Institute of Physical and Chemical Research
Priority to JP55181046A priority Critical patent/JPS592391B2/en
Priority to US06/315,505 priority patent/US4494131A/en
Priority to DE19813142949 priority patent/DE3142949A1/en
Priority to FR8120406A priority patent/FR2493605B1/en
Publication of JPS57104282A publication Critical patent/JPS57104282A/en
Priority to US06/540,811 priority patent/US4539741A/en
Publication of JPS592391B2 publication Critical patent/JPS592391B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/12Josephson-effect devices

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳細な説明】 本発明は、特性が均一でつくり易いジョセフソン接合素
子の構造とその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a Josephson junction element that has uniform characteristics and is easy to manufacture, and a method for manufacturing the same.

ジョセフソン接合素子の応用範囲は広く、小電力超高速
スイッチングの電算機用素子として、マイクロ波、ミリ
波などの高感度高速度応答の検出器として、人間の脳や
心臓から放射される微弱磁場の検出器として、あるいは
電圧標準器として使用することが提案されており、その
工業化に対する要請が日ましに増大している。本発明者
は先に、ジョセフソン接合素子の弱結合部を極限まで短
縮してその特性を改善することを可能とし、しかも容易
に同一特性の素子を大量生産し得るジョセフソン接合素
子の構成(準平面型ジョセフソン接合素子)を提案した
(特公昭55−7712号)。
Josephson junction devices have a wide range of applications, including as low-power, ultra-high-speed switching computer devices, as detectors for high-sensitivity, high-speed response to microwaves, millimeter waves, etc., and for use in weak magnetic fields emitted from the human brain and heart. It has been proposed to use it as a detector or as a voltage standard, and the demand for its industrialization is increasing day by day. The present inventor has previously discovered a configuration of a Josephson junction element that makes it possible to shorten the weak coupling part of the Josephson junction element to the utmost limit and improve its characteristics, and also to easily mass-produce elements with the same characteristics. proposed a quasi-planar Josephson junction device (Japanese Patent Publication No. 7712/1983).

第1図に示すように準平面型ジョセフソン接合素子では
基板1上に二つの超伝導体層2、3が絶縁体層4を介し
て部分的に向かい合いそしてこの絶縁体層4を横切つて
弱結合部5が上下の超伝導体層2、3にまたがつている
。このような構成としたので弱結合部の長さは極めて薄
い絶縁体層4の厚みに等しくなり、それ故弱結合部の長
さは絶縁体層を形成するときの絶縁物質のスパッタリン
グ又は蒸着時間を調整することによつて極めて小さくし
かも精確に制御し得る。実際には、数百〜数千λ程度の
厚さの超伝導体薄膜2の上に5102などの絶縁物質又
は半導体をスパッタリングすることにより、或いは超伝
導層2の表面を酸化性雰囲気中で酸化することにより数
百入程度の厚さの絶縁体層4を形成する。絶縁体層4の
厚みを横切つて上下超伝導薄膜にまたがつて数百人ない
し数千人の厚さに適当な障壁物質を蒸着して弱結合部5
を形成する。このようにして上下超伝導体層2,3を接
続する弱結合部5の長さは絶縁体層4の厚みとなり、要
求されるインピーダンスの大きさに応じて数百人ないし
数千人の範囲の適正値を選択することができる。このよ
うな構造としたことにより1電極部の超伝導体層2,3
の膜厚を大きく保つたま\で、弱結合部の長さを極端に
短かくでき、それによりImRj積を著しく大きくする
ことができ、2弱結合部に種々の材質を使用でき、3静
電容量を小さくでき、4上記超伝導体層3に鉛合金以外
のNb等を用いて長寿命とすることができ、そして5フ
オトリソグラフイや電子ビームリソグラフイを用いて容
易に量産することができるようになつたのである。
As shown in FIG. 1, in a quasi-planar Josephson junction device, two superconductor layers 2 and 3 are placed on a substrate 1, partially facing each other with an insulator layer 4 in between, and extending across the insulator layer 4. A weak coupling portion 5 spans the upper and lower superconductor layers 2 and 3. With this configuration, the length of the weak bond is equal to the thickness of the extremely thin insulator layer 4, and therefore the length of the weak bond is determined by the sputtering or evaporation time of the insulating material when forming the insulator layer. can be extremely small and precisely controlled by adjusting the . Actually, by sputtering an insulating material or semiconductor such as 5102 onto the superconductor thin film 2 with a thickness of several hundred to several thousand λ, or by oxidizing the surface of the superconducting layer 2 in an oxidizing atmosphere. By doing so, an insulator layer 4 having a thickness of about several hundred layers is formed. A suitable barrier material is deposited across the thickness of the insulating layer 4 and across the upper and lower superconducting thin films to a thickness of several hundred to several thousand layers to form a weak coupling portion 5.
form. The length of the weak coupling portion 5 that connects the upper and lower superconductor layers 2 and 3 in this way is the thickness of the insulator layer 4, and ranges from several hundred to several thousand depending on the required impedance. An appropriate value can be selected. With this structure, the superconductor layers 2 and 3 of one electrode part
While maintaining a large film thickness, the length of the weak coupling part can be extremely shortened, thereby making it possible to significantly increase the ImRj product, allowing the use of various materials for the weak coupling part, and reducing electrostatic 4. The superconductor layer 3 can have a long life by using Nb, etc. other than lead alloy, and 5. It can be easily mass-produced using photolithography or electron beam lithography. It became like this.

この準平面型ジヨセフソン接合素子の主な特性のうち、
静電容量は絶縁体層4を挟んで対申している部分の超伝
導体層2,3の面積AXbによつて左右され、この面積
AXbを小さくする程静電容量は小さくなる。
Among the main characteristics of this quasi-planar Josephson junction device,
The capacitance depends on the area AXb of the superconductor layers 2 and 3 facing each other with the insulator layer 4 in between, and the smaller the area AXb, the smaller the capacitance becomes.

また、接合抵抗Rjは絶縁体層4の厚み側面を横切つて
いる部分の弱結合部5の幅Cによつて左右され、幅Cを
小さくする程接合抵抗Rjは大きくなる。つまり、準平
面型ジヨセフソン接合素子の特性の主なバラツキ(不均
一性)は、面積a><.bの精度と幅Cの精度すなわち
フオトリソグラフイ又は電子ビームリソグラフイを使用
する際のマスク合せの精度によつて決まるといえる。と
ころで、第1図からも明らかなように、準平面型ジヨセ
フソン接合素子では、マスク合せの(XまたはY方向の
)ずれが面積AXbの精度に直接影響する構造であり、
結果として、素子の特性(静電容量)がバラツキ易い。
Further, the junction resistance Rj is influenced by the width C of the weak coupling portion 5 that crosses the thickness side of the insulating layer 4, and the smaller the width C is, the greater the junction resistance Rj becomes. In other words, the main variation (non-uniformity) in the characteristics of the quasi-planar Josephson junction element is the area a><. It can be said that it is determined by the precision of b and the precision of width C, that is, the precision of mask alignment when using photolithography or electron beam lithography. By the way, as is clear from FIG. 1, the quasi-planar Josephson junction element has a structure in which misalignment of the mask alignment (in the X or Y direction) directly affects the accuracy of the area AXb.
As a result, the characteristics (capacitance) of the elements tend to vary.

また、静電容量を小さくししかも接合抵抗を大きくする
ために、例えばa及びbが数μm程度の微小な面積のと
ころに、幅Cが1μm以下の弱結合部5を形成するため
には、非常に高いマスク合せの精度が要求され、極めて
製造が困難である。本発明はこの準平面型ジヨセフソン
接合素子のマスク合せ精度による特性のバラツキを少な
くしつくり易くすることを目的としている。
Furthermore, in order to reduce the capacitance and increase the junction resistance, for example, in order to form a weak coupling portion 5 with a width C of 1 μm or less in a minute area where a and b are about several μm, This requires extremely high precision in mask alignment and is extremely difficult to manufacture. It is an object of the present invention to reduce variations in characteristics of this quasi-planar Josephson junction element due to mask alignment accuracy and to facilitate fabrication.

この目的は、二つの帯状の超伝導体薄膜を絶縁体層を介
して交差させ、この交差領域の相対する各縁において絶
縁体層の厚み側面を横切つて上下の超伝導体薄膜を一つ
の線状の弱結合部で結合させることによつて達成される
The purpose of this is to intersect two strip-shaped superconductor thin films through an insulator layer, and at each opposing edge of this crossing region, cross the thickness side of the insulator layer to combine the upper and lower superconductor thin films into one. This is achieved by coupling with a linear weak bond.

また、この目的は、絶縁体層を介して交差させた二つの
帯状の超伝導体薄膜の下側の超伝導体薄膜の幅よりも狭
い間隔をおいて平行に延びる複数の線状の、レジストマ
スク又は窓を有するレジストマスクを用いて、弱結合部
を形成する方法によつて達成される。
In addition, for this purpose, two strip-shaped superconductor thin films are intersected with each other with an insulating layer interposed between them. This is achieved by a method of forming a weak bond using a mask or a resist mask with windows.

以下に本発明の実施例を詳しく説明する。Examples of the present invention will be described in detail below.

第2図は本発明のジヨセフソン接合素子の一実施例を示
す拡大平面図である。第3図は第2図の斜視図である。
第2,3図に示すように、基板1上にの/びる帯状の超
伝導体薄膜2の上に絶縁体層4を配置し、別の帯状の超
伝導体薄膜3を下方の超伝導体薄膜2を横切つて絶縁体
層4の上に配置している。
FIG. 2 is an enlarged plan view showing one embodiment of the Josephson junction element of the present invention. FIG. 3 is a perspective view of FIG. 2.
As shown in FIGS. 2 and 3, an insulator layer 4 is disposed on a strip-shaped superconductor thin film 2 extending over a substrate 1, and another strip-shaped superconductor thin film 3 is placed on the superconductor thin film 2 below. It is disposed across the thin film 2 and on top of the insulator layer 4.

この上下両超伝導体薄膜2,3の交差領域の相対する各
縁において、上下の超伝導体層間で露出する絶縁体層4
の厚み側面4′,4″を横切つて上下の超伝導体薄膜を
結合して延びる一つの線状の障壁物質の膜を形成し弱結
合部5をつくる。このように、二つの帯状の超伝導体薄
膜を絶縁体層を介して交差させているので、素子の静電
容量の大きさは帯状の超伝導体薄膜の幅a又はbにより
決定することができ、従つてこの幅を正しい寸法に形成
しておけば、この交差領域の面積AXbは超伝導体薄膜
2,3の位置がずれても変らないので、フオトリソグラ
フイ又は電子ビームリソグラフイにおけるマスク合せの
位置精度にそれほどの厳格さは要求されない。したがつ
て、静電容量の均一な素子を極めて容易につくることが
できる。
At each opposing edge of the intersection area of the upper and lower superconductor thin films 2 and 3, an insulator layer 4 exposed between the upper and lower superconductor layers
A linear barrier material film is formed which extends across the thickness sides 4' and 4'' of the upper and lower superconductor thin films to form a weak coupling part 5. In this way, two strip-shaped Since the superconductor thin films intersect with each other through the insulator layer, the capacitance of the device can be determined by the width a or b of the strip-shaped superconductor thin film. If formed to the same dimensions, the area AXb of this intersection region will not change even if the positions of the superconductor thin films 2 and 3 are shifted, so there is no need to be so strict about the positional accuracy of mask alignment in photolithography or electron beam lithography. Therefore, an element with uniform capacitance can be produced extremely easily.

このジヨセフソン接合素子の作動に当つては上下の超伝
導体薄膜間の最短距離である絶縁体層の両側面4′,4
7を通つて超伝導電流が流れる″ので、これを2個の準
平面型ジヨセフソン結合素子の並列接続で等価的に表わ
すことができる(第4図)。
In the operation of this Josephson junction element, the shortest distance between the upper and lower superconductor thin films is on both sides of the insulator layer 4', 4.
Since a superconducting current flows through 7'', this can be equivalently represented by two quasi-planar Josephson coupling elements connected in parallel (FIG. 4).

すなわち素子の臨界電流1mは準平面型ジヨセフソン接
合素子の臨界電流の2倍となり、接合抵抗Rjは準平面
型ジヨセフソン接合素子の接合抵抗の%倍となつて、結
局MRj積は準平面型ジヨセフソン接合素子のImRj
積と同一となる。従つて準平而型ジヨセフソン接合素子
と同等の優れた特性を保持する。本発明のジヨセフソン
接合素子の製造方法について述べる。
In other words, the critical current 1 m of the device is twice the critical current of the quasi-planar Josephson junction element, and the junction resistance Rj is % times the junction resistance of the quasi-planar Josephson junction element, so that the MRj product is ultimately the same as that of the quasi-planar Josephson junction element. ImRj of the element
It is the same as the product. Therefore, it maintains excellent characteristics equivalent to quasi-planetary Josephson junction elements. A method of manufacturing the Josephson junction device of the present invention will be described.

先ず基板1上にマスクを使用して第1の帯状の超伝導体
薄膜2をつくる。
First, a first strip-shaped superconductor thin film 2 is formed on a substrate 1 using a mask.

この超伝導体薄膜は、Nb,Ta,W,La,Pb,S
nJn,Alなどの金属あるいはそれらの合金など超伝
導性を示す各種の超伝導物質からなる。第5図を参照す
る。フオトリソグフフイ又は電子ビームリソグラフイに
よりレジストマスクM1を基板1上につくり(第5図A
)、このマスクM1を通して超伝導物質を数百ないし数
千への厚さにスパツタリング又は蒸着し、次にマスクを
取除いて帯状のパターン(第1の帯状伝導体薄膜2)を
残す(第5図B)。このパターンの両端は外部接続を容
易にするため拡大しておく。次でこの第1の帯状超伝導
体薄膜2に交差して帯状の窓をもつレジストマスクM2
を配置し(第5図C)、SiO2などの絶縁物質又は半
導体物質を五十八ないし数千への厚さにスパツタリング
又は蒸着し、それから超伝導物質を数百ないし数千人の
厚さにスパツタリング又は蒸着し、その後マスクを取除
いて帯状のパターン(第2の帯状超伝導体薄膜3)を残
す(第5図D)。次に、全面をスパツタークリーニング
して酸化膜を超伝導体表面から取除く。それから、全面
に障壁物質を数千λの厚さにスパツタリング又は蒸着す
る。次いで、その帯状パターンの交差領域に、第1の帯
状超伝導体薄膜2の幅aよりも狭い間隔dをおいて平行
にのびる複数の線状のレジストマスクM3をつくる(第
5図E)。化学エツチングによりマスクされていない障
壁物質を取除く(第5図F)。最後に、レジストマスク
M3を取除いて完成する(第5図G)。なお、第5図E
,F,Gの製造工程を第6図A,B,Cの製造工程にお
きかえてもよい。
This superconductor thin film consists of Nb, Ta, W, La, Pb, S
It is made of various superconducting materials that exhibit superconductivity, such as metals such as nJn and Al, or alloys thereof. Please refer to FIG. A resist mask M1 is made on the substrate 1 by photolithography or electron beam lithography (see Fig. 5A).
), the superconducting material is sputtered or evaporated to a thickness of several hundred to several thousand through this mask M1, and then the mask is removed to leave a band-shaped pattern (first band-shaped conductor thin film 2) (fifth Figure B). Both ends of this pattern are enlarged to facilitate external connections. Next, a resist mask M2 having a band-shaped window crossing this first band-shaped superconductor thin film 2 is formed.
(Figure 5C), sputtering or evaporating an insulating or semiconducting material such as SiO2 to a thickness of 58 to several thousand, and then sputtering or depositing a superconducting material to a thickness of several hundred to several thousand. Sputtering or vapor deposition is performed, and then the mask is removed to leave a band-shaped pattern (second band-shaped superconductor thin film 3) (FIG. 5D). Next, the entire surface is sputter cleaned to remove the oxide film from the superconductor surface. Then, a barrier material is sputtered or deposited over the entire surface to a thickness of several thousand λ. Next, a plurality of linear resist masks M3 extending in parallel at intervals d narrower than the width a of the first strip-shaped superconductor thin film 2 are formed in the intersecting regions of the strip-shaped patterns (FIG. 5E). Remove the unmasked barrier material by chemical etching (Figure 5F). Finally, the resist mask M3 is removed to complete the process (FIG. 5G). Furthermore, Figure 5E
, F, and G may be replaced with the manufacturing steps shown in FIGS. 6A, B, and C.

第1の帯状の超伝導体薄膜2の幅aよりも狭い間隔dを
おいて平行に延びる複数の線状の窓6を有するレジスト
マスクM4を、第1の帯状の超伝導体薄膜2に対して配
置し(第6図A)、全表面をスパツタクリーニングした
後にレジストマスクM4の窓6を通して弱結合物質をス
パツタリング又は蒸着する(第6図B)。次いで、レジ
ストマスクM4を取除くとその上の弱結合物質が剥れ(
リフトオフされ)、接合素子が完成する。(第6図C)
。上記の製法においては、第1の帯状の超伝導体薄膜の
幅aよりも狭い間隔dをおいて平行に延びる複数線状の
、レジストマスクM3又は窓を有するレジストマスク鳩
を用いて(第5図E又は第6図A)いることが重要であ
る。すなわち、d〈aにしておけば、両超伝導体薄膜2
,3の交差領域に1本の弱結合部4を形成する確率(歩
留りN)は一例として、a=d+2cの場合、で表わさ
れるので、歩留り良く1本の弱結合部を容易に形成する
ことができる。
A resist mask M4 having a plurality of linear windows 6 extending in parallel at intervals d narrower than the width a of the first strip-shaped superconductor thin film 2 is applied to the first strip-shaped superconductor thin film 2. (FIG. 6A), and after sputter cleaning the entire surface, a weakly bonding material is sputtered or evaporated through the window 6 of the resist mask M4 (FIG. 6B). Next, when the resist mask M4 is removed, the weak bonding material on it peels off (
(lifted off) to complete the bonding element. (Figure 6C)
. In the above manufacturing method, a resist mask M3 having a plurality of lines extending in parallel at an interval d narrower than the width a of the first strip-shaped superconductor thin film or a resist mask pigeon having a window is used (fifth Figure E or Figure 6A) is important. That is, if d<a, both superconductor thin films 2
, 3, the probability (yield N) of forming one weak coupling part 4 in the intersection area of 3 is expressed as, for example, when a=d+2c, so one weak coupling part 4 can be easily formed with a high yield. I can do it.

例えば、第7図に拡大して示すように、a=4μMld
=3.6μMlc=0.2μmの場合、約84%の歩留
りが得られる。X印が2本の弱結合部が形成されている
場合でその割合は3/19であり、1本の場合は16/
19″.0.84であり、土式から得られる歩留りと一
致する。このように、d<aにした複数本の線状のレジ
ストマスクM3又は窓を有するレジストマスクM4を用
いることにより、そのマスク合せの位置精度をあまり必
要とせずに、幅cの小さい弱結合部を両超伝導体薄膜の
交差領域に歩留り良く容易に形成することができる。
For example, as shown enlarged in FIG. 7, a=4μMld
When =3.6μMlc=0.2μm, a yield of about 84% is obtained. When two weak bonds are formed, the ratio is 3/19, and when there is one, the ratio is 16/
19".0.84, which is consistent with the yield obtained from the soil method. In this way, by using a plurality of linear resist masks M3 with d<a or a resist mask M4 having windows, the yield can be improved. A weak coupling portion with a small width c can be easily formed at a high yield in the intersection region of both superconductor thin films without requiring much positional accuracy in mask alignment.

そのため接合抵抗Rjの大きい接合素子の量産が容易と
なる。なお、交差領域以外に形成された弱結合部5は、
両超伝導体2,3を結合していないので接合素子の特性
への影響は全くない。
Therefore, mass production of junction elements with a large junction resistance Rj becomes easy. Note that the weak coupling portion 5 formed outside the intersection area is
Since both superconductors 2 and 3 are not bonded together, there is no effect on the characteristics of the junction element.

更に上記の製法においては第1の帯状超伝導体薄膜2に
交差してレジストマスクM2を配置し(第5図C)、絶
縁物質をスパツタリング又は蒸着し、それから同じマス
クM2を使用して超伝導物質をスパツタリング又は蒸着
している。
Furthermore, in the above manufacturing method, a resist mask M2 is placed across the first strip-shaped superconductor thin film 2 (FIG. 5C), an insulating material is sputtered or vapor-deposited, and then the same mask M2 is used to form a superconductor. Sputtering or vapor depositing a substance.

このように第1の帯状超伝導体薄膜2に交差して絶縁物
質をスパツタリング又は蒸着することが重要である。も
しこれと逆に第1の帯状超伝導体薄膜2をつくつたマス
クM1を利用して第1の帯状超伝導体薄膜2の全面に重
ねて絶縁物質薄膜をつけると素子の製造上著しい不都合
を生じる。すなわち弱結合部をつくる前に上下の超伝導
体薄膜の重なり合う交差領域以外の部分から下の超伝導
体薄膜表面を損傷せずに絶縁物質のみを選択的にスパツ
タエツチングにより取除くことは極めて困難だからであ
る。又、全面をスパツタークリーニングして酸化膜を超
伝導体表面から取除いているが、この際絶縁体層の厚み
側面の整形も行なわれる。絶縁物質又は半導体物質をス
パツタリング又は蒸着して絶縁体層をつくるが、この絶
縁体層が比較的薄い場合(通常200λ以下)にはピン
ホールを生じて超伝導シヨートを生じることがある。こ
のピンホールを閉塞するには絶縁体層を酸化雰囲気にさ
らして酸化すればよい。絶縁物質又は半導体物質をスパ
ツタリング又は蒸着して絶縁体層をつくる代りに、マス
クM2の窓を通して露出している超伝導体薄膜2の表面
を酸化雰囲気にさらして酸化して絶縁体層としてもよい
It is important to sputter or evaporate the insulating material across the first strip-shaped superconductor thin film 2 in this way. If, on the other hand, a thin film of insulating material is applied over the entire surface of the first strip-shaped superconductor thin film 2 using the mask M1 with which the first strip-shaped superconductor thin film 2 is made, significant inconveniences will occur in the manufacturing of the device. arise. In other words, it is extremely difficult to selectively remove only the insulating material from areas other than the intersection area where the upper and lower superconductor thin films overlap without damaging the underlying superconductor thin film surface by sputter etching before forming a weak bond. This is because it is difficult. Further, the entire surface is sputter cleaned to remove the oxide film from the superconductor surface, and at this time, the thickness side of the insulator layer is also shaped. An insulator layer is formed by sputtering or depositing an insulating or semiconductor material, but if this insulator layer is relatively thin (typically less than 200λ), pinholes may form and superconducting shorts may occur. To close this pinhole, the insulating layer may be oxidized by exposing it to an oxidizing atmosphere. Instead of sputtering or vapor depositing an insulating material or a semiconductor material to form an insulating layer, the surface of the superconductor thin film 2 exposed through the window of the mask M2 may be exposed to an oxidizing atmosphere and oxidized to form an insulating layer. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の準平面型ジヨセフソン接合素子の拡大斜
視図である。 第2図は本発明のジヨセフソン接合素子の拡大平面図で
ある。第3図は第2図の斜視図である。第4図は本発明
のジヨセフソン接合素子の等価回路である。第5図A,
B,C,D,E,F,G及び第6図A,B,Cは本発明
のジヨセフソン接合素子の製造工程を示す。第7図は本
発明の製造法の効果を説明するための拡大説明図である
。図中の符号、1・・・・・・基板、M1〜鳩・・・・
・ルジストマスク、2,3・・・・・・超伝導体薄膜、
4・・・・・・絶縁体層、5・・・・・・弱結合物質の
薄膜、6・・・・・ルジストマスクの窓。
FIG. 1 is an enlarged perspective view of a conventional quasi-planar Josephson junction element. FIG. 2 is an enlarged plan view of the Josephson junction device of the present invention. FIG. 3 is a perspective view of FIG. 2. FIG. 4 is an equivalent circuit of the Josephson junction device of the present invention. Figure 5A,
B, C, D, E, F, G and FIGS. 6A, B, and C show the manufacturing process of the Josephson junction device of the present invention. FIG. 7 is an enlarged explanatory diagram for explaining the effects of the manufacturing method of the present invention. Symbols in the figure, 1... Board, M1 ~ Pigeon...
・Lugist mask, 2, 3... superconductor thin film,
4...Insulator layer, 5...Thin film of weakly bonded substance, 6...Window of rugist mask.

Claims (1)

【特許請求の範囲】 1 絶縁体層を介して交差している二つの帯状の超伝導
体薄膜と、交差領域の相対する各縁において前記の絶縁
体層の厚みの側面を横切つて上下の超伝導体薄膜を結合
して延びる一つの線状の弱結合部とを備えたことを特徴
とするジョセフソン接合素子。 2 基板上に第1の帯状の超伝導体薄膜をつくり、この
第1の帯状の超伝導体薄膜に交差して絶縁体層をつくり
、この絶縁体層に重ねて第2の帯状の超伝導体薄膜をつ
くり、このようにしてつくつた積層薄膜をスパッタクリ
ーニングし、前記の積層薄膜の全面に弱結合物質の薄膜
をつくり、この弱結合物質の薄膜の上に前記の第1の帯
状の超伝導体薄膜の幅よりも狭い間隔をおいて平行に延
びる複数の線状のレジストマスクをつくり、このレジス
トマスクに覆われていない弱結合物質を取除くことを特
徴とするジョセフソン接合素子の製造方法。 3 基板上に第1の帯状の超伝導体薄膜をつくり、この
第1の帯状の超伝導体薄膜に交差して絶縁体層をつくり
、この絶縁体層に重ねて第2の帯状の超伝導体薄膜をつ
くり、そして前記の第1の帯状の超伝導体薄膜の幅より
も狭い間隔をおいて平行に延びる複数の線状の窓を有す
るレジストマスクを前記の第1の帯状の超伝導体薄膜に
対して配置し、表面をスパッタクリーニングした後その
窓を通して弱結合物質をスパッタリング又は蒸着するこ
とを特徴とするジョセフソン接合素子の製造方法。
[Scope of Claims] 1. Two strip-shaped superconductor thin films intersecting with each other with an insulating layer interposed therebetween, and upper and lower layers crossing the sides of the thickness of the insulating layer at each opposing edge of the crossing region. 1. A Josephson junction device comprising: a linear weak coupling portion that connects and extends a superconductor thin film. 2. Create a first belt-shaped superconductor thin film on a substrate, create an insulating layer across this first belt-shaped superconductor thin film, and overlap this insulator layer to form a second belt-shaped superconductor thin film. The laminated thin film thus created is sputter-cleaned to form a thin film of a weakly binding substance on the entire surface of the laminated thin film, and the first belt-shaped superconducting film is formed on the thin film of the weakly binding substance. A method for manufacturing a Josephson junction device, characterized by creating a plurality of linear resist masks extending in parallel at intervals narrower than the width of a body thin film, and removing weakly bonded substances not covered by the resist masks. . 3 Create a first belt-shaped superconductor thin film on a substrate, create an insulator layer across this first belt-shaped superconductor thin film, and overlap this insulator layer to form a second belt-shaped superconductor thin film. A resist mask having a plurality of linear windows extending in parallel at intervals narrower than the width of the first strip-shaped superconductor thin film is applied to the first strip-shaped superconductor thin film. 1. A method of manufacturing a Josephson junction device, comprising sputtering or depositing a weakly bonding material through the window after sputter cleaning the surface of the thin film.
JP55181046A 1980-10-31 1980-12-20 Josephson junction device and its manufacturing method Expired JPS592391B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55181046A JPS592391B2 (en) 1980-12-20 1980-12-20 Josephson junction device and its manufacturing method
US06/315,505 US4494131A (en) 1980-10-31 1981-10-27 Josephson junction element and method of making the same
DE19813142949 DE3142949A1 (en) 1980-10-31 1981-10-29 JOSEPHSON ELEMENT AND METHOD FOR THE PRODUCTION THEREOF
FR8120406A FR2493605B1 (en) 1980-10-31 1981-10-30 JOSEPHSON JUNCTION ELEMENT AND MANUFACTURING METHOD
US06/540,811 US4539741A (en) 1980-10-31 1983-10-11 Josephson junction element and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55181046A JPS592391B2 (en) 1980-12-20 1980-12-20 Josephson junction device and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS57104282A JPS57104282A (en) 1982-06-29
JPS592391B2 true JPS592391B2 (en) 1984-01-18

Family

ID=16093816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55181046A Expired JPS592391B2 (en) 1980-10-31 1980-12-20 Josephson junction device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS592391B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180295U (en) * 1988-06-13 1989-12-25

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180295U (en) * 1988-06-13 1989-12-25

Also Published As

Publication number Publication date
JPS57104282A (en) 1982-06-29

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