JPS5923113B2 - Semiconductor equipment for ultra-high frequencies - Google Patents
Semiconductor equipment for ultra-high frequenciesInfo
- Publication number
- JPS5923113B2 JPS5923113B2 JP53023248A JP2324878A JPS5923113B2 JP S5923113 B2 JPS5923113 B2 JP S5923113B2 JP 53023248 A JP53023248 A JP 53023248A JP 2324878 A JP2324878 A JP 2324878A JP S5923113 B2 JPS5923113 B2 JP S5923113B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- bonding wire
- diameter
- high frequency
- ultra
- Prior art date
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- Expired
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
- H01L2224/48456—Shape
- H01L2224/48458—Shape of the interface with the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20751—Diameter ranges larger or equal to 10 microns less than 20 microns
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明はショットキダイオードなどの超高周波用半導
体装置に係り、特にその電極形状の改良関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to ultra-high frequency semiconductor devices such as Schottky diodes, and particularly to improvements in the shape of electrodes thereof.
以下、ショットキダイオードを例にとり説明する。The following will explain the Schottky diode as an example.
ショットキダイオードは、超高周波帯における制御変換
素子として重要な位置を占めており、そのしや断固波数
ｆｃの高いことが必須条件である。A Schottky diode occupies an important position as a control conversion element in an ultra-high frequency band, and a high wave number fc is an essential condition.
ショットキダイオードの基板のキャリヤ濃度が一定の場
合には、理論的な考察よりショットキダイオードのショ
ットキ接合電極（以下「Ｓ電極」と略称する）の面積が
小さくなるにつれてそのしや断固波数ｆｃも増大するこ
とが解明されているので、最近ではｓ電極の半径が５μ
ｍ程度以下のものまで開発されている。第１図はショッ
トキダイオードのオーバレイ構造のｓ電極を説明するた
めの断面図である。When the carrier concentration of the Schottky diode substrate is constant, theoretical considerations suggest that as the area of the Schottky junction electrode (hereinafter abbreviated as "S electrode") of the Schottky diode becomes smaller, the absolute wave number fc also increases. Since it has been clarified that the radius of the s electrode is 5μ,
Even devices with a size of about m or less have been developed. FIG. 1 is a cross-sectional view for explaining an s-electrode of an overlay structure of a Schottky diode.
図において、１は半導体基板、２は半導体基板１の主面
上に設けられ上記主面の一部を露出させた窓を有する絶
縁保護膜、３は絶縁保護膜２の窓内の半導体基板１上お
よび上記窓の周辺部の絶縁保護膜２上に形成されたｓ電
極、４はｓ電極３上に形成されたボンディング用電極、
５は直径１０μｍ程度の金線からなリボンディング用電
極４上に接続されたボンディングワイヤである。このよ
うなオーバレイ構造のｓ電極では、微少なｓ電極３でも
これとボンディングワイヤ５とを容易に接続できるので
、従来広く使用されていた。In the figure, 1 is a semiconductor substrate, 2 is an insulating protective film provided on the main surface of the semiconductor substrate 1 and has a window exposing a part of the main surface, and 3 is the semiconductor substrate 1 inside the window of the insulating protective film 2. s electrode formed on the insulating protective film 2 on the upper and peripheral parts of the window; 4 is a bonding electrode formed on the s electrode 3;
A bonding wire 5 is connected to the rebonding electrode 4 made of a gold wire with a diameter of about 10 μm. Such an s-electrode having an overlay structure has been widely used in the past because even a minute s-electrode 3 can be easily connected to the bonding wire 5.
しかしながら、ｓ電極３の絶縁保護膜２上にはみ出たオ
ーバレイの部分と半導体基板１との間に、絶縁保護膜２
の厚さと誘電率とで決まる容量が形成され、この容量が
、ｓ電極３の接合容量Ｃｊと並列に入るため、高周波特
性に悪影響を及ぽしていた。これに対して、オーバレイ
の無い構造のｓ電極では、これを例えばメッキ法などに
より形成することが可能であり、浮遊容量をほとんど無
視できるものの、微少なＳ電極ではこれとボンデイング
ワイヤとを接続することが容易ではないという問題点が
ある。However, between the overlay portion of the s electrode 3 that protrudes onto the insulating protective film 2 and the semiconductor substrate 1, the insulating protective film 2
A capacitance determined by the thickness and dielectric constant of the s-electrode 3 is formed, and this capacitance enters in parallel with the junction capacitance Cj of the s-electrode 3, thereby adversely affecting the high frequency characteristics. On the other hand, in the case of an S electrode with a structure without overlay, it is possible to form this by, for example, a plating method, and the stray capacitance can be almost ignored. The problem is that it is not easy.
次に、この問題点について具体的に説明する。Next, this problem will be specifically explained.
通常、ボンデイングワイヤを直接接続する要のあるＳ電
極の形状は、シヨツトキ接合電界効果トランジスタのゲ
ート電極などを例外として除くと次の理由により円形で
ある。すなわち、半導体基板のＳ電極の周辺部において
、Ｓ電極の逆方向リーク電流が発生し易いため、Ｓ電極
の周囲長をできるだけ短かくすることが望ましく、同一
面積であれば、最小の周囲長をもつ円が専ら用いられて
きたのである。一方、ボンデイングワイヤは、その径が
１０μｍ程度以上ないと非常に切れ易く、実用上使用す
ることができない。Generally, the shape of the S electrode to which a bonding wire must be directly connected is circular for the following reason, with the exception of the gate electrode of a shotgun field effect transistor. In other words, since reverse leakage current of the S electrode is likely to occur in the peripheral area of the S electrode of the semiconductor substrate, it is desirable to make the peripheral length of the S electrode as short as possible. The motsu yen has been used exclusively. On the other hand, unless the bonding wire has a diameter of about 10 μm or more, it is extremely easy to break and cannot be used practically.
このために、オーバレイのないＳ電極とボンデイングワ
イヤとを重ねて接続する場合に、上記Ｓ電極の径が上記
ボンデイグワイヤの径より小さいときには、上記Ｓ電翫
と上記ポンデイングワイヤとの位置合わせを正確に行う
ことができないので、上記Ｓ電極の面積を小さくしてし
や断周波数Ｆｃの増大を図ることが容易ではなかつた。For this reason, when connecting an S electrode without an overlay and a bonding wire in an overlapping manner, if the diameter of the S electrode is smaller than the diameter of the bonding wire, it is necessary to accurately align the S electrode and the bonding wire. Therefore, it is not easy to increase the shear cutoff frequency Fc by reducing the area of the S electrode.
第２図は半径４μｍ程度の円形のＳ電極上に直径１．０
μｍ程度のボンデイングワイヤを重ね合わせこれを実体
顕微鏡で観察した状態を示す図である。Figure 2 shows a circular S electrode with a radius of about 4 μm and a diameter of 1.0 μm.
It is a diagram showing a state in which bonding wires of about μm size are stacked and observed with a stereomicroscope.
図に示すように、破線で示す半径４μｍ程度のＳ電極３
ａは直径１０μｍ程度のボンデイングワイヤ５ａの影に
隠れて観察することができないので、作業者の熟練によ
る勘にたよつて、Ｓ電極３ａの真上と思われるポンチイ
ンクワイア５ａの部分にポンチインク用ウエツジを押し
つけてＳ電極３ａとボンデイングワイヤ５ａとを接続し
ていた。このように、ポンチインクワイアとこれより小
さい直径のＳ電極とを接続する作業は上記Ｓ電極の面積
を小さくしてしや断周波数Ｆｃの増大を図る上で大きな
障害になつていた。ところで、発明者らの行なつた実験
結果によれば半導体基板のＳ電極の周辺部にこの半導体
基板と反対の伝導形のガードリング層を設けることによ
つて、逆方向リーク電流の少ないＳ電極を上記半導体基
板上に形成し得るので、必ずしもＳ電極の形状を円にす
る必要のないことが確認された。As shown in the figure, an S electrode 3 with a radius of about 4 μm indicated by a broken line
Since point a cannot be observed because it is hidden in the shadow of the bonding wire 5a, which has a diameter of about 10 μm, the operator relied on his/her experienced intuition to place the punch ink on the part of the punch ink wire 5a that seemed to be directly above the S electrode 3a. The wedge was pressed to connect the S electrode 3a and the bonding wire 5a. As described above, the work of connecting the punch inquire and the S electrode having a smaller diameter has been a major obstacle in reducing the area of the S electrode and increasing the shear cutting frequency Fc. By the way, according to the experimental results conducted by the inventors, by providing a guard ring layer of a conductivity type opposite to that of the semiconductor substrate around the S electrode of the semiconductor substrate, the S electrode with less reverse leakage current can be formed. It was confirmed that the shape of the S electrode does not necessarily have to be circular because it can be formed on the semiconductor substrate.
この発明は、上述の実験結果にもとずいてなされたもの
で、電極が通常の円形ならばこの上にボンデイングすべ
く重ね合わせたボンディングワイヤに隠れて重ね合わせ
状態の識別困難な上記電極を同一面積に保持しつつ変形
して上記ボンデイングワイヤの側面から一部が露出する
ような所定形状にすることによつて、上記電極と上記ボ
ンデイングワイヤとの位置合わせを精度よく行い得るよ
うにして、上記電極の面積の減少を図り、その高周波特
性の向上を図り得る超高周波用半導体装置を提供するこ
とを目的とする。第３図はこの発明による一実施例のダ
円形状のＳ電極の上にボンデイングワイヤを重ね合わせ
、これを実体顕微鏡で観察した状態を説明するための図
である。This invention was made based on the above-mentioned experimental results, and if the electrode is a normal circular shape, the above-mentioned electrode is hidden by the bonding wire that is overlapped to be bonded on top of it, making it difficult to identify the overlapping state. By deforming the bonding wire to a predetermined shape such that a portion thereof is exposed from the side surface of the bonding wire while maintaining the same area, the electrode and the bonding wire can be precisely aligned. It is an object of the present invention to provide a super high frequency semiconductor device that can reduce the area of electrodes and improve its high frequency characteristics. FIG. 3 is a diagram for explaining a state in which a bonding wire is superimposed on a circular S electrode according to an embodiment of the present invention, and the bonding wire is observed using a stereoscopic microscope.
図において、３ｂはこの実施例のＳ電極で、第２図に示
したＳ電極３ａと同一面積のダ円形である。In the figure, 3b is the S electrode of this embodiment, which has a circular shape with the same area as the S electrode 3a shown in FIG.
このＳ電極３ｂの短径と平行にボンデイングワイヤ５ａ
が重ねてある。そこで、Ｓ電極３ｂの長径２Ｒ１を直径
１０μｍ程度のボンデイングワイヤ５ａの両側へそれぞ
れ長さＤｌ，Ｄ２だけ露見するようにすると、これらの
長さＤｌ，Ｄ２をそれぞれ実体顕微鏡で目測しながら、
Ｓ電極３ｂとボンデイングワイヤ５ａとを正確に位置合
わせすることができる。実際の作業では１００倍前後の
倍率の実体顕微鏡を使用するので、確認できる長さ（Ｄ
，＋Ｄ２）として、Ｄ１＋Ｄ２≧１．０μｍが必要であ
る。一方、ボンデイングワイヤの直径が実用上１０ｐｍ
程度以上ないと切れ易く使用できないため、Ｓ電極３ｂ
の長径２Ｒ１の限界は次式のようになる。２Ｒ１≧１０
μｍ＋１μｍ＝１１μｍ・・・・・・・・・〔１〕とこ
ろが、Ｓ電極３ｂの長径２Ｒ１をどんどん長くすると、
Ｓ電極３ｂのボンデイングワイヤ５ａの両側から露出す
る長さＤｌ，Ｄ２は大きくなり、Ｓ電極３ｂとボンデイ
ングワイヤ５ａとの位置合わせが容易になるが、Ｓ電極
３ｂの短径２Ｒ２が短かくなりすぎて、ボンデイングワ
イヤ５ａとＳ電極３ｂとの接触面積が小さくなり、ボン
デイングワイヤ５ａの直列抵抗の増加を引きおこすこと
になる。A bonding wire 5a is placed parallel to the short axis of this S electrode 3b.
are stacked on top of each other. Therefore, if the long axis 2R1 of the S electrode 3b is exposed on both sides of the bonding wire 5a having a diameter of about 10 μm by lengths Dl and D2, respectively, while visually measuring these lengths Dl and D2 with a stereomicroscope,
The S electrode 3b and the bonding wire 5a can be accurately aligned. In actual work, a stereo microscope with a magnification of around 100x is used, so the length that can be confirmed (D
, +D2), it is necessary that D1+D2≧1.0 μm. On the other hand, the diameter of the bonding wire is practically 10 pm.
If the S electrode 3b is
The limit of the major axis 2R1 is as shown in the following equation. 2R1≧10
μm+1μm=11μm・・・・・・・・・[1] However, if the long diameter 2R1 of the S electrode 3b is made longer and longer,
The lengths Dl and D2 of the S electrode 3b exposed from both sides of the bonding wire 5a become larger, making it easier to align the S electrode 3b and the bonding wire 5a, but the minor axis 2R2 of the S electrode 3b becomes too short. As a result, the contact area between the bonding wire 5a and the S electrode 3b becomes smaller, causing an increase in the series resistance of the bonding wire 5a.
したがつて、Ｓ電極３ｂを形成するための通常の写真製
版の精度を考慮に入れて、Ｓ電極３ｂの短径２Ｒ２の限
界は次のようになる。２Ｒ２−＞４μｍ ・・・・・
・・・・・・・・・・・・・ 〔〕ところで、上記〔１
〕式および〔〕式の条件を満たすダ円形のＳ電極と同一
面積の円形のＳ電極の直径２Ｒ０の限界は次のようにな
る。Therefore, taking into account the accuracy of normal photolithography for forming the S electrode 3b, the limit of the short diameter 2R2 of the S electrode 3b is as follows. 2R2->4μm・・・・・・
・・・・・・・・・・・・ [] By the way, the above [1]
The limit of the diameter 2R0 of a circular S electrode having the same area as the circular S electrode that satisfies the conditions of formulas [] and [] is as follows.
上述のように、実用上の使用限界である１．０μｍ程度
の直径のボンデイングワイヤとこのボンデイングワイヤ
の断面積より小さい面積のＳ電極との位置合わせを精度
よく行うことができる。As described above, it is possible to accurately align the bonding wire with a diameter of about 1.0 μm, which is the limit of practical use, and the S electrode with an area smaller than the cross-sectional area of the bonding wire.
よつて、この実施例のＳ電極３ｂでは、上記〔ｌ〕式を
満たす直径２Ｒ０の円面積までＳ電極３ｂの面積の減少
を図り、そのしや断周波数Ｆｃの増大を容易に図り得る
シヨツキダイオードを提供することができる。第４図は
この発明による他の実施例のＳ電極の上にボンデイング
ワイヤを重ね合わせ、これを実体顕微鏡で観察した状態
を示す図である。Therefore, in the S electrode 3b of this embodiment, it is possible to reduce the area of the S electrode 3b to a circular area of diameter 2R0 that satisfies the above formula [l], and to easily increase the shear cut-off frequency Fc. A diode can be provided. FIG. 4 is a diagram showing a state in which a bonding wire is superimposed on the S electrode of another embodiment of the present invention, and this is observed with a stereoscopic microscope.
図において、３ｃはこの実施例のＳ電極で、このＳ電極
３ｃは半円形と長方形とを組合わせた形状であるほかは
、第３図に示したＳ電極３ｂと同様である。In the figure, 3c is the S electrode of this embodiment, and this S electrode 3c is the same as the S electrode 3b shown in FIG. 3, except that it has a shape that is a combination of a semicircle and a rectangle.
したがつて、Ｓ電極３ｃの効果もＳ電極３ｂと同様であ
ることは容易に理解できよう。なお、これまで、微少な
Ｓ電極を有するシヨツトキダイオードについて述べてき
たが、この発明はこれに限らず、この他のＰｎ接合電極
もしくはオーミツク電極などの微少な電極を有する超高
周波用半導体装置にも適用することができる。以上、説
明したように、この発明によれば、半導体基体の主面上
に設けられた電極が通常の円形ならばこの上にボンデイ
ングすべく重ね合わせたボンデイングワイヤに隠れて重
ね合わせ状態の識別困難なものにおいて、上記電極を同
一面積に保持しつつ上記ボンデイングワイヤの側面から
一部が露出するような所定形状にしてあるので、゛上記
電極と上記ボンデイングワイヤとの位置合わせを精度よ
く行うことができる。よつて、上記電極の面積の減少を
図り、その高周波特性の向上を図り得る超高周波用半導
体装置を提供することができる。Therefore, it can be easily understood that the effect of the S electrode 3c is also the same as that of the S electrode 3b. Although the Schottky diode having a minute S electrode has been described so far, the present invention is not limited to this, and can be applied to ultra-high frequency semiconductor devices having minute electrodes such as other Pn junction electrodes or ohmic electrodes. can also be applied. As explained above, according to the present invention, if the electrode provided on the main surface of the semiconductor substrate is a normal circle, it will be hidden by the bonding wire that is overlapped to be bonded thereon, making it difficult to identify the overlapping state. In the present invention, the electrodes are held in the same area and are shaped in a predetermined manner such that a portion thereof is exposed from the side surface of the bonding wire, so that the electrodes and the bonding wire can be precisely aligned. can. Therefore, it is possible to provide an ultra-high frequency semiconductor device that can reduce the area of the electrode and improve its high frequency characteristics.
第１図はシヨツトキダイオードのオーバレイ構造のＳ電
極を説明するための断面図、第２図は半径４μｍ程度の
円形のＳ電極上に直径１０μｍ程度のボンデイングワイ
ヤを重ね合わせ、これを実体顕微鏡で観察した状態を示
す図、第３図はこの発明による一実施例のＳ電極の上に
ボンデイングワイヤを重ね合わせ、これを実体顕微鏡で
観察した状態を説明するための図、第４図はこの発明に
よる他の実施例のＳ電極の上にボンデイングワイヤを重
ね合わせ、これを実体顕微鏡で観察した状態を示す図で
ある。
図において、１は半導体基板、２は絶縁保護膜、３，３
ａ，３ｂ，３ｃはそれぞれＳ電極、４はボンデイング用
電極、５，５ａはそれぞれボンデイングワイヤを示す。Figure 1 is a cross-sectional view to explain the S electrode of the overlay structure of the Schottky diode, and Figure 2 is a circular S electrode with a radius of approximately 4 μm overlaid with a bonding wire of approximately 10 μm in diameter, which is examined using a stereomicroscope. A diagram showing the observed state, FIG. 3 is a diagram for explaining the state in which a bonding wire is superimposed on the S electrode of an embodiment of the present invention, and observed with a stereomicroscope, and FIG. 4 is a diagram showing the state observed with a stereomicroscope. FIG. 7 is a diagram showing a state in which a bonding wire is superimposed on the S electrode of another example according to the present invention, and the bonding wire is observed with a stereoscopic microscope. In the figure, 1 is a semiconductor substrate, 2 is an insulating protective film, 3, 3
a, 3b, and 3c are S electrodes, 4 is a bonding electrode, and 5 and 5a are bonding wires, respectively.
Claims (1)
ならばこの上にボンディングすべく重ね合わせたボンデ
ィングワイヤに隠れて重ね合わせ状態の識別困難なもの
において、上記電極を同一面積に保持しつつ変形して上
記ボンディングワイヤの側面から一部が露出するような
所定形状としたことを特徴とする超音周波用半導体装置
。 ２ 電極がショットキ接合電極であることを特徴とする
特許請求の範囲第１項記載の超高周波用半導体装置。 ３ 電極の形状をダ円形状にしたことを特徴とする特許
請求の範囲第１項記載の超高周波用半導体装置。[Scope of Claims] 1. If the electrode provided on the main surface of the semiconductor substrate is a normal circular shape, the electrode is hidden by the bonding wire overlaid to be bonded thereon, making it difficult to identify the overlapping state. An ultrasonic frequency semiconductor device characterized in that the bonding wire is deformed into a predetermined shape such that a portion thereof is exposed from the side surface of the bonding wire while maintaining the same area. 2. The super high frequency semiconductor device according to claim 1, wherein the electrode is a Schottky junction electrode. 3. The super high frequency semiconductor device according to claim 1, wherein the electrode has a circular shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53023248A JPS5923113B2 (en) | 1978-02-28 | 1978-02-28 | Semiconductor equipment for ultra-high frequencies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53023248A JPS5923113B2 (en) | 1978-02-28 | 1978-02-28 | Semiconductor equipment for ultra-high frequencies |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54115067A JPS54115067A (en) | 1979-09-07 |
| JPS5923113B2 true JPS5923113B2 (en) | 1984-05-30 |
Family
ID=12105287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53023248A Expired JPS5923113B2 (en) | 1978-02-28 | 1978-02-28 | Semiconductor equipment for ultra-high frequencies |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923113B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018074404A1 (en) | 2016-10-17 | 2018-04-26 | アドバンスト・ソフトマテリアルズ株式会社 | Spherical powder containing crosslinked body formed having polyrotaxane, and method for producing same |
-
1978
- 1978-02-28 JP JP53023248A patent/JPS5923113B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018074404A1 (en) | 2016-10-17 | 2018-04-26 | アドバンスト・ソフトマテリアルズ株式会社 | Spherical powder containing crosslinked body formed having polyrotaxane, and method for producing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54115067A (en) | 1979-09-07 |
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